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1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3define <8 x i8> @vabss8(ptr %A) nounwind {4;CHECK-LABEL: vabss8:5;CHECK: vabs.s86 %tmp1 = load <8 x i8>, ptr %A7 %tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1)8 ret <8 x i8> %tmp29}10 11define <8 x i8> @vabss8_fold(ptr %A) nounwind {12; CHECK-LABEL: vabss8_fold:13; CHECK: vldr d16, .LCPI1_014; CHECK: .LCPI1_0:15; CHECK-NEXT: .byte 128 @ 0x8016; CHECK-NEXT: .byte 127 @ 0x7f17; CHECK-NEXT: .byte 1 @ 0x118; CHECK-NEXT: .byte 0 @ 0x019; CHECK-NEXT: .byte 1 @ 0x120; CHECK-NEXT: .byte 127 @ 0x7f21; CHECK-NEXT: .byte 128 @ 0x8022; CHECK-NEXT: .byte 1 @ 0x123 %tmp1 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> <i8 -128, i8 -127, i8 -1, i8 0, i8 1, i8 127, i8 128, i8 255>)24 ret <8 x i8> %tmp125}26 27define <4 x i16> @vabss16(ptr %A) nounwind {28;CHECK-LABEL: vabss16:29;CHECK: vabs.s1630 %tmp1 = load <4 x i16>, ptr %A31 %tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1)32 ret <4 x i16> %tmp233}34 35define <4 x i16> @vabss16_fold() nounwind {36; CHECK-LABEL: vabss16_fold:37; CHECK: vldr d16, .LCPI3_038; CHECK: .LCPI3_0:39; CHECK-NEXT: .short 32768 @ 0x800040; CHECK-NEXT: .short 32767 @ 0x7fff41; CHECK-NEXT: .short 255 @ 0xff42; CHECK-NEXT: .short 32768 @ 0x800043 %tmp1 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> <i16 -32768, i16 -32767, i16 255, i16 32768>)44 ret <4 x i16> %tmp145}46 47define <2 x i32> @vabss32(ptr %A) nounwind {48;CHECK-LABEL: vabss32:49;CHECK: vabs.s3250 %tmp1 = load <2 x i32>, ptr %A51 %tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1)52 ret <2 x i32> %tmp253}54 55define <2 x i32> @vabss32_fold() nounwind {56; CHECK-LABEL: vabss32_fold:57; CHECK: vldr d16, .LCPI5_058; CHECK: .LCPI5_0:59; CHECK-NEXT: .long 2147483647 @ 0x7fffffff60; CHECK-NEXT: .long 2147483648 @ 0x8000000061 %tmp1 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> <i32 -2147483647, i32 2147483648>)62 ret <2 x i32> %tmp163}64 65define <2 x float> @vabsf32(ptr %A) nounwind {66;CHECK-LABEL: vabsf32:67;CHECK: vabs.f3268 %tmp1 = load <2 x float>, ptr %A69 %tmp2 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %tmp1)70 ret <2 x float> %tmp271}72 73define <16 x i8> @vabsQs8(ptr %A) nounwind {74;CHECK-LABEL: vabsQs8:75;CHECK: vabs.s876 %tmp1 = load <16 x i8>, ptr %A77 %tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1)78 ret <16 x i8> %tmp279}80 81define <8 x i16> @vabsQs16(ptr %A) nounwind {82;CHECK-LABEL: vabsQs16:83;CHECK: vabs.s1684 %tmp1 = load <8 x i16>, ptr %A85 %tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1)86 ret <8 x i16> %tmp287}88 89define <4 x i32> @vabsQs32(ptr %A) nounwind {90;CHECK-LABEL: vabsQs32:91;CHECK: vabs.s3292 %tmp1 = load <4 x i32>, ptr %A93 %tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1)94 ret <4 x i32> %tmp295}96 97define <4 x float> @vabsQf32(ptr %A) nounwind {98;CHECK-LABEL: vabsQf32:99;CHECK: vabs.f32100 %tmp1 = load <4 x float>, ptr %A101 %tmp2 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %tmp1)102 ret <4 x float> %tmp2103}104 105declare <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8>) nounwind readnone106declare <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16>) nounwind readnone107declare <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32>) nounwind readnone108declare <2 x float> @llvm.fabs.v2f32(<2 x float>) nounwind readnone109 110declare <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8>) nounwind readnone111declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone112declare <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32>) nounwind readnone113declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone114 115define <8 x i8> @vqabss8(ptr %A) nounwind {116;CHECK-LABEL: vqabss8:117;CHECK: vqabs.s8118 %tmp1 = load <8 x i8>, ptr %A119 %tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1)120 ret <8 x i8> %tmp2121}122 123define <4 x i16> @vqabss16(ptr %A) nounwind {124;CHECK-LABEL: vqabss16:125;CHECK: vqabs.s16126 %tmp1 = load <4 x i16>, ptr %A127 %tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1)128 ret <4 x i16> %tmp2129}130 131define <2 x i32> @vqabss32(ptr %A) nounwind {132;CHECK-LABEL: vqabss32:133;CHECK: vqabs.s32134 %tmp1 = load <2 x i32>, ptr %A135 %tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1)136 ret <2 x i32> %tmp2137}138 139define <16 x i8> @vqabsQs8(ptr %A) nounwind {140;CHECK-LABEL: vqabsQs8:141;CHECK: vqabs.s8142 %tmp1 = load <16 x i8>, ptr %A143 %tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1)144 ret <16 x i8> %tmp2145}146 147define <8 x i16> @vqabsQs16(ptr %A) nounwind {148;CHECK-LABEL: vqabsQs16:149;CHECK: vqabs.s16150 %tmp1 = load <8 x i16>, ptr %A151 %tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1)152 ret <8 x i16> %tmp2153}154 155define <4 x i32> @vqabsQs32(ptr %A) nounwind {156;CHECK-LABEL: vqabsQs32:157;CHECK: vqabs.s32158 %tmp1 = load <4 x i32>, ptr %A159 %tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1)160 ret <4 x i32> %tmp2161}162 163declare <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8>) nounwind readnone164declare <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16>) nounwind readnone165declare <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32>) nounwind readnone166 167declare <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8>) nounwind readnone168declare <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16>) nounwind readnone169declare <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32>) nounwind readnone170