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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a8 | FileCheck %s3 4define <8 x i8> @v_andi8(ptr %A, ptr %B) nounwind {5; CHECK-LABEL: v_andi8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vldr d16, [r1]8; CHECK-NEXT: vldr d17, [r0]9; CHECK-NEXT: vand d16, d17, d1610; CHECK-NEXT: vmov r0, r1, d1611; CHECK-NEXT: bx lr12 %tmp1 = load <8 x i8>, ptr %A13 %tmp2 = load <8 x i8>, ptr %B14 %tmp3 = and <8 x i8> %tmp1, %tmp215 ret <8 x i8> %tmp316}17 18define <4 x i16> @v_andi16(ptr %A, ptr %B) nounwind {19; CHECK-LABEL: v_andi16:20; CHECK: @ %bb.0:21; CHECK-NEXT: vldr d16, [r1]22; CHECK-NEXT: vldr d17, [r0]23; CHECK-NEXT: vand d16, d17, d1624; CHECK-NEXT: vmov r0, r1, d1625; CHECK-NEXT: bx lr26 %tmp1 = load <4 x i16>, ptr %A27 %tmp2 = load <4 x i16>, ptr %B28 %tmp3 = and <4 x i16> %tmp1, %tmp229 ret <4 x i16> %tmp330}31 32define <2 x i32> @v_andi32(ptr %A, ptr %B) nounwind {33; CHECK-LABEL: v_andi32:34; CHECK: @ %bb.0:35; CHECK-NEXT: vldr d16, [r1]36; CHECK-NEXT: vldr d17, [r0]37; CHECK-NEXT: vand d16, d17, d1638; CHECK-NEXT: vmov r0, r1, d1639; CHECK-NEXT: bx lr40 %tmp1 = load <2 x i32>, ptr %A41 %tmp2 = load <2 x i32>, ptr %B42 %tmp3 = and <2 x i32> %tmp1, %tmp243 ret <2 x i32> %tmp344}45 46define <1 x i64> @v_andi64(ptr %A, ptr %B) nounwind {47; CHECK-LABEL: v_andi64:48; CHECK: @ %bb.0:49; CHECK-NEXT: vldr d16, [r1]50; CHECK-NEXT: vldr d17, [r0]51; CHECK-NEXT: vand d16, d17, d1652; CHECK-NEXT: vmov r0, r1, d1653; CHECK-NEXT: bx lr54 %tmp1 = load <1 x i64>, ptr %A55 %tmp2 = load <1 x i64>, ptr %B56 %tmp3 = and <1 x i64> %tmp1, %tmp257 ret <1 x i64> %tmp358}59 60define <16 x i8> @v_andQi8(ptr %A, ptr %B) nounwind {61; CHECK-LABEL: v_andQi8:62; CHECK: @ %bb.0:63; CHECK-NEXT: vld1.64 {d16, d17}, [r1]64; CHECK-NEXT: vld1.64 {d18, d19}, [r0]65; CHECK-NEXT: vand q8, q9, q866; CHECK-NEXT: vmov r0, r1, d1667; CHECK-NEXT: vmov r2, r3, d1768; CHECK-NEXT: bx lr69 %tmp1 = load <16 x i8>, ptr %A70 %tmp2 = load <16 x i8>, ptr %B71 %tmp3 = and <16 x i8> %tmp1, %tmp272 ret <16 x i8> %tmp373}74 75define <8 x i16> @v_andQi16(ptr %A, ptr %B) nounwind {76; CHECK-LABEL: v_andQi16:77; CHECK: @ %bb.0:78; CHECK-NEXT: vld1.64 {d16, d17}, [r1]79; CHECK-NEXT: vld1.64 {d18, d19}, [r0]80; CHECK-NEXT: vand q8, q9, q881; CHECK-NEXT: vmov r0, r1, d1682; CHECK-NEXT: vmov r2, r3, d1783; CHECK-NEXT: bx lr84 %tmp1 = load <8 x i16>, ptr %A85 %tmp2 = load <8 x i16>, ptr %B86 %tmp3 = and <8 x i16> %tmp1, %tmp287 ret <8 x i16> %tmp388}89 90define <4 x i32> @v_andQi32(ptr %A, ptr %B) nounwind {91; CHECK-LABEL: v_andQi32:92; CHECK: @ %bb.0:93; CHECK-NEXT: vld1.64 {d16, d17}, [r1]94; CHECK-NEXT: vld1.64 {d18, d19}, [r0]95; CHECK-NEXT: vand q8, q9, q896; CHECK-NEXT: vmov r0, r1, d1697; CHECK-NEXT: vmov r2, r3, d1798; CHECK-NEXT: bx lr99 %tmp1 = load <4 x i32>, ptr %A100 %tmp2 = load <4 x i32>, ptr %B101 %tmp3 = and <4 x i32> %tmp1, %tmp2102 ret <4 x i32> %tmp3103}104 105define <2 x i64> @v_andQi64(ptr %A, ptr %B) nounwind {106; CHECK-LABEL: v_andQi64:107; CHECK: @ %bb.0:108; CHECK-NEXT: vld1.64 {d16, d17}, [r1]109; CHECK-NEXT: vld1.64 {d18, d19}, [r0]110; CHECK-NEXT: vand q8, q9, q8111; CHECK-NEXT: vmov r0, r1, d16112; CHECK-NEXT: vmov r2, r3, d17113; CHECK-NEXT: bx lr114 %tmp1 = load <2 x i64>, ptr %A115 %tmp2 = load <2 x i64>, ptr %B116 %tmp3 = and <2 x i64> %tmp1, %tmp2117 ret <2 x i64> %tmp3118}119 120define <8 x i8> @v_bici8(ptr %A, ptr %B) nounwind {121; CHECK-LABEL: v_bici8:122; CHECK: @ %bb.0:123; CHECK-NEXT: vldr d16, [r1]124; CHECK-NEXT: vldr d17, [r0]125; CHECK-NEXT: vbic d16, d17, d16126; CHECK-NEXT: vmov r0, r1, d16127; CHECK-NEXT: bx lr128 %tmp1 = load <8 x i8>, ptr %A129 %tmp2 = load <8 x i8>, ptr %B130 %tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >131 %tmp4 = and <8 x i8> %tmp1, %tmp3132 ret <8 x i8> %tmp4133}134 135define <4 x i16> @v_bici16(ptr %A, ptr %B) nounwind {136; CHECK-LABEL: v_bici16:137; CHECK: @ %bb.0:138; CHECK-NEXT: vldr d16, [r1]139; CHECK-NEXT: vldr d17, [r0]140; CHECK-NEXT: vbic d16, d17, d16141; CHECK-NEXT: vmov r0, r1, d16142; CHECK-NEXT: bx lr143 %tmp1 = load <4 x i16>, ptr %A144 %tmp2 = load <4 x i16>, ptr %B145 %tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 >146 %tmp4 = and <4 x i16> %tmp1, %tmp3147 ret <4 x i16> %tmp4148}149 150define <2 x i32> @v_bici32(ptr %A, ptr %B) nounwind {151; CHECK-LABEL: v_bici32:152; CHECK: @ %bb.0:153; CHECK-NEXT: vldr d16, [r1]154; CHECK-NEXT: vldr d17, [r0]155; CHECK-NEXT: vbic d16, d17, d16156; CHECK-NEXT: vmov r0, r1, d16157; CHECK-NEXT: bx lr158 %tmp1 = load <2 x i32>, ptr %A159 %tmp2 = load <2 x i32>, ptr %B160 %tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 >161 %tmp4 = and <2 x i32> %tmp1, %tmp3162 ret <2 x i32> %tmp4163}164 165define <1 x i64> @v_bici64(ptr %A, ptr %B) nounwind {166; CHECK-LABEL: v_bici64:167; CHECK: @ %bb.0:168; CHECK-NEXT: vldr d16, [r1]169; CHECK-NEXT: vldr d17, [r0]170; CHECK-NEXT: vbic d16, d17, d16171; CHECK-NEXT: vmov r0, r1, d16172; CHECK-NEXT: bx lr173 %tmp1 = load <1 x i64>, ptr %A174 %tmp2 = load <1 x i64>, ptr %B175 %tmp3 = xor <1 x i64> %tmp2, < i64 -1 >176 %tmp4 = and <1 x i64> %tmp1, %tmp3177 ret <1 x i64> %tmp4178}179 180define <16 x i8> @v_bicQi8(ptr %A, ptr %B) nounwind {181; CHECK-LABEL: v_bicQi8:182; CHECK: @ %bb.0:183; CHECK-NEXT: vld1.64 {d16, d17}, [r1]184; CHECK-NEXT: vld1.64 {d18, d19}, [r0]185; CHECK-NEXT: vbic q8, q9, q8186; CHECK-NEXT: vmov r0, r1, d16187; CHECK-NEXT: vmov r2, r3, d17188; CHECK-NEXT: bx lr189 %tmp1 = load <16 x i8>, ptr %A190 %tmp2 = load <16 x i8>, ptr %B191 %tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >192 %tmp4 = and <16 x i8> %tmp1, %tmp3193 ret <16 x i8> %tmp4194}195 196define <8 x i16> @v_bicQi16(ptr %A, ptr %B) nounwind {197; CHECK-LABEL: v_bicQi16:198; CHECK: @ %bb.0:199; CHECK-NEXT: vld1.64 {d16, d17}, [r1]200; CHECK-NEXT: vld1.64 {d18, d19}, [r0]201; CHECK-NEXT: vbic q8, q9, q8202; CHECK-NEXT: vmov r0, r1, d16203; CHECK-NEXT: vmov r2, r3, d17204; CHECK-NEXT: bx lr205 %tmp1 = load <8 x i16>, ptr %A206 %tmp2 = load <8 x i16>, ptr %B207 %tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >208 %tmp4 = and <8 x i16> %tmp1, %tmp3209 ret <8 x i16> %tmp4210}211 212define <4 x i32> @v_bicQi32(ptr %A, ptr %B) nounwind {213; CHECK-LABEL: v_bicQi32:214; CHECK: @ %bb.0:215; CHECK-NEXT: vld1.64 {d16, d17}, [r1]216; CHECK-NEXT: vld1.64 {d18, d19}, [r0]217; CHECK-NEXT: vbic q8, q9, q8218; CHECK-NEXT: vmov r0, r1, d16219; CHECK-NEXT: vmov r2, r3, d17220; CHECK-NEXT: bx lr221 %tmp1 = load <4 x i32>, ptr %A222 %tmp2 = load <4 x i32>, ptr %B223 %tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 >224 %tmp4 = and <4 x i32> %tmp1, %tmp3225 ret <4 x i32> %tmp4226}227 228define <2 x i64> @v_bicQi64(ptr %A, ptr %B) nounwind {229; CHECK-LABEL: v_bicQi64:230; CHECK: @ %bb.0:231; CHECK-NEXT: vld1.64 {d16, d17}, [r1]232; CHECK-NEXT: vld1.64 {d18, d19}, [r0]233; CHECK-NEXT: vbic q8, q9, q8234; CHECK-NEXT: vmov r0, r1, d16235; CHECK-NEXT: vmov r2, r3, d17236; CHECK-NEXT: bx lr237 %tmp1 = load <2 x i64>, ptr %A238 %tmp2 = load <2 x i64>, ptr %B239 %tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 >240 %tmp4 = and <2 x i64> %tmp1, %tmp3241 ret <2 x i64> %tmp4242}243 244define <8 x i8> @v_eori8(ptr %A, ptr %B) nounwind {245; CHECK-LABEL: v_eori8:246; CHECK: @ %bb.0:247; CHECK-NEXT: vldr d16, [r1]248; CHECK-NEXT: vldr d17, [r0]249; CHECK-NEXT: veor d16, d17, d16250; CHECK-NEXT: vmov r0, r1, d16251; CHECK-NEXT: bx lr252 %tmp1 = load <8 x i8>, ptr %A253 %tmp2 = load <8 x i8>, ptr %B254 %tmp3 = xor <8 x i8> %tmp1, %tmp2255 ret <8 x i8> %tmp3256}257 258define <4 x i16> @v_eori16(ptr %A, ptr %B) nounwind {259; CHECK-LABEL: v_eori16:260; CHECK: @ %bb.0:261; CHECK-NEXT: vldr d16, [r1]262; CHECK-NEXT: vldr d17, [r0]263; CHECK-NEXT: veor d16, d17, d16264; CHECK-NEXT: vmov r0, r1, d16265; CHECK-NEXT: bx lr266 %tmp1 = load <4 x i16>, ptr %A267 %tmp2 = load <4 x i16>, ptr %B268 %tmp3 = xor <4 x i16> %tmp1, %tmp2269 ret <4 x i16> %tmp3270}271 272define <2 x i32> @v_eori32(ptr %A, ptr %B) nounwind {273; CHECK-LABEL: v_eori32:274; CHECK: @ %bb.0:275; CHECK-NEXT: vldr d16, [r1]276; CHECK-NEXT: vldr d17, [r0]277; CHECK-NEXT: veor d16, d17, d16278; CHECK-NEXT: vmov r0, r1, d16279; CHECK-NEXT: bx lr280 %tmp1 = load <2 x i32>, ptr %A281 %tmp2 = load <2 x i32>, ptr %B282 %tmp3 = xor <2 x i32> %tmp1, %tmp2283 ret <2 x i32> %tmp3284}285 286define <1 x i64> @v_eori64(ptr %A, ptr %B) nounwind {287; CHECK-LABEL: v_eori64:288; CHECK: @ %bb.0:289; CHECK-NEXT: vldr d16, [r1]290; CHECK-NEXT: vldr d17, [r0]291; CHECK-NEXT: veor d16, d17, d16292; CHECK-NEXT: vmov r0, r1, d16293; CHECK-NEXT: bx lr294 %tmp1 = load <1 x i64>, ptr %A295 %tmp2 = load <1 x i64>, ptr %B296 %tmp3 = xor <1 x i64> %tmp1, %tmp2297 ret <1 x i64> %tmp3298}299 300define <16 x i8> @v_eorQi8(ptr %A, ptr %B) nounwind {301; CHECK-LABEL: v_eorQi8:302; CHECK: @ %bb.0:303; CHECK-NEXT: vld1.64 {d16, d17}, [r1]304; CHECK-NEXT: vld1.64 {d18, d19}, [r0]305; CHECK-NEXT: veor q8, q9, q8306; CHECK-NEXT: vmov r0, r1, d16307; CHECK-NEXT: vmov r2, r3, d17308; CHECK-NEXT: bx lr309 %tmp1 = load <16 x i8>, ptr %A310 %tmp2 = load <16 x i8>, ptr %B311 %tmp3 = xor <16 x i8> %tmp1, %tmp2312 ret <16 x i8> %tmp3313}314 315define <8 x i16> @v_eorQi16(ptr %A, ptr %B) nounwind {316; CHECK-LABEL: v_eorQi16:317; CHECK: @ %bb.0:318; CHECK-NEXT: vld1.64 {d16, d17}, [r1]319; CHECK-NEXT: vld1.64 {d18, d19}, [r0]320; CHECK-NEXT: veor q8, q9, q8321; CHECK-NEXT: vmov r0, r1, d16322; CHECK-NEXT: vmov r2, r3, d17323; CHECK-NEXT: bx lr324 %tmp1 = load <8 x i16>, ptr %A325 %tmp2 = load <8 x i16>, ptr %B326 %tmp3 = xor <8 x i16> %tmp1, %tmp2327 ret <8 x i16> %tmp3328}329 330define <4 x i32> @v_eorQi32(ptr %A, ptr %B) nounwind {331; CHECK-LABEL: v_eorQi32:332; CHECK: @ %bb.0:333; CHECK-NEXT: vld1.64 {d16, d17}, [r1]334; CHECK-NEXT: vld1.64 {d18, d19}, [r0]335; CHECK-NEXT: veor q8, q9, q8336; CHECK-NEXT: vmov r0, r1, d16337; CHECK-NEXT: vmov r2, r3, d17338; CHECK-NEXT: bx lr339 %tmp1 = load <4 x i32>, ptr %A340 %tmp2 = load <4 x i32>, ptr %B341 %tmp3 = xor <4 x i32> %tmp1, %tmp2342 ret <4 x i32> %tmp3343}344 345define <2 x i64> @v_eorQi64(ptr %A, ptr %B) nounwind {346; CHECK-LABEL: v_eorQi64:347; CHECK: @ %bb.0:348; CHECK-NEXT: vld1.64 {d16, d17}, [r1]349; CHECK-NEXT: vld1.64 {d18, d19}, [r0]350; CHECK-NEXT: veor q8, q9, q8351; CHECK-NEXT: vmov r0, r1, d16352; CHECK-NEXT: vmov r2, r3, d17353; CHECK-NEXT: bx lr354 %tmp1 = load <2 x i64>, ptr %A355 %tmp2 = load <2 x i64>, ptr %B356 %tmp3 = xor <2 x i64> %tmp1, %tmp2357 ret <2 x i64> %tmp3358}359 360define <8 x i8> @v_mvni8(ptr %A) nounwind {361; CHECK-LABEL: v_mvni8:362; CHECK: @ %bb.0:363; CHECK-NEXT: vldr d16, [r0]364; CHECK-NEXT: vmvn d16, d16365; CHECK-NEXT: vmov r0, r1, d16366; CHECK-NEXT: bx lr367 %tmp1 = load <8 x i8>, ptr %A368 %tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >369 ret <8 x i8> %tmp2370}371 372define <4 x i16> @v_mvni16(ptr %A) nounwind {373; CHECK-LABEL: v_mvni16:374; CHECK: @ %bb.0:375; CHECK-NEXT: vldr d16, [r0]376; CHECK-NEXT: vmvn d16, d16377; CHECK-NEXT: vmov r0, r1, d16378; CHECK-NEXT: bx lr379 %tmp1 = load <4 x i16>, ptr %A380 %tmp2 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 >381 ret <4 x i16> %tmp2382}383 384define <2 x i32> @v_mvni32(ptr %A) nounwind {385; CHECK-LABEL: v_mvni32:386; CHECK: @ %bb.0:387; CHECK-NEXT: vldr d16, [r0]388; CHECK-NEXT: vmvn d16, d16389; CHECK-NEXT: vmov r0, r1, d16390; CHECK-NEXT: bx lr391 %tmp1 = load <2 x i32>, ptr %A392 %tmp2 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 >393 ret <2 x i32> %tmp2394}395 396define <1 x i64> @v_mvni64(ptr %A) nounwind {397; CHECK-LABEL: v_mvni64:398; CHECK: @ %bb.0:399; CHECK-NEXT: vldr d16, [r0]400; CHECK-NEXT: vmvn d16, d16401; CHECK-NEXT: vmov r0, r1, d16402; CHECK-NEXT: bx lr403 %tmp1 = load <1 x i64>, ptr %A404 %tmp2 = xor <1 x i64> %tmp1, < i64 -1 >405 ret <1 x i64> %tmp2406}407 408define <16 x i8> @v_mvnQi8(ptr %A) nounwind {409; CHECK-LABEL: v_mvnQi8:410; CHECK: @ %bb.0:411; CHECK-NEXT: vld1.64 {d16, d17}, [r0]412; CHECK-NEXT: vmvn q8, q8413; CHECK-NEXT: vmov r0, r1, d16414; CHECK-NEXT: vmov r2, r3, d17415; CHECK-NEXT: bx lr416 %tmp1 = load <16 x i8>, ptr %A417 %tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >418 ret <16 x i8> %tmp2419}420 421define <8 x i16> @v_mvnQi16(ptr %A) nounwind {422; CHECK-LABEL: v_mvnQi16:423; CHECK: @ %bb.0:424; CHECK-NEXT: vld1.64 {d16, d17}, [r0]425; CHECK-NEXT: vmvn q8, q8426; CHECK-NEXT: vmov r0, r1, d16427; CHECK-NEXT: vmov r2, r3, d17428; CHECK-NEXT: bx lr429 %tmp1 = load <8 x i16>, ptr %A430 %tmp2 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >431 ret <8 x i16> %tmp2432}433 434define <4 x i32> @v_mvnQi32(ptr %A) nounwind {435; CHECK-LABEL: v_mvnQi32:436; CHECK: @ %bb.0:437; CHECK-NEXT: vld1.64 {d16, d17}, [r0]438; CHECK-NEXT: vmvn q8, q8439; CHECK-NEXT: vmov r0, r1, d16440; CHECK-NEXT: vmov r2, r3, d17441; CHECK-NEXT: bx lr442 %tmp1 = load <4 x i32>, ptr %A443 %tmp2 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 >444 ret <4 x i32> %tmp2445}446 447define <2 x i64> @v_mvnQi64(ptr %A) nounwind {448; CHECK-LABEL: v_mvnQi64:449; CHECK: @ %bb.0:450; CHECK-NEXT: vld1.64 {d16, d17}, [r0]451; CHECK-NEXT: vmvn q8, q8452; CHECK-NEXT: vmov r0, r1, d16453; CHECK-NEXT: vmov r2, r3, d17454; CHECK-NEXT: bx lr455 %tmp1 = load <2 x i64>, ptr %A456 %tmp2 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 >457 ret <2 x i64> %tmp2458}459 460define <8 x i8> @v_orri8(ptr %A, ptr %B) nounwind {461; CHECK-LABEL: v_orri8:462; CHECK: @ %bb.0:463; CHECK-NEXT: vldr d16, [r1]464; CHECK-NEXT: vldr d17, [r0]465; CHECK-NEXT: vorr d16, d17, d16466; CHECK-NEXT: vmov r0, r1, d16467; CHECK-NEXT: bx lr468 %tmp1 = load <8 x i8>, ptr %A469 %tmp2 = load <8 x i8>, ptr %B470 %tmp3 = or <8 x i8> %tmp1, %tmp2471 ret <8 x i8> %tmp3472}473 474define <4 x i16> @v_orri16(ptr %A, ptr %B) nounwind {475; CHECK-LABEL: v_orri16:476; CHECK: @ %bb.0:477; CHECK-NEXT: vldr d16, [r1]478; CHECK-NEXT: vldr d17, [r0]479; CHECK-NEXT: vorr d16, d17, d16480; CHECK-NEXT: vmov r0, r1, d16481; CHECK-NEXT: bx lr482 %tmp1 = load <4 x i16>, ptr %A483 %tmp2 = load <4 x i16>, ptr %B484 %tmp3 = or <4 x i16> %tmp1, %tmp2485 ret <4 x i16> %tmp3486}487 488define <2 x i32> @v_orri32(ptr %A, ptr %B) nounwind {489; CHECK-LABEL: v_orri32:490; CHECK: @ %bb.0:491; CHECK-NEXT: vldr d16, [r1]492; CHECK-NEXT: vldr d17, [r0]493; CHECK-NEXT: vorr d16, d17, d16494; CHECK-NEXT: vmov r0, r1, d16495; CHECK-NEXT: bx lr496 %tmp1 = load <2 x i32>, ptr %A497 %tmp2 = load <2 x i32>, ptr %B498 %tmp3 = or <2 x i32> %tmp1, %tmp2499 ret <2 x i32> %tmp3500}501 502define <1 x i64> @v_orri64(ptr %A, ptr %B) nounwind {503; CHECK-LABEL: v_orri64:504; CHECK: @ %bb.0:505; CHECK-NEXT: vldr d16, [r1]506; CHECK-NEXT: vldr d17, [r0]507; CHECK-NEXT: vorr d16, d17, d16508; CHECK-NEXT: vmov r0, r1, d16509; CHECK-NEXT: bx lr510 %tmp1 = load <1 x i64>, ptr %A511 %tmp2 = load <1 x i64>, ptr %B512 %tmp3 = or <1 x i64> %tmp1, %tmp2513 ret <1 x i64> %tmp3514}515 516define <16 x i8> @v_orrQi8(ptr %A, ptr %B) nounwind {517; CHECK-LABEL: v_orrQi8:518; CHECK: @ %bb.0:519; CHECK-NEXT: vld1.64 {d16, d17}, [r1]520; CHECK-NEXT: vld1.64 {d18, d19}, [r0]521; CHECK-NEXT: vorr q8, q9, q8522; CHECK-NEXT: vmov r0, r1, d16523; CHECK-NEXT: vmov r2, r3, d17524; CHECK-NEXT: bx lr525 %tmp1 = load <16 x i8>, ptr %A526 %tmp2 = load <16 x i8>, ptr %B527 %tmp3 = or <16 x i8> %tmp1, %tmp2528 ret <16 x i8> %tmp3529}530 531define <8 x i16> @v_orrQi16(ptr %A, ptr %B) nounwind {532; CHECK-LABEL: v_orrQi16:533; CHECK: @ %bb.0:534; CHECK-NEXT: vld1.64 {d16, d17}, [r1]535; CHECK-NEXT: vld1.64 {d18, d19}, [r0]536; CHECK-NEXT: vorr q8, q9, q8537; CHECK-NEXT: vmov r0, r1, d16538; CHECK-NEXT: vmov r2, r3, d17539; CHECK-NEXT: bx lr540 %tmp1 = load <8 x i16>, ptr %A541 %tmp2 = load <8 x i16>, ptr %B542 %tmp3 = or <8 x i16> %tmp1, %tmp2543 ret <8 x i16> %tmp3544}545 546define <4 x i32> @v_orrQi32(ptr %A, ptr %B) nounwind {547; CHECK-LABEL: v_orrQi32:548; CHECK: @ %bb.0:549; CHECK-NEXT: vld1.64 {d16, d17}, [r1]550; CHECK-NEXT: vld1.64 {d18, d19}, [r0]551; CHECK-NEXT: vorr q8, q9, q8552; CHECK-NEXT: vmov r0, r1, d16553; CHECK-NEXT: vmov r2, r3, d17554; CHECK-NEXT: bx lr555 %tmp1 = load <4 x i32>, ptr %A556 %tmp2 = load <4 x i32>, ptr %B557 %tmp3 = or <4 x i32> %tmp1, %tmp2558 ret <4 x i32> %tmp3559}560 561define <2 x i64> @v_orrQi64(ptr %A, ptr %B) nounwind {562; CHECK-LABEL: v_orrQi64:563; CHECK: @ %bb.0:564; CHECK-NEXT: vld1.64 {d16, d17}, [r1]565; CHECK-NEXT: vld1.64 {d18, d19}, [r0]566; CHECK-NEXT: vorr q8, q9, q8567; CHECK-NEXT: vmov r0, r1, d16568; CHECK-NEXT: vmov r2, r3, d17569; CHECK-NEXT: bx lr570 %tmp1 = load <2 x i64>, ptr %A571 %tmp2 = load <2 x i64>, ptr %B572 %tmp3 = or <2 x i64> %tmp1, %tmp2573 ret <2 x i64> %tmp3574}575 576define <8 x i8> @v_orni8(ptr %A, ptr %B) nounwind {577; CHECK-LABEL: v_orni8:578; CHECK: @ %bb.0:579; CHECK-NEXT: vldr d16, [r1]580; CHECK-NEXT: vldr d17, [r0]581; CHECK-NEXT: vorn d16, d17, d16582; CHECK-NEXT: vmov r0, r1, d16583; CHECK-NEXT: bx lr584 %tmp1 = load <8 x i8>, ptr %A585 %tmp2 = load <8 x i8>, ptr %B586 %tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >587 %tmp4 = or <8 x i8> %tmp1, %tmp3588 ret <8 x i8> %tmp4589}590 591define <4 x i16> @v_orni16(ptr %A, ptr %B) nounwind {592; CHECK-LABEL: v_orni16:593; CHECK: @ %bb.0:594; CHECK-NEXT: vldr d16, [r1]595; CHECK-NEXT: vldr d17, [r0]596; CHECK-NEXT: vorn d16, d17, d16597; CHECK-NEXT: vmov r0, r1, d16598; CHECK-NEXT: bx lr599 %tmp1 = load <4 x i16>, ptr %A600 %tmp2 = load <4 x i16>, ptr %B601 %tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 >602 %tmp4 = or <4 x i16> %tmp1, %tmp3603 ret <4 x i16> %tmp4604}605 606define <2 x i32> @v_orni32(ptr %A, ptr %B) nounwind {607; CHECK-LABEL: v_orni32:608; CHECK: @ %bb.0:609; CHECK-NEXT: vldr d16, [r1]610; CHECK-NEXT: vldr d17, [r0]611; CHECK-NEXT: vorn d16, d17, d16612; CHECK-NEXT: vmov r0, r1, d16613; CHECK-NEXT: bx lr614 %tmp1 = load <2 x i32>, ptr %A615 %tmp2 = load <2 x i32>, ptr %B616 %tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 >617 %tmp4 = or <2 x i32> %tmp1, %tmp3618 ret <2 x i32> %tmp4619}620 621define <1 x i64> @v_orni64(ptr %A, ptr %B) nounwind {622; CHECK-LABEL: v_orni64:623; CHECK: @ %bb.0:624; CHECK-NEXT: vldr d16, [r1]625; CHECK-NEXT: vldr d17, [r0]626; CHECK-NEXT: vorn d16, d17, d16627; CHECK-NEXT: vmov r0, r1, d16628; CHECK-NEXT: bx lr629 %tmp1 = load <1 x i64>, ptr %A630 %tmp2 = load <1 x i64>, ptr %B631 %tmp3 = xor <1 x i64> %tmp2, < i64 -1 >632 %tmp4 = or <1 x i64> %tmp1, %tmp3633 ret <1 x i64> %tmp4634}635 636define <16 x i8> @v_ornQi8(ptr %A, ptr %B) nounwind {637; CHECK-LABEL: v_ornQi8:638; CHECK: @ %bb.0:639; CHECK-NEXT: vld1.64 {d16, d17}, [r1]640; CHECK-NEXT: vld1.64 {d18, d19}, [r0]641; CHECK-NEXT: vorn q8, q9, q8642; CHECK-NEXT: vmov r0, r1, d16643; CHECK-NEXT: vmov r2, r3, d17644; CHECK-NEXT: bx lr645 %tmp1 = load <16 x i8>, ptr %A646 %tmp2 = load <16 x i8>, ptr %B647 %tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >648 %tmp4 = or <16 x i8> %tmp1, %tmp3649 ret <16 x i8> %tmp4650}651 652define <8 x i16> @v_ornQi16(ptr %A, ptr %B) nounwind {653; CHECK-LABEL: v_ornQi16:654; CHECK: @ %bb.0:655; CHECK-NEXT: vld1.64 {d16, d17}, [r1]656; CHECK-NEXT: vld1.64 {d18, d19}, [r0]657; CHECK-NEXT: vorn q8, q9, q8658; CHECK-NEXT: vmov r0, r1, d16659; CHECK-NEXT: vmov r2, r3, d17660; CHECK-NEXT: bx lr661 %tmp1 = load <8 x i16>, ptr %A662 %tmp2 = load <8 x i16>, ptr %B663 %tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >664 %tmp4 = or <8 x i16> %tmp1, %tmp3665 ret <8 x i16> %tmp4666}667 668define <4 x i32> @v_ornQi32(ptr %A, ptr %B) nounwind {669; CHECK-LABEL: v_ornQi32:670; CHECK: @ %bb.0:671; CHECK-NEXT: vld1.64 {d16, d17}, [r1]672; CHECK-NEXT: vld1.64 {d18, d19}, [r0]673; CHECK-NEXT: vorn q8, q9, q8674; CHECK-NEXT: vmov r0, r1, d16675; CHECK-NEXT: vmov r2, r3, d17676; CHECK-NEXT: bx lr677 %tmp1 = load <4 x i32>, ptr %A678 %tmp2 = load <4 x i32>, ptr %B679 %tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 >680 %tmp4 = or <4 x i32> %tmp1, %tmp3681 ret <4 x i32> %tmp4682}683 684define <2 x i64> @v_ornQi64(ptr %A, ptr %B) nounwind {685; CHECK-LABEL: v_ornQi64:686; CHECK: @ %bb.0:687; CHECK-NEXT: vld1.64 {d16, d17}, [r1]688; CHECK-NEXT: vld1.64 {d18, d19}, [r0]689; CHECK-NEXT: vorn q8, q9, q8690; CHECK-NEXT: vmov r0, r1, d16691; CHECK-NEXT: vmov r2, r3, d17692; CHECK-NEXT: bx lr693 %tmp1 = load <2 x i64>, ptr %A694 %tmp2 = load <2 x i64>, ptr %B695 %tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 >696 %tmp4 = or <2 x i64> %tmp1, %tmp3697 ret <2 x i64> %tmp4698}699 700define <8 x i8> @vtsti8(ptr %A, ptr %B) nounwind {701; CHECK-LABEL: vtsti8:702; CHECK: @ %bb.0:703; CHECK-NEXT: vldr d16, [r1]704; CHECK-NEXT: vldr d17, [r0]705; CHECK-NEXT: vtst.8 d16, d17, d16706; CHECK-NEXT: vmov r0, r1, d16707; CHECK-NEXT: bx lr708 %tmp1 = load <8 x i8>, ptr %A709 %tmp2 = load <8 x i8>, ptr %B710 %tmp3 = and <8 x i8> %tmp1, %tmp2711 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer712 %tmp5 = sext <8 x i1> %tmp4 to <8 x i8>713 ret <8 x i8> %tmp5714}715 716define <4 x i16> @vtsti16(ptr %A, ptr %B) nounwind {717; CHECK-LABEL: vtsti16:718; CHECK: @ %bb.0:719; CHECK-NEXT: vldr d16, [r1]720; CHECK-NEXT: vldr d17, [r0]721; CHECK-NEXT: vtst.16 d16, d17, d16722; CHECK-NEXT: vmov r0, r1, d16723; CHECK-NEXT: bx lr724 %tmp1 = load <4 x i16>, ptr %A725 %tmp2 = load <4 x i16>, ptr %B726 %tmp3 = and <4 x i16> %tmp1, %tmp2727 %tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer728 %tmp5 = sext <4 x i1> %tmp4 to <4 x i16>729 ret <4 x i16> %tmp5730}731 732define <2 x i32> @vtsti32(ptr %A, ptr %B) nounwind {733; CHECK-LABEL: vtsti32:734; CHECK: @ %bb.0:735; CHECK-NEXT: vldr d16, [r1]736; CHECK-NEXT: vldr d17, [r0]737; CHECK-NEXT: vtst.32 d16, d17, d16738; CHECK-NEXT: vmov r0, r1, d16739; CHECK-NEXT: bx lr740 %tmp1 = load <2 x i32>, ptr %A741 %tmp2 = load <2 x i32>, ptr %B742 %tmp3 = and <2 x i32> %tmp1, %tmp2743 %tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer744 %tmp5 = sext <2 x i1> %tmp4 to <2 x i32>745 ret <2 x i32> %tmp5746}747 748define <16 x i8> @vtstQi8(ptr %A, ptr %B) nounwind {749; CHECK-LABEL: vtstQi8:750; CHECK: @ %bb.0:751; CHECK-NEXT: vld1.64 {d16, d17}, [r1]752; CHECK-NEXT: vld1.64 {d18, d19}, [r0]753; CHECK-NEXT: vtst.8 q8, q9, q8754; CHECK-NEXT: vmov r0, r1, d16755; CHECK-NEXT: vmov r2, r3, d17756; CHECK-NEXT: bx lr757 %tmp1 = load <16 x i8>, ptr %A758 %tmp2 = load <16 x i8>, ptr %B759 %tmp3 = and <16 x i8> %tmp1, %tmp2760 %tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer761 %tmp5 = sext <16 x i1> %tmp4 to <16 x i8>762 ret <16 x i8> %tmp5763}764 765define <8 x i16> @vtstQi16(ptr %A, ptr %B) nounwind {766; CHECK-LABEL: vtstQi16:767; CHECK: @ %bb.0:768; CHECK-NEXT: vld1.64 {d16, d17}, [r1]769; CHECK-NEXT: vld1.64 {d18, d19}, [r0]770; CHECK-NEXT: vtst.16 q8, q9, q8771; CHECK-NEXT: vmov r0, r1, d16772; CHECK-NEXT: vmov r2, r3, d17773; CHECK-NEXT: bx lr774 %tmp1 = load <8 x i16>, ptr %A775 %tmp2 = load <8 x i16>, ptr %B776 %tmp3 = and <8 x i16> %tmp1, %tmp2777 %tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer778 %tmp5 = sext <8 x i1> %tmp4 to <8 x i16>779 ret <8 x i16> %tmp5780}781 782define <4 x i32> @vtstQi32(ptr %A, ptr %B) nounwind {783; CHECK-LABEL: vtstQi32:784; CHECK: @ %bb.0:785; CHECK-NEXT: vld1.64 {d16, d17}, [r1]786; CHECK-NEXT: vld1.64 {d18, d19}, [r0]787; CHECK-NEXT: vtst.32 q8, q9, q8788; CHECK-NEXT: vmov r0, r1, d16789; CHECK-NEXT: vmov r2, r3, d17790; CHECK-NEXT: bx lr791 %tmp1 = load <4 x i32>, ptr %A792 %tmp2 = load <4 x i32>, ptr %B793 %tmp3 = and <4 x i32> %tmp1, %tmp2794 %tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer795 %tmp5 = sext <4 x i1> %tmp4 to <4 x i32>796 ret <4 x i32> %tmp5797}798 799define <8 x i8> @v_orrimm(ptr %A) nounwind {800; CHECK-LABEL: v_orrimm:801; CHECK: @ %bb.0:802; CHECK-NEXT: vldr d16, [r0]803; CHECK-NEXT: vorr.i32 d16, #0x1000000804; CHECK-NEXT: vmov r0, r1, d16805; CHECK-NEXT: bx lr806 %tmp1 = load <8 x i8>, ptr %A807 %tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>808 ret <8 x i8> %tmp3809}810 811define <16 x i8> @v_orrimmQ(ptr %A) nounwind {812; CHECK-LABEL: v_orrimmQ:813; CHECK: @ %bb.0:814; CHECK-NEXT: vld1.64 {d16, d17}, [r0]815; CHECK-NEXT: vorr.i32 q8, #0x1000000816; CHECK-NEXT: vmov r0, r1, d16817; CHECK-NEXT: vmov r2, r3, d17818; CHECK-NEXT: bx lr819 %tmp1 = load <16 x i8>, ptr %A820 %tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>821 ret <16 x i8> %tmp3822}823 824define <8 x i8> @v_bicimm(ptr %A) nounwind {825; CHECK-LABEL: v_bicimm:826; CHECK: @ %bb.0:827; CHECK-NEXT: vldr d16, [r0]828; CHECK-NEXT: vbic.i32 d16, #0xff000000829; CHECK-NEXT: vmov r0, r1, d16830; CHECK-NEXT: bx lr831 %tmp1 = load <8 x i8>, ptr %A832 %tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >833 ret <8 x i8> %tmp3834}835 836define <16 x i8> @v_bicimmQ(ptr %A) nounwind {837; CHECK-LABEL: v_bicimmQ:838; CHECK: @ %bb.0:839; CHECK-NEXT: vld1.64 {d16, d17}, [r0]840; CHECK-NEXT: vbic.i32 q8, #0xff000000841; CHECK-NEXT: vmov r0, r1, d16842; CHECK-NEXT: vmov r2, r3, d17843; CHECK-NEXT: bx lr844 %tmp1 = load <16 x i8>, ptr %A845 %tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >846 ret <16 x i8> %tmp3847}848 849define <4 x i32> @hidden_not_v4i32(<4 x i32> %x) nounwind {850; CHECK-LABEL: hidden_not_v4i32:851; CHECK: @ %bb.0:852; CHECK-NEXT: vmov d19, r2, r3853; CHECK-NEXT: vmov.i32 q8, #0x6854; CHECK-NEXT: vmov d18, r0, r1855; CHECK-NEXT: vbic q8, q8, q9856; CHECK-NEXT: vmov r0, r1, d16857; CHECK-NEXT: vmov r2, r3, d17858; CHECK-NEXT: bx lr859 %xor = xor <4 x i32> %x, <i32 15, i32 15, i32 15, i32 15>860 %and = and <4 x i32> %xor, <i32 6, i32 6, i32 6, i32 6>861 ret <4 x i32> %and862}863 864