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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+neon | FileCheck %s3 4define <8 x i8> @v_bsli8(ptr %A, ptr %B, ptr %C) nounwind {5; CHECK-LABEL: v_bsli8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vmov.i8 d16, #0x38; CHECK-NEXT: vldr d17, [r2]9; CHECK-NEXT: vldr d18, [r0]10; CHECK-NEXT: vbsl d16, d18, d1711; CHECK-NEXT: vmov r0, r1, d1612; CHECK-NEXT: mov pc, lr13 %tmp1 = load <8 x i8>, ptr %A14 %tmp2 = load <8 x i8>, ptr %B15 %tmp3 = load <8 x i8>, ptr %C16 %tmp4 = and <8 x i8> %tmp1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>17 %tmp6 = and <8 x i8> %tmp3, <i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4>18 %tmp7 = or <8 x i8> %tmp4, %tmp619 ret <8 x i8> %tmp720}21 22define <4 x i16> @v_bsli16(ptr %A, ptr %B, ptr %C) nounwind {23; CHECK-LABEL: v_bsli16:24; CHECK: @ %bb.0:25; CHECK-NEXT: vmov.i16 d16, #0x326; CHECK-NEXT: vldr d17, [r2]27; CHECK-NEXT: vldr d18, [r0]28; CHECK-NEXT: vbsl d16, d18, d1729; CHECK-NEXT: vmov r0, r1, d1630; CHECK-NEXT: mov pc, lr31 %tmp1 = load <4 x i16>, ptr %A32 %tmp2 = load <4 x i16>, ptr %B33 %tmp3 = load <4 x i16>, ptr %C34 %tmp4 = and <4 x i16> %tmp1, <i16 3, i16 3, i16 3, i16 3>35 %tmp6 = and <4 x i16> %tmp3, <i16 -4, i16 -4, i16 -4, i16 -4>36 %tmp7 = or <4 x i16> %tmp4, %tmp637 ret <4 x i16> %tmp738}39 40define <2 x i32> @v_bsli32(ptr %A, ptr %B, ptr %C) nounwind {41; CHECK-LABEL: v_bsli32:42; CHECK: @ %bb.0:43; CHECK-NEXT: vmov.i32 d16, #0x344; CHECK-NEXT: vldr d17, [r2]45; CHECK-NEXT: vldr d18, [r0]46; CHECK-NEXT: vbsl d16, d18, d1747; CHECK-NEXT: vmov r0, r1, d1648; CHECK-NEXT: mov pc, lr49 %tmp1 = load <2 x i32>, ptr %A50 %tmp2 = load <2 x i32>, ptr %B51 %tmp3 = load <2 x i32>, ptr %C52 %tmp4 = and <2 x i32> %tmp1, <i32 3, i32 3>53 %tmp6 = and <2 x i32> %tmp3, <i32 -4, i32 -4>54 %tmp7 = or <2 x i32> %tmp4, %tmp655 ret <2 x i32> %tmp756}57 58define <1 x i64> @v_bsli64(ptr %A, ptr %B, ptr %C) nounwind {59; CHECK-LABEL: v_bsli64:60; CHECK: @ %bb.0:61; CHECK-NEXT: vldr d17, [r2]62; CHECK-NEXT: vldr d16, LCPI3_063; CHECK-NEXT: vldr d18, [r0]64; CHECK-NEXT: vbsl d16, d18, d1765; CHECK-NEXT: vmov r0, r1, d1666; CHECK-NEXT: mov pc, lr67 %tmp1 = load <1 x i64>, ptr %A68 %tmp2 = load <1 x i64>, ptr %B69 %tmp3 = load <1 x i64>, ptr %C70 %tmp4 = and <1 x i64> %tmp1, <i64 3>71 %tmp6 = and <1 x i64> %tmp3, <i64 -4>72 %tmp7 = or <1 x i64> %tmp4, %tmp673 ret <1 x i64> %tmp774}75 76define <16 x i8> @v_bslQi8(ptr %A, ptr %B, ptr %C) nounwind {77; CHECK-LABEL: v_bslQi8:78; CHECK: @ %bb.0:79; CHECK-NEXT: vld1.32 {d16, d17}, [r2]80; CHECK-NEXT: vmov.i8 q9, #0x381; CHECK-NEXT: vld1.32 {d20, d21}, [r0]82; CHECK-NEXT: vbit q8, q10, q983; CHECK-NEXT: vmov r0, r1, d1684; CHECK-NEXT: vmov r2, r3, d1785; CHECK-NEXT: mov pc, lr86 %tmp1 = load <16 x i8>, ptr %A87 %tmp2 = load <16 x i8>, ptr %B88 %tmp3 = load <16 x i8>, ptr %C89 %tmp4 = and <16 x i8> %tmp1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>90 %tmp6 = and <16 x i8> %tmp3, <i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4>91 %tmp7 = or <16 x i8> %tmp4, %tmp692 ret <16 x i8> %tmp793}94 95define <8 x i16> @v_bslQi16(ptr %A, ptr %B, ptr %C) nounwind {96; CHECK-LABEL: v_bslQi16:97; CHECK: @ %bb.0:98; CHECK-NEXT: vld1.32 {d16, d17}, [r2]99; CHECK-NEXT: vmov.i16 q9, #0x3100; CHECK-NEXT: vld1.32 {d20, d21}, [r0]101; CHECK-NEXT: vbit q8, q10, q9102; CHECK-NEXT: vmov r0, r1, d16103; CHECK-NEXT: vmov r2, r3, d17104; CHECK-NEXT: mov pc, lr105 %tmp1 = load <8 x i16>, ptr %A106 %tmp2 = load <8 x i16>, ptr %B107 %tmp3 = load <8 x i16>, ptr %C108 %tmp4 = and <8 x i16> %tmp1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>109 %tmp6 = and <8 x i16> %tmp3, <i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4>110 %tmp7 = or <8 x i16> %tmp4, %tmp6111 ret <8 x i16> %tmp7112}113 114define <4 x i32> @v_bslQi32(ptr %A, ptr %B, ptr %C) nounwind {115; CHECK-LABEL: v_bslQi32:116; CHECK: @ %bb.0:117; CHECK-NEXT: vld1.32 {d16, d17}, [r2]118; CHECK-NEXT: vmov.i32 q9, #0x3119; CHECK-NEXT: vld1.32 {d20, d21}, [r0]120; CHECK-NEXT: vbit q8, q10, q9121; CHECK-NEXT: vmov r0, r1, d16122; CHECK-NEXT: vmov r2, r3, d17123; CHECK-NEXT: mov pc, lr124 %tmp1 = load <4 x i32>, ptr %A125 %tmp2 = load <4 x i32>, ptr %B126 %tmp3 = load <4 x i32>, ptr %C127 %tmp4 = and <4 x i32> %tmp1, <i32 3, i32 3, i32 3, i32 3>128 %tmp6 = and <4 x i32> %tmp3, <i32 -4, i32 -4, i32 -4, i32 -4>129 %tmp7 = or <4 x i32> %tmp4, %tmp6130 ret <4 x i32> %tmp7131}132 133define <2 x i64> @v_bslQi64(ptr %A, ptr %B, ptr %C) nounwind {134; CHECK-LABEL: v_bslQi64:135; CHECK: @ %bb.0:136; CHECK-NEXT: vld1.32 {d16, d17}, [r2]137; CHECK-NEXT: vld1.32 {d18, d19}, [r0]138; CHECK-NEXT: adr r0, LCPI7_0139; CHECK-NEXT: vld1.64 {d20, d21}, [r0:128]140; CHECK-NEXT: vbit q8, q9, q10141; CHECK-NEXT: vmov r0, r1, d16142; CHECK-NEXT: vmov r2, r3, d17143; CHECK-NEXT: mov pc, lr144 %tmp1 = load <2 x i64>, ptr %A145 %tmp2 = load <2 x i64>, ptr %B146 %tmp3 = load <2 x i64>, ptr %C147 %tmp4 = and <2 x i64> %tmp1, <i64 3, i64 3>148 %tmp6 = and <2 x i64> %tmp3, <i64 -4, i64 -4>149 %tmp7 = or <2 x i64> %tmp4, %tmp6150 ret <2 x i64> %tmp7151}152