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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=armv7-eabihf -mattr=+neon -verify-machineinstrs %s -o - | FileCheck %s3 4define <8 x i8> @v_bsli8(ptr %A, ptr %B, ptr %C) nounwind {5; CHECK-LABEL: v_bsli8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vldr d18, [r0]8; CHECK-NEXT: vldr d16, [r2]9; CHECK-NEXT: vorr d0, d18, d1810; CHECK-NEXT: vldr d17, [r1]11; CHECK-NEXT: vbsl d0, d17, d1612; CHECK-NEXT: bx lr13 %tmp1 = load <8 x i8>, ptr %A14 %tmp2 = load <8 x i8>, ptr %B15 %tmp3 = load <8 x i8>, ptr %C16 %tmp4 = and <8 x i8> %tmp1, %tmp217 %tmp5 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >18 %tmp6 = and <8 x i8> %tmp5, %tmp319 %tmp7 = or <8 x i8> %tmp4, %tmp620 ret <8 x i8> %tmp721}22 23define <4 x i16> @v_bsli16(ptr %A, ptr %B, ptr %C) nounwind {24; CHECK-LABEL: v_bsli16:25; CHECK: @ %bb.0:26; CHECK-NEXT: vldr d18, [r0]27; CHECK-NEXT: vldr d16, [r2]28; CHECK-NEXT: vorr d0, d18, d1829; CHECK-NEXT: vldr d17, [r1]30; CHECK-NEXT: vbsl d0, d17, d1631; CHECK-NEXT: bx lr32 %tmp1 = load <4 x i16>, ptr %A33 %tmp2 = load <4 x i16>, ptr %B34 %tmp3 = load <4 x i16>, ptr %C35 %tmp4 = and <4 x i16> %tmp1, %tmp236 %tmp5 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 >37 %tmp6 = and <4 x i16> %tmp5, %tmp338 %tmp7 = or <4 x i16> %tmp4, %tmp639 ret <4 x i16> %tmp740}41 42define <2 x i32> @v_bsli32(ptr %A, ptr %B, ptr %C) nounwind {43; CHECK-LABEL: v_bsli32:44; CHECK: @ %bb.0:45; CHECK-NEXT: vldr d18, [r0]46; CHECK-NEXT: vldr d16, [r2]47; CHECK-NEXT: vorr d0, d18, d1848; CHECK-NEXT: vldr d17, [r1]49; CHECK-NEXT: vbsl d0, d17, d1650; CHECK-NEXT: bx lr51 %tmp1 = load <2 x i32>, ptr %A52 %tmp2 = load <2 x i32>, ptr %B53 %tmp3 = load <2 x i32>, ptr %C54 %tmp4 = and <2 x i32> %tmp1, %tmp255 %tmp5 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 >56 %tmp6 = and <2 x i32> %tmp5, %tmp357 %tmp7 = or <2 x i32> %tmp4, %tmp658 ret <2 x i32> %tmp759}60 61define <1 x i64> @v_bsli64(ptr %A, ptr %B, ptr %C) nounwind {62; CHECK-LABEL: v_bsli64:63; CHECK: @ %bb.0:64; CHECK-NEXT: vldr d18, [r0]65; CHECK-NEXT: vldr d16, [r2]66; CHECK-NEXT: vorr d0, d18, d1867; CHECK-NEXT: vldr d17, [r1]68; CHECK-NEXT: vbsl d0, d17, d1669; CHECK-NEXT: bx lr70 %tmp1 = load <1 x i64>, ptr %A71 %tmp2 = load <1 x i64>, ptr %B72 %tmp3 = load <1 x i64>, ptr %C73 %tmp4 = and <1 x i64> %tmp1, %tmp274 %tmp5 = xor <1 x i64> %tmp1, < i64 -1 >75 %tmp6 = and <1 x i64> %tmp5, %tmp376 %tmp7 = or <1 x i64> %tmp4, %tmp677 ret <1 x i64> %tmp778}79 80define <16 x i8> @v_bslQi8(ptr %A, ptr %B, ptr %C) nounwind {81; CHECK-LABEL: v_bslQi8:82; CHECK: @ %bb.0:83; CHECK-NEXT: vld1.64 {d20, d21}, [r0]84; CHECK-NEXT: vorr q0, q10, q1085; CHECK-NEXT: vld1.64 {d16, d17}, [r2]86; CHECK-NEXT: vld1.64 {d18, d19}, [r1]87; CHECK-NEXT: vbsl q0, q9, q888; CHECK-NEXT: bx lr89 %tmp1 = load <16 x i8>, ptr %A90 %tmp2 = load <16 x i8>, ptr %B91 %tmp3 = load <16 x i8>, ptr %C92 %tmp4 = and <16 x i8> %tmp1, %tmp293 %tmp5 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >94 %tmp6 = and <16 x i8> %tmp5, %tmp395 %tmp7 = or <16 x i8> %tmp4, %tmp696 ret <16 x i8> %tmp797}98 99define <8 x i16> @v_bslQi16(ptr %A, ptr %B, ptr %C) nounwind {100; CHECK-LABEL: v_bslQi16:101; CHECK: @ %bb.0:102; CHECK-NEXT: vld1.64 {d20, d21}, [r0]103; CHECK-NEXT: vorr q0, q10, q10104; CHECK-NEXT: vld1.64 {d16, d17}, [r2]105; CHECK-NEXT: vld1.64 {d18, d19}, [r1]106; CHECK-NEXT: vbsl q0, q9, q8107; CHECK-NEXT: bx lr108 %tmp1 = load <8 x i16>, ptr %A109 %tmp2 = load <8 x i16>, ptr %B110 %tmp3 = load <8 x i16>, ptr %C111 %tmp4 = and <8 x i16> %tmp1, %tmp2112 %tmp5 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >113 %tmp6 = and <8 x i16> %tmp5, %tmp3114 %tmp7 = or <8 x i16> %tmp4, %tmp6115 ret <8 x i16> %tmp7116}117 118define <4 x i32> @v_bslQi32(ptr %A, ptr %B, ptr %C) nounwind {119; CHECK-LABEL: v_bslQi32:120; CHECK: @ %bb.0:121; CHECK-NEXT: vld1.64 {d20, d21}, [r0]122; CHECK-NEXT: vorr q0, q10, q10123; CHECK-NEXT: vld1.64 {d16, d17}, [r2]124; CHECK-NEXT: vld1.64 {d18, d19}, [r1]125; CHECK-NEXT: vbsl q0, q9, q8126; CHECK-NEXT: bx lr127 %tmp1 = load <4 x i32>, ptr %A128 %tmp2 = load <4 x i32>, ptr %B129 %tmp3 = load <4 x i32>, ptr %C130 %tmp4 = and <4 x i32> %tmp1, %tmp2131 %tmp5 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 >132 %tmp6 = and <4 x i32> %tmp5, %tmp3133 %tmp7 = or <4 x i32> %tmp4, %tmp6134 ret <4 x i32> %tmp7135}136 137define <2 x i64> @v_bslQi64(ptr %A, ptr %B, ptr %C) nounwind {138; CHECK-LABEL: v_bslQi64:139; CHECK: @ %bb.0:140; CHECK-NEXT: vld1.64 {d20, d21}, [r0]141; CHECK-NEXT: vorr q0, q10, q10142; CHECK-NEXT: vld1.64 {d16, d17}, [r2]143; CHECK-NEXT: vld1.64 {d18, d19}, [r1]144; CHECK-NEXT: vbsl q0, q9, q8145; CHECK-NEXT: bx lr146 %tmp1 = load <2 x i64>, ptr %A147 %tmp2 = load <2 x i64>, ptr %B148 %tmp3 = load <2 x i64>, ptr %C149 %tmp4 = and <2 x i64> %tmp1, %tmp2150 %tmp5 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 >151 %tmp6 = and <2 x i64> %tmp5, %tmp3152 %tmp7 = or <2 x i64> %tmp4, %tmp6153 ret <2 x i64> %tmp7154}155 156define <8 x i8> @f1(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind readnone optsize ssp {157; CHECK-LABEL: f1:158; CHECK: @ %bb.0:159; CHECK-NEXT: vbsl d0, d1, d2160; CHECK-NEXT: bx lr161 %vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind162 ret <8 x i8> %vbsl.i163}164 165define <4 x i16> @f2(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {166; CHECK-LABEL: f2:167; CHECK: @ %bb.0:168; CHECK-NEXT: vbsl d0, d1, d2169; CHECK-NEXT: bx lr170 %vbsl3.i = tail call <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind171 ret <4 x i16> %vbsl3.i172}173 174define <2 x i32> @f3(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {175; CHECK-LABEL: f3:176; CHECK: @ %bb.0:177; CHECK-NEXT: vbsl d0, d1, d2178; CHECK-NEXT: bx lr179 %vbsl3.i = tail call <2 x i32> @llvm.arm.neon.vbsl.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind180 ret <2 x i32> %vbsl3.i181}182 183define <2 x float> @f4(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone optsize ssp {184; CHECK-LABEL: f4:185; CHECK: @ %bb.0:186; CHECK-NEXT: vbsl d0, d1, d2187; CHECK-NEXT: bx lr188 %vbsl4.i = tail call <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind189 ret <2 x float> %vbsl4.i190}191 192define <16 x i8> @g1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind readnone optsize ssp {193; CHECK-LABEL: g1:194; CHECK: @ %bb.0:195; CHECK-NEXT: vbsl q0, q1, q2196; CHECK-NEXT: bx lr197 %vbsl.i = tail call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind198 ret <16 x i8> %vbsl.i199}200 201define <8 x i16> @g2(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind readnone optsize ssp {202; CHECK-LABEL: g2:203; CHECK: @ %bb.0:204; CHECK-NEXT: vbsl q0, q1, q2205; CHECK-NEXT: bx lr206 %vbsl3.i = tail call <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind207 ret <8 x i16> %vbsl3.i208}209 210define <4 x i32> @g3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {211; CHECK-LABEL: g3:212; CHECK: @ %bb.0:213; CHECK-NEXT: vbsl q0, q1, q2214; CHECK-NEXT: bx lr215 %vbsl3.i = tail call <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind216 ret <4 x i32> %vbsl3.i217}218 219define <4 x float> @g4(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone optsize ssp {220; CHECK-LABEL: g4:221; CHECK: @ %bb.0:222; CHECK-NEXT: vbsl q0, q1, q2223; CHECK-NEXT: bx lr224 %vbsl4.i = tail call <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind225 ret <4 x float> %vbsl4.i226}227 228define <1 x i64> @test_vbsl_s64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {229; CHECK-LABEL: test_vbsl_s64:230; CHECK: @ %bb.0:231; CHECK-NEXT: vbsl d0, d1, d2232; CHECK-NEXT: bx lr233 %vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind234 ret <1 x i64> %vbsl3.i235}236 237define <1 x i64> @test_vbsl_u64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {238; CHECK-LABEL: test_vbsl_u64:239; CHECK: @ %bb.0:240; CHECK-NEXT: vbsl d0, d1, d2241; CHECK-NEXT: bx lr242 %vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind243 ret <1 x i64> %vbsl3.i244}245 246define <2 x i64> @test_vbslq_s64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {247; CHECK-LABEL: test_vbslq_s64:248; CHECK: @ %bb.0:249; CHECK-NEXT: vbsl q0, q1, q2250; CHECK-NEXT: bx lr251 %vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind252 ret <2 x i64> %vbsl3.i253}254 255define <2 x i64> @test_vbslq_u64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {256; CHECK-LABEL: test_vbslq_u64:257; CHECK: @ %bb.0:258; CHECK-NEXT: vbsl q0, q1, q2259; CHECK-NEXT: bx lr260 %vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind261 ret <2 x i64> %vbsl3.i262}263 264define <8 x i8> @same_param_all(<8 x i8> %a, <8 x i8> %b) {265; CHECK-LABEL: same_param_all:266; CHECK: @ %bb.0:267; CHECK-NEXT: vmov.f64 d0, d1268; CHECK-NEXT: bx lr269 %vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %b, <8 x i8> %b, <8 x i8> %b)270 ret <8 x i8> %vbsl.i271}272 273define <8 x i8> @same_param_12(<8 x i8> %a, <8 x i8> %b) {274; CHECK-LABEL: same_param_12:275; CHECK: @ %bb.0:276; CHECK-NEXT: vmov.f64 d0, d1277; CHECK-NEXT: bx lr278 %vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %b)279 ret <8 x i8> %vbsl.i280}281 282define <8 x i8> @same_param_01(<8 x i8> %a, <8 x i8> %b) {283; CHECK-LABEL: same_param_01:284; CHECK: @ %bb.0:285; CHECK-NEXT: vbif d0, d1, d0286; CHECK-NEXT: bx lr287 %vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> %b)288 ret <8 x i8> %vbsl.i289}290 291declare <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone292declare <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone293declare <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone294declare <2 x i32> @llvm.arm.neon.vbsl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone295declare <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone296declare <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone297declare <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone298declare <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone299declare <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone300declare <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64>, <1 x i64>, <1 x i64>) nounwind readnone301