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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon | FileCheck %s3 4define <8 x i8> @vceqi8(ptr %A, ptr %B) nounwind {5; CHECK-LABEL: vceqi8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vldr d16, [r1]8; CHECK-NEXT: vldr d17, [r0]9; CHECK-NEXT: vceq.i8 d16, d17, d1610; CHECK-NEXT: vmov r0, r1, d1611; CHECK-NEXT: mov pc, lr12 %tmp1 = load <8 x i8>, ptr %A13 %tmp2 = load <8 x i8>, ptr %B14 %tmp3 = icmp eq <8 x i8> %tmp1, %tmp215 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>16 ret <8 x i8> %tmp417}18 19define <4 x i16> @vceqi16(ptr %A, ptr %B) nounwind {20; CHECK-LABEL: vceqi16:21; CHECK: @ %bb.0:22; CHECK-NEXT: vldr d16, [r1]23; CHECK-NEXT: vldr d17, [r0]24; CHECK-NEXT: vceq.i16 d16, d17, d1625; CHECK-NEXT: vmov r0, r1, d1626; CHECK-NEXT: mov pc, lr27 %tmp1 = load <4 x i16>, ptr %A28 %tmp2 = load <4 x i16>, ptr %B29 %tmp3 = icmp eq <4 x i16> %tmp1, %tmp230 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>31 ret <4 x i16> %tmp432}33 34define <2 x i32> @vceqi32(ptr %A, ptr %B) nounwind {35; CHECK-LABEL: vceqi32:36; CHECK: @ %bb.0:37; CHECK-NEXT: vldr d16, [r1]38; CHECK-NEXT: vldr d17, [r0]39; CHECK-NEXT: vceq.i32 d16, d17, d1640; CHECK-NEXT: vmov r0, r1, d1641; CHECK-NEXT: mov pc, lr42 %tmp1 = load <2 x i32>, ptr %A43 %tmp2 = load <2 x i32>, ptr %B44 %tmp3 = icmp eq <2 x i32> %tmp1, %tmp245 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>46 ret <2 x i32> %tmp447}48 49define <2 x i32> @vceqf32(ptr %A, ptr %B) nounwind {50; CHECK-LABEL: vceqf32:51; CHECK: @ %bb.0:52; CHECK-NEXT: vldr d16, [r1]53; CHECK-NEXT: vldr d17, [r0]54; CHECK-NEXT: vceq.f32 d16, d17, d1655; CHECK-NEXT: vmov r0, r1, d1656; CHECK-NEXT: mov pc, lr57 %tmp1 = load <2 x float>, ptr %A58 %tmp2 = load <2 x float>, ptr %B59 %tmp3 = fcmp oeq <2 x float> %tmp1, %tmp260 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>61 ret <2 x i32> %tmp462}63 64define <16 x i8> @vceqQi8(ptr %A, ptr %B) nounwind {65; CHECK-LABEL: vceqQi8:66; CHECK: @ %bb.0:67; CHECK-NEXT: vld1.64 {d16, d17}, [r1]68; CHECK-NEXT: vld1.64 {d18, d19}, [r0]69; CHECK-NEXT: vceq.i8 q8, q9, q870; CHECK-NEXT: vmov r0, r1, d1671; CHECK-NEXT: vmov r2, r3, d1772; CHECK-NEXT: mov pc, lr73 %tmp1 = load <16 x i8>, ptr %A74 %tmp2 = load <16 x i8>, ptr %B75 %tmp3 = icmp eq <16 x i8> %tmp1, %tmp276 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>77 ret <16 x i8> %tmp478}79 80define <8 x i16> @vceqQi16(ptr %A, ptr %B) nounwind {81; CHECK-LABEL: vceqQi16:82; CHECK: @ %bb.0:83; CHECK-NEXT: vld1.64 {d16, d17}, [r1]84; CHECK-NEXT: vld1.64 {d18, d19}, [r0]85; CHECK-NEXT: vceq.i16 q8, q9, q886; CHECK-NEXT: vmov r0, r1, d1687; CHECK-NEXT: vmov r2, r3, d1788; CHECK-NEXT: mov pc, lr89 %tmp1 = load <8 x i16>, ptr %A90 %tmp2 = load <8 x i16>, ptr %B91 %tmp3 = icmp eq <8 x i16> %tmp1, %tmp292 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>93 ret <8 x i16> %tmp494}95 96define <4 x i32> @vceqQi32(ptr %A, ptr %B) nounwind {97; CHECK-LABEL: vceqQi32:98; CHECK: @ %bb.0:99; CHECK-NEXT: vld1.64 {d16, d17}, [r1]100; CHECK-NEXT: vld1.64 {d18, d19}, [r0]101; CHECK-NEXT: vceq.i32 q8, q9, q8102; CHECK-NEXT: vmov r0, r1, d16103; CHECK-NEXT: vmov r2, r3, d17104; CHECK-NEXT: mov pc, lr105 %tmp1 = load <4 x i32>, ptr %A106 %tmp2 = load <4 x i32>, ptr %B107 %tmp3 = icmp eq <4 x i32> %tmp1, %tmp2108 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>109 ret <4 x i32> %tmp4110}111 112define <4 x i32> @vceqQf32(ptr %A, ptr %B) nounwind {113; CHECK-LABEL: vceqQf32:114; CHECK: @ %bb.0:115; CHECK-NEXT: vld1.64 {d16, d17}, [r1]116; CHECK-NEXT: vld1.64 {d18, d19}, [r0]117; CHECK-NEXT: vceq.f32 q8, q9, q8118; CHECK-NEXT: vmov r0, r1, d16119; CHECK-NEXT: vmov r2, r3, d17120; CHECK-NEXT: mov pc, lr121 %tmp1 = load <4 x float>, ptr %A122 %tmp2 = load <4 x float>, ptr %B123 %tmp3 = fcmp oeq <4 x float> %tmp1, %tmp2124 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>125 ret <4 x i32> %tmp4126}127 128define <8 x i8> @vceqi8Z(ptr %A) nounwind {129; CHECK-LABEL: vceqi8Z:130; CHECK: @ %bb.0:131; CHECK-NEXT: vldr d16, [r0]132; CHECK-NEXT: vceq.i8 d16, d16, #0133; CHECK-NEXT: vmov r0, r1, d16134; CHECK-NEXT: mov pc, lr135 %tmp1 = load <8 x i8>, ptr %A136 %tmp3 = icmp eq <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>137 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>138 ret <8 x i8> %tmp4139}140