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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon | FileCheck %s3 4define <8 x i8> @vcges8(ptr %A, ptr %B) nounwind {5; CHECK-LABEL: vcges8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vldr d16, [r1]8; CHECK-NEXT: vldr d17, [r0]9; CHECK-NEXT: vcge.s8 d16, d17, d1610; CHECK-NEXT: vmov r0, r1, d1611; CHECK-NEXT: mov pc, lr12 %tmp1 = load <8 x i8>, ptr %A13 %tmp2 = load <8 x i8>, ptr %B14 %tmp3 = icmp sge <8 x i8> %tmp1, %tmp215 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>16 ret <8 x i8> %tmp417}18 19define <4 x i16> @vcges16(ptr %A, ptr %B) nounwind {20; CHECK-LABEL: vcges16:21; CHECK: @ %bb.0:22; CHECK-NEXT: vldr d16, [r1]23; CHECK-NEXT: vldr d17, [r0]24; CHECK-NEXT: vcge.s16 d16, d17, d1625; CHECK-NEXT: vmov r0, r1, d1626; CHECK-NEXT: mov pc, lr27 %tmp1 = load <4 x i16>, ptr %A28 %tmp2 = load <4 x i16>, ptr %B29 %tmp3 = icmp sge <4 x i16> %tmp1, %tmp230 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>31 ret <4 x i16> %tmp432}33 34define <2 x i32> @vcges32(ptr %A, ptr %B) nounwind {35; CHECK-LABEL: vcges32:36; CHECK: @ %bb.0:37; CHECK-NEXT: vldr d16, [r1]38; CHECK-NEXT: vldr d17, [r0]39; CHECK-NEXT: vcge.s32 d16, d17, d1640; CHECK-NEXT: vmov r0, r1, d1641; CHECK-NEXT: mov pc, lr42 %tmp1 = load <2 x i32>, ptr %A43 %tmp2 = load <2 x i32>, ptr %B44 %tmp3 = icmp sge <2 x i32> %tmp1, %tmp245 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>46 ret <2 x i32> %tmp447}48 49define <8 x i8> @vcgeu8(ptr %A, ptr %B) nounwind {50; CHECK-LABEL: vcgeu8:51; CHECK: @ %bb.0:52; CHECK-NEXT: vldr d16, [r1]53; CHECK-NEXT: vldr d17, [r0]54; CHECK-NEXT: vcge.u8 d16, d17, d1655; CHECK-NEXT: vmov r0, r1, d1656; CHECK-NEXT: mov pc, lr57 %tmp1 = load <8 x i8>, ptr %A58 %tmp2 = load <8 x i8>, ptr %B59 %tmp3 = icmp uge <8 x i8> %tmp1, %tmp260 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>61 ret <8 x i8> %tmp462}63 64define <4 x i16> @vcgeu16(ptr %A, ptr %B) nounwind {65; CHECK-LABEL: vcgeu16:66; CHECK: @ %bb.0:67; CHECK-NEXT: vldr d16, [r1]68; CHECK-NEXT: vldr d17, [r0]69; CHECK-NEXT: vcge.u16 d16, d17, d1670; CHECK-NEXT: vmov r0, r1, d1671; CHECK-NEXT: mov pc, lr72 %tmp1 = load <4 x i16>, ptr %A73 %tmp2 = load <4 x i16>, ptr %B74 %tmp3 = icmp uge <4 x i16> %tmp1, %tmp275 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>76 ret <4 x i16> %tmp477}78 79define <2 x i32> @vcgeu32(ptr %A, ptr %B) nounwind {80; CHECK-LABEL: vcgeu32:81; CHECK: @ %bb.0:82; CHECK-NEXT: vldr d16, [r1]83; CHECK-NEXT: vldr d17, [r0]84; CHECK-NEXT: vcge.u32 d16, d17, d1685; CHECK-NEXT: vmov r0, r1, d1686; CHECK-NEXT: mov pc, lr87 %tmp1 = load <2 x i32>, ptr %A88 %tmp2 = load <2 x i32>, ptr %B89 %tmp3 = icmp uge <2 x i32> %tmp1, %tmp290 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>91 ret <2 x i32> %tmp492}93 94define <2 x i32> @vcgef32(ptr %A, ptr %B) nounwind {95; CHECK-LABEL: vcgef32:96; CHECK: @ %bb.0:97; CHECK-NEXT: vldr d16, [r1]98; CHECK-NEXT: vldr d17, [r0]99; CHECK-NEXT: vcge.f32 d16, d17, d16100; CHECK-NEXT: vmov r0, r1, d16101; CHECK-NEXT: mov pc, lr102 %tmp1 = load <2 x float>, ptr %A103 %tmp2 = load <2 x float>, ptr %B104 %tmp3 = fcmp oge <2 x float> %tmp1, %tmp2105 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>106 ret <2 x i32> %tmp4107}108 109define <16 x i8> @vcgeQs8(ptr %A, ptr %B) nounwind {110; CHECK-LABEL: vcgeQs8:111; CHECK: @ %bb.0:112; CHECK-NEXT: vld1.64 {d16, d17}, [r1]113; CHECK-NEXT: vld1.64 {d18, d19}, [r0]114; CHECK-NEXT: vcge.s8 q8, q9, q8115; CHECK-NEXT: vmov r0, r1, d16116; CHECK-NEXT: vmov r2, r3, d17117; CHECK-NEXT: mov pc, lr118 %tmp1 = load <16 x i8>, ptr %A119 %tmp2 = load <16 x i8>, ptr %B120 %tmp3 = icmp sge <16 x i8> %tmp1, %tmp2121 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>122 ret <16 x i8> %tmp4123}124 125define <8 x i16> @vcgeQs16(ptr %A, ptr %B) nounwind {126; CHECK-LABEL: vcgeQs16:127; CHECK: @ %bb.0:128; CHECK-NEXT: vld1.64 {d16, d17}, [r1]129; CHECK-NEXT: vld1.64 {d18, d19}, [r0]130; CHECK-NEXT: vcge.s16 q8, q9, q8131; CHECK-NEXT: vmov r0, r1, d16132; CHECK-NEXT: vmov r2, r3, d17133; CHECK-NEXT: mov pc, lr134 %tmp1 = load <8 x i16>, ptr %A135 %tmp2 = load <8 x i16>, ptr %B136 %tmp3 = icmp sge <8 x i16> %tmp1, %tmp2137 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>138 ret <8 x i16> %tmp4139}140 141define <4 x i32> @vcgeQs32(ptr %A, ptr %B) nounwind {142; CHECK-LABEL: vcgeQs32:143; CHECK: @ %bb.0:144; CHECK-NEXT: vld1.64 {d16, d17}, [r1]145; CHECK-NEXT: vld1.64 {d18, d19}, [r0]146; CHECK-NEXT: vcge.s32 q8, q9, q8147; CHECK-NEXT: vmov r0, r1, d16148; CHECK-NEXT: vmov r2, r3, d17149; CHECK-NEXT: mov pc, lr150 %tmp1 = load <4 x i32>, ptr %A151 %tmp2 = load <4 x i32>, ptr %B152 %tmp3 = icmp sge <4 x i32> %tmp1, %tmp2153 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>154 ret <4 x i32> %tmp4155}156 157define <16 x i8> @vcgeQu8(ptr %A, ptr %B) nounwind {158; CHECK-LABEL: vcgeQu8:159; CHECK: @ %bb.0:160; CHECK-NEXT: vld1.64 {d16, d17}, [r1]161; CHECK-NEXT: vld1.64 {d18, d19}, [r0]162; CHECK-NEXT: vcge.u8 q8, q9, q8163; CHECK-NEXT: vmov r0, r1, d16164; CHECK-NEXT: vmov r2, r3, d17165; CHECK-NEXT: mov pc, lr166 %tmp1 = load <16 x i8>, ptr %A167 %tmp2 = load <16 x i8>, ptr %B168 %tmp3 = icmp uge <16 x i8> %tmp1, %tmp2169 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>170 ret <16 x i8> %tmp4171}172 173define <8 x i16> @vcgeQu16(ptr %A, ptr %B) nounwind {174; CHECK-LABEL: vcgeQu16:175; CHECK: @ %bb.0:176; CHECK-NEXT: vld1.64 {d16, d17}, [r1]177; CHECK-NEXT: vld1.64 {d18, d19}, [r0]178; CHECK-NEXT: vcge.u16 q8, q9, q8179; CHECK-NEXT: vmov r0, r1, d16180; CHECK-NEXT: vmov r2, r3, d17181; CHECK-NEXT: mov pc, lr182 %tmp1 = load <8 x i16>, ptr %A183 %tmp2 = load <8 x i16>, ptr %B184 %tmp3 = icmp uge <8 x i16> %tmp1, %tmp2185 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>186 ret <8 x i16> %tmp4187}188 189define <4 x i32> @vcgeQu32(ptr %A, ptr %B) nounwind {190; CHECK-LABEL: vcgeQu32:191; CHECK: @ %bb.0:192; CHECK-NEXT: vld1.64 {d16, d17}, [r1]193; CHECK-NEXT: vld1.64 {d18, d19}, [r0]194; CHECK-NEXT: vcge.u32 q8, q9, q8195; CHECK-NEXT: vmov r0, r1, d16196; CHECK-NEXT: vmov r2, r3, d17197; CHECK-NEXT: mov pc, lr198 %tmp1 = load <4 x i32>, ptr %A199 %tmp2 = load <4 x i32>, ptr %B200 %tmp3 = icmp uge <4 x i32> %tmp1, %tmp2201 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>202 ret <4 x i32> %tmp4203}204 205define <4 x i32> @vcgeQf32(ptr %A, ptr %B) nounwind {206; CHECK-LABEL: vcgeQf32:207; CHECK: @ %bb.0:208; CHECK-NEXT: vld1.64 {d16, d17}, [r1]209; CHECK-NEXT: vld1.64 {d18, d19}, [r0]210; CHECK-NEXT: vcge.f32 q8, q9, q8211; CHECK-NEXT: vmov r0, r1, d16212; CHECK-NEXT: vmov r2, r3, d17213; CHECK-NEXT: mov pc, lr214 %tmp1 = load <4 x float>, ptr %A215 %tmp2 = load <4 x float>, ptr %B216 %tmp3 = fcmp oge <4 x float> %tmp1, %tmp2217 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>218 ret <4 x i32> %tmp4219}220 221define <2 x i32> @vacgef32(ptr %A, ptr %B) nounwind {222; CHECK-LABEL: vacgef32:223; CHECK: @ %bb.0:224; CHECK-NEXT: vldr d16, [r1]225; CHECK-NEXT: vldr d17, [r0]226; CHECK-NEXT: vacge.f32 d16, d17, d16227; CHECK-NEXT: vmov r0, r1, d16228; CHECK-NEXT: mov pc, lr229 %tmp1 = load <2 x float>, ptr %A230 %tmp2 = load <2 x float>, ptr %B231 %tmp3 = call <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)232 ret <2 x i32> %tmp3233}234 235define <4 x i32> @vacgeQf32(ptr %A, ptr %B) nounwind {236; CHECK-LABEL: vacgeQf32:237; CHECK: @ %bb.0:238; CHECK-NEXT: vld1.64 {d16, d17}, [r1]239; CHECK-NEXT: vld1.64 {d18, d19}, [r0]240; CHECK-NEXT: vacge.f32 q8, q9, q8241; CHECK-NEXT: vmov r0, r1, d16242; CHECK-NEXT: vmov r2, r3, d17243; CHECK-NEXT: mov pc, lr244 %tmp1 = load <4 x float>, ptr %A245 %tmp2 = load <4 x float>, ptr %B246 %tmp3 = call <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)247 ret <4 x i32> %tmp3248}249 250declare <2 x i32> @llvm.arm.neon.vacge.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone251declare <4 x i32> @llvm.arm.neon.vacge.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone252 253define <8 x i8> @vcgei8Z(ptr %A) nounwind {254; CHECK-LABEL: vcgei8Z:255; CHECK: @ %bb.0:256; CHECK-NEXT: vldr d16, [r0]257; CHECK-NEXT: vcge.s8 d16, d16, #0258; CHECK-NEXT: vmov r0, r1, d16259; CHECK-NEXT: mov pc, lr260 %tmp1 = load <8 x i8>, ptr %A261 %tmp3 = icmp sge <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>262 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>263 ret <8 x i8> %tmp4264}265 266define <8 x i8> @vclei8Z(ptr %A) nounwind {267; CHECK-LABEL: vclei8Z:268; CHECK: @ %bb.0:269; CHECK-NEXT: vldr d16, [r0]270; CHECK-NEXT: vcle.s8 d16, d16, #0271; CHECK-NEXT: vmov r0, r1, d16272; CHECK-NEXT: mov pc, lr273 %tmp1 = load <8 x i8>, ptr %A274 %tmp3 = icmp sle <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>275 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>276 ret <8 x i8> %tmp4277}278 279; Radar 8782191280; Floating-point comparisons against zero produce results with integer281; elements, not floating-point elements.282define void @test_vclez_fp(ptr %A) nounwind optsize {283; CHECK-LABEL: test_vclez_fp:284; CHECK: @ %bb.0: @ %entry285; CHECK-NEXT: vld1.64 {d16, d17}, [r0]286; CHECK-NEXT: vcle.f32 q8, q8, #0287; CHECK-NEXT: vmovn.i32 d16, q8288; CHECK-NEXT: vmov.i8 d17, #0x1289; CHECK-NEXT: vuzp.8 d16, d18290; CHECK-NEXT: vadd.i8 d16, d16, d17291; CHECK-NEXT: vst1.8 {d16}, [r0]292entry:293 %ld = load <4 x float>, ptr %A294 %0 = fcmp ole <4 x float> %ld, zeroinitializer295 %1 = sext <4 x i1> %0 to <4 x i16>296 %2 = add <4 x i16> %1, zeroinitializer297 %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>298 %4 = add <8 x i16> %3, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>299 %5 = trunc <8 x i16> %4 to <8 x i8>300 tail call void @llvm.arm.neon.vst1.p0.v8i8(ptr undef, <8 x i8> %5, i32 1)301 unreachable302}303 304declare void @llvm.arm.neon.vst1.p0.v8i8(ptr, <8 x i8>, i32) nounwind305