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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon | FileCheck %s --check-prefixes=CHECK,ALLOC3; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon -regalloc=basic | FileCheck %s --check-prefixes=CHECK,BASIC4 5define <8 x i8> @vcgts8(ptr %A, ptr %B) nounwind {6; ALLOC-LABEL: vcgts8:7; ALLOC: @ %bb.0:8; ALLOC-NEXT: vldr d16, [r1]9; ALLOC-NEXT: vldr d17, [r0]10; ALLOC-NEXT: vcgt.s8 d16, d17, d1611; ALLOC-NEXT: vmov r0, r1, d1612; ALLOC-NEXT: mov pc, lr13;14; BASIC-LABEL: vcgts8:15; BASIC: @ %bb.0:16; BASIC-NEXT: vldr d17, [r1]17; BASIC-NEXT: vldr d16, [r0]18; BASIC-NEXT: vcgt.s8 d16, d16, d1719; BASIC-NEXT: vmov r0, r1, d1620; BASIC-NEXT: mov pc, lr21 %tmp1 = load <8 x i8>, ptr %A22 %tmp2 = load <8 x i8>, ptr %B23 %tmp3 = icmp sgt <8 x i8> %tmp1, %tmp224 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>25 ret <8 x i8> %tmp426}27 28define <4 x i16> @vcgts16(ptr %A, ptr %B) nounwind {29; ALLOC-LABEL: vcgts16:30; ALLOC: @ %bb.0:31; ALLOC-NEXT: vldr d16, [r1]32; ALLOC-NEXT: vldr d17, [r0]33; ALLOC-NEXT: vcgt.s16 d16, d17, d1634; ALLOC-NEXT: vmov r0, r1, d1635; ALLOC-NEXT: mov pc, lr36;37; BASIC-LABEL: vcgts16:38; BASIC: @ %bb.0:39; BASIC-NEXT: vldr d17, [r1]40; BASIC-NEXT: vldr d16, [r0]41; BASIC-NEXT: vcgt.s16 d16, d16, d1742; BASIC-NEXT: vmov r0, r1, d1643; BASIC-NEXT: mov pc, lr44 %tmp1 = load <4 x i16>, ptr %A45 %tmp2 = load <4 x i16>, ptr %B46 %tmp3 = icmp sgt <4 x i16> %tmp1, %tmp247 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>48 ret <4 x i16> %tmp449}50 51define <2 x i32> @vcgts32(ptr %A, ptr %B) nounwind {52; ALLOC-LABEL: vcgts32:53; ALLOC: @ %bb.0:54; ALLOC-NEXT: vldr d16, [r1]55; ALLOC-NEXT: vldr d17, [r0]56; ALLOC-NEXT: vcgt.s32 d16, d17, d1657; ALLOC-NEXT: vmov r0, r1, d1658; ALLOC-NEXT: mov pc, lr59;60; BASIC-LABEL: vcgts32:61; BASIC: @ %bb.0:62; BASIC-NEXT: vldr d17, [r1]63; BASIC-NEXT: vldr d16, [r0]64; BASIC-NEXT: vcgt.s32 d16, d16, d1765; BASIC-NEXT: vmov r0, r1, d1666; BASIC-NEXT: mov pc, lr67 %tmp1 = load <2 x i32>, ptr %A68 %tmp2 = load <2 x i32>, ptr %B69 %tmp3 = icmp sgt <2 x i32> %tmp1, %tmp270 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>71 ret <2 x i32> %tmp472}73 74define <8 x i8> @vcgtu8(ptr %A, ptr %B) nounwind {75; ALLOC-LABEL: vcgtu8:76; ALLOC: @ %bb.0:77; ALLOC-NEXT: vldr d16, [r1]78; ALLOC-NEXT: vldr d17, [r0]79; ALLOC-NEXT: vcgt.u8 d16, d17, d1680; ALLOC-NEXT: vmov r0, r1, d1681; ALLOC-NEXT: mov pc, lr82;83; BASIC-LABEL: vcgtu8:84; BASIC: @ %bb.0:85; BASIC-NEXT: vldr d17, [r1]86; BASIC-NEXT: vldr d16, [r0]87; BASIC-NEXT: vcgt.u8 d16, d16, d1788; BASIC-NEXT: vmov r0, r1, d1689; BASIC-NEXT: mov pc, lr90 %tmp1 = load <8 x i8>, ptr %A91 %tmp2 = load <8 x i8>, ptr %B92 %tmp3 = icmp ugt <8 x i8> %tmp1, %tmp293 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>94 ret <8 x i8> %tmp495}96 97define <4 x i16> @vcgtu16(ptr %A, ptr %B) nounwind {98; ALLOC-LABEL: vcgtu16:99; ALLOC: @ %bb.0:100; ALLOC-NEXT: vldr d16, [r1]101; ALLOC-NEXT: vldr d17, [r0]102; ALLOC-NEXT: vcgt.u16 d16, d17, d16103; ALLOC-NEXT: vmov r0, r1, d16104; ALLOC-NEXT: mov pc, lr105;106; BASIC-LABEL: vcgtu16:107; BASIC: @ %bb.0:108; BASIC-NEXT: vldr d17, [r1]109; BASIC-NEXT: vldr d16, [r0]110; BASIC-NEXT: vcgt.u16 d16, d16, d17111; BASIC-NEXT: vmov r0, r1, d16112; BASIC-NEXT: mov pc, lr113 %tmp1 = load <4 x i16>, ptr %A114 %tmp2 = load <4 x i16>, ptr %B115 %tmp3 = icmp ugt <4 x i16> %tmp1, %tmp2116 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>117 ret <4 x i16> %tmp4118}119 120define <2 x i32> @vcgtu32(ptr %A, ptr %B) nounwind {121; ALLOC-LABEL: vcgtu32:122; ALLOC: @ %bb.0:123; ALLOC-NEXT: vldr d16, [r1]124; ALLOC-NEXT: vldr d17, [r0]125; ALLOC-NEXT: vcgt.u32 d16, d17, d16126; ALLOC-NEXT: vmov r0, r1, d16127; ALLOC-NEXT: mov pc, lr128;129; BASIC-LABEL: vcgtu32:130; BASIC: @ %bb.0:131; BASIC-NEXT: vldr d17, [r1]132; BASIC-NEXT: vldr d16, [r0]133; BASIC-NEXT: vcgt.u32 d16, d16, d17134; BASIC-NEXT: vmov r0, r1, d16135; BASIC-NEXT: mov pc, lr136 %tmp1 = load <2 x i32>, ptr %A137 %tmp2 = load <2 x i32>, ptr %B138 %tmp3 = icmp ugt <2 x i32> %tmp1, %tmp2139 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>140 ret <2 x i32> %tmp4141}142 143define <2 x i32> @vcgtf32(ptr %A, ptr %B) nounwind {144; ALLOC-LABEL: vcgtf32:145; ALLOC: @ %bb.0:146; ALLOC-NEXT: vldr d16, [r1]147; ALLOC-NEXT: vldr d17, [r0]148; ALLOC-NEXT: vcgt.f32 d16, d17, d16149; ALLOC-NEXT: vmov r0, r1, d16150; ALLOC-NEXT: mov pc, lr151;152; BASIC-LABEL: vcgtf32:153; BASIC: @ %bb.0:154; BASIC-NEXT: vldr d17, [r1]155; BASIC-NEXT: vldr d16, [r0]156; BASIC-NEXT: vcgt.f32 d16, d16, d17157; BASIC-NEXT: vmov r0, r1, d16158; BASIC-NEXT: mov pc, lr159 %tmp1 = load <2 x float>, ptr %A160 %tmp2 = load <2 x float>, ptr %B161 %tmp3 = fcmp ogt <2 x float> %tmp1, %tmp2162 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>163 ret <2 x i32> %tmp4164}165 166define <16 x i8> @vcgtQs8(ptr %A, ptr %B) nounwind {167; ALLOC-LABEL: vcgtQs8:168; ALLOC: @ %bb.0:169; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]170; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]171; ALLOC-NEXT: vcgt.s8 q8, q9, q8172; ALLOC-NEXT: vmov r0, r1, d16173; ALLOC-NEXT: vmov r2, r3, d17174; ALLOC-NEXT: mov pc, lr175;176; BASIC-LABEL: vcgtQs8:177; BASIC: @ %bb.0:178; BASIC-NEXT: vld1.64 {d18, d19}, [r1]179; BASIC-NEXT: vld1.64 {d16, d17}, [r0]180; BASIC-NEXT: vcgt.s8 q8, q8, q9181; BASIC-NEXT: vmov r0, r1, d16182; BASIC-NEXT: vmov r2, r3, d17183; BASIC-NEXT: mov pc, lr184 %tmp1 = load <16 x i8>, ptr %A185 %tmp2 = load <16 x i8>, ptr %B186 %tmp3 = icmp sgt <16 x i8> %tmp1, %tmp2187 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>188 ret <16 x i8> %tmp4189}190 191define <8 x i16> @vcgtQs16(ptr %A, ptr %B) nounwind {192; ALLOC-LABEL: vcgtQs16:193; ALLOC: @ %bb.0:194; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]195; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]196; ALLOC-NEXT: vcgt.s16 q8, q9, q8197; ALLOC-NEXT: vmov r0, r1, d16198; ALLOC-NEXT: vmov r2, r3, d17199; ALLOC-NEXT: mov pc, lr200;201; BASIC-LABEL: vcgtQs16:202; BASIC: @ %bb.0:203; BASIC-NEXT: vld1.64 {d18, d19}, [r1]204; BASIC-NEXT: vld1.64 {d16, d17}, [r0]205; BASIC-NEXT: vcgt.s16 q8, q8, q9206; BASIC-NEXT: vmov r0, r1, d16207; BASIC-NEXT: vmov r2, r3, d17208; BASIC-NEXT: mov pc, lr209 %tmp1 = load <8 x i16>, ptr %A210 %tmp2 = load <8 x i16>, ptr %B211 %tmp3 = icmp sgt <8 x i16> %tmp1, %tmp2212 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>213 ret <8 x i16> %tmp4214}215 216define <4 x i32> @vcgtQs32(ptr %A, ptr %B) nounwind {217; ALLOC-LABEL: vcgtQs32:218; ALLOC: @ %bb.0:219; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]220; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]221; ALLOC-NEXT: vcgt.s32 q8, q9, q8222; ALLOC-NEXT: vmov r0, r1, d16223; ALLOC-NEXT: vmov r2, r3, d17224; ALLOC-NEXT: mov pc, lr225;226; BASIC-LABEL: vcgtQs32:227; BASIC: @ %bb.0:228; BASIC-NEXT: vld1.64 {d18, d19}, [r1]229; BASIC-NEXT: vld1.64 {d16, d17}, [r0]230; BASIC-NEXT: vcgt.s32 q8, q8, q9231; BASIC-NEXT: vmov r0, r1, d16232; BASIC-NEXT: vmov r2, r3, d17233; BASIC-NEXT: mov pc, lr234 %tmp1 = load <4 x i32>, ptr %A235 %tmp2 = load <4 x i32>, ptr %B236 %tmp3 = icmp sgt <4 x i32> %tmp1, %tmp2237 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>238 ret <4 x i32> %tmp4239}240 241define <16 x i8> @vcgtQu8(ptr %A, ptr %B) nounwind {242; ALLOC-LABEL: vcgtQu8:243; ALLOC: @ %bb.0:244; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]245; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]246; ALLOC-NEXT: vcgt.u8 q8, q9, q8247; ALLOC-NEXT: vmov r0, r1, d16248; ALLOC-NEXT: vmov r2, r3, d17249; ALLOC-NEXT: mov pc, lr250;251; BASIC-LABEL: vcgtQu8:252; BASIC: @ %bb.0:253; BASIC-NEXT: vld1.64 {d18, d19}, [r1]254; BASIC-NEXT: vld1.64 {d16, d17}, [r0]255; BASIC-NEXT: vcgt.u8 q8, q8, q9256; BASIC-NEXT: vmov r0, r1, d16257; BASIC-NEXT: vmov r2, r3, d17258; BASIC-NEXT: mov pc, lr259 %tmp1 = load <16 x i8>, ptr %A260 %tmp2 = load <16 x i8>, ptr %B261 %tmp3 = icmp ugt <16 x i8> %tmp1, %tmp2262 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>263 ret <16 x i8> %tmp4264}265 266define <8 x i16> @vcgtQu16(ptr %A, ptr %B) nounwind {267; ALLOC-LABEL: vcgtQu16:268; ALLOC: @ %bb.0:269; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]270; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]271; ALLOC-NEXT: vcgt.u16 q8, q9, q8272; ALLOC-NEXT: vmov r0, r1, d16273; ALLOC-NEXT: vmov r2, r3, d17274; ALLOC-NEXT: mov pc, lr275;276; BASIC-LABEL: vcgtQu16:277; BASIC: @ %bb.0:278; BASIC-NEXT: vld1.64 {d18, d19}, [r1]279; BASIC-NEXT: vld1.64 {d16, d17}, [r0]280; BASIC-NEXT: vcgt.u16 q8, q8, q9281; BASIC-NEXT: vmov r0, r1, d16282; BASIC-NEXT: vmov r2, r3, d17283; BASIC-NEXT: mov pc, lr284 %tmp1 = load <8 x i16>, ptr %A285 %tmp2 = load <8 x i16>, ptr %B286 %tmp3 = icmp ugt <8 x i16> %tmp1, %tmp2287 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>288 ret <8 x i16> %tmp4289}290 291define <4 x i32> @vcgtQu32(ptr %A, ptr %B) nounwind {292; ALLOC-LABEL: vcgtQu32:293; ALLOC: @ %bb.0:294; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]295; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]296; ALLOC-NEXT: vcgt.u32 q8, q9, q8297; ALLOC-NEXT: vmov r0, r1, d16298; ALLOC-NEXT: vmov r2, r3, d17299; ALLOC-NEXT: mov pc, lr300;301; BASIC-LABEL: vcgtQu32:302; BASIC: @ %bb.0:303; BASIC-NEXT: vld1.64 {d18, d19}, [r1]304; BASIC-NEXT: vld1.64 {d16, d17}, [r0]305; BASIC-NEXT: vcgt.u32 q8, q8, q9306; BASIC-NEXT: vmov r0, r1, d16307; BASIC-NEXT: vmov r2, r3, d17308; BASIC-NEXT: mov pc, lr309 %tmp1 = load <4 x i32>, ptr %A310 %tmp2 = load <4 x i32>, ptr %B311 %tmp3 = icmp ugt <4 x i32> %tmp1, %tmp2312 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>313 ret <4 x i32> %tmp4314}315 316define <4 x i32> @vcgtQf32(ptr %A, ptr %B) nounwind {317; ALLOC-LABEL: vcgtQf32:318; ALLOC: @ %bb.0:319; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]320; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]321; ALLOC-NEXT: vcgt.f32 q8, q9, q8322; ALLOC-NEXT: vmov r0, r1, d16323; ALLOC-NEXT: vmov r2, r3, d17324; ALLOC-NEXT: mov pc, lr325;326; BASIC-LABEL: vcgtQf32:327; BASIC: @ %bb.0:328; BASIC-NEXT: vld1.64 {d18, d19}, [r1]329; BASIC-NEXT: vld1.64 {d16, d17}, [r0]330; BASIC-NEXT: vcgt.f32 q8, q8, q9331; BASIC-NEXT: vmov r0, r1, d16332; BASIC-NEXT: vmov r2, r3, d17333; BASIC-NEXT: mov pc, lr334 %tmp1 = load <4 x float>, ptr %A335 %tmp2 = load <4 x float>, ptr %B336 %tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2337 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>338 ret <4 x i32> %tmp4339}340 341define <2 x i32> @vacgtf32(ptr %A, ptr %B) nounwind {342; ALLOC-LABEL: vacgtf32:343; ALLOC: @ %bb.0:344; ALLOC-NEXT: vldr d16, [r1]345; ALLOC-NEXT: vldr d17, [r0]346; ALLOC-NEXT: vacgt.f32 d16, d17, d16347; ALLOC-NEXT: vmov r0, r1, d16348; ALLOC-NEXT: mov pc, lr349;350; BASIC-LABEL: vacgtf32:351; BASIC: @ %bb.0:352; BASIC-NEXT: vldr d17, [r1]353; BASIC-NEXT: vldr d16, [r0]354; BASIC-NEXT: vacgt.f32 d16, d16, d17355; BASIC-NEXT: vmov r0, r1, d16356; BASIC-NEXT: mov pc, lr357 %tmp1 = load <2 x float>, ptr %A358 %tmp2 = load <2 x float>, ptr %B359 %tmp3 = call <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)360 ret <2 x i32> %tmp3361}362 363define <4 x i32> @vacgtQf32(ptr %A, ptr %B) nounwind {364; ALLOC-LABEL: vacgtQf32:365; ALLOC: @ %bb.0:366; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]367; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]368; ALLOC-NEXT: vacgt.f32 q8, q9, q8369; ALLOC-NEXT: vmov r0, r1, d16370; ALLOC-NEXT: vmov r2, r3, d17371; ALLOC-NEXT: mov pc, lr372;373; BASIC-LABEL: vacgtQf32:374; BASIC: @ %bb.0:375; BASIC-NEXT: vld1.64 {d18, d19}, [r1]376; BASIC-NEXT: vld1.64 {d16, d17}, [r0]377; BASIC-NEXT: vacgt.f32 q8, q8, q9378; BASIC-NEXT: vmov r0, r1, d16379; BASIC-NEXT: vmov r2, r3, d17380; BASIC-NEXT: mov pc, lr381 %tmp1 = load <4 x float>, ptr %A382 %tmp2 = load <4 x float>, ptr %B383 %tmp3 = call <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)384 ret <4 x i32> %tmp3385}386 387; rdar://7923010388define <4 x i32> @vcgt_zext(ptr %A, ptr %B) nounwind {389; ALLOC-LABEL: vcgt_zext:390; ALLOC: @ %bb.0:391; ALLOC-NEXT: vld1.64 {d16, d17}, [r1]392; ALLOC-NEXT: vld1.64 {d18, d19}, [r0]393; ALLOC-NEXT: vcgt.f32 q8, q9, q8394; ALLOC-NEXT: vmov.i32 q9, #0x1395; ALLOC-NEXT: vand q8, q8, q9396; ALLOC-NEXT: vmov r0, r1, d16397; ALLOC-NEXT: vmov r2, r3, d17398; ALLOC-NEXT: mov pc, lr399;400; BASIC-LABEL: vcgt_zext:401; BASIC: @ %bb.0:402; BASIC-NEXT: vld1.64 {d18, d19}, [r1]403; BASIC-NEXT: vld1.64 {d16, d17}, [r0]404; BASIC-NEXT: vcgt.f32 q9, q8, q9405; BASIC-NEXT: vmov.i32 q8, #0x1406; BASIC-NEXT: vand q8, q9, q8407; BASIC-NEXT: vmov r0, r1, d16408; BASIC-NEXT: vmov r2, r3, d17409; BASIC-NEXT: mov pc, lr410 %tmp1 = load <4 x float>, ptr %A411 %tmp2 = load <4 x float>, ptr %B412 %tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2413 %tmp4 = zext <4 x i1> %tmp3 to <4 x i32>414 ret <4 x i32> %tmp4415}416 417declare <2 x i32> @llvm.arm.neon.vacgt.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone418declare <4 x i32> @llvm.arm.neon.vacgt.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone419 420define <8 x i8> @vcgti8Z(ptr %A) nounwind {421; CHECK-LABEL: vcgti8Z:422; CHECK: @ %bb.0:423; CHECK-NEXT: vldr d16, [r0]424; CHECK-NEXT: vcgt.s8 d16, d16, #0425; CHECK-NEXT: vmov r0, r1, d16426; CHECK-NEXT: mov pc, lr427 %tmp1 = load <8 x i8>, ptr %A428 %tmp3 = icmp sgt <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>429 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>430 ret <8 x i8> %tmp4431}432 433define <8 x i8> @vclti8Z(ptr %A) nounwind {434; CHECK-LABEL: vclti8Z:435; CHECK: @ %bb.0:436; CHECK-NEXT: vldr d16, [r0]437; CHECK-NEXT: vclt.s8 d16, d16, #0438; CHECK-NEXT: vmov r0, r1, d16439; CHECK-NEXT: mov pc, lr440 %tmp1 = load <8 x i8>, ptr %A441 %tmp3 = icmp slt <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>442 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>443 ret <8 x i8> %tmp4444}445