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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=armv8-eabi -mattr=+neon | FileCheck %s3 4define arm_aapcs_vfpcc <4 x i32> @vcmpz_eq(<4 x i32> %0, <4 x i32> %b) {5; CHECK-LABEL: vcmpz_eq:6; CHECK: @ %bb.0:7; CHECK-NEXT: vceq.i32 q0, q0, q18; CHECK-NEXT: bx lr9 %2 = icmp eq <4 x i32> %0, %b10 %3 = sext <4 x i1> %2 to <4 x i32>11 ret <4 x i32> %312}13 14define arm_aapcs_vfpcc <4 x i32> @vcmpz_ne(<4 x i32> %0, <4 x i32> %b) {15; CHECK-LABEL: vcmpz_ne:16; CHECK: @ %bb.0:17; CHECK-NEXT: vceq.i32 q8, q0, q118; CHECK-NEXT: vmvn q0, q819; CHECK-NEXT: bx lr20 %2 = icmp ne <4 x i32> %0, %b21 %3 = sext <4 x i1> %2 to <4 x i32>22 ret <4 x i32> %323}24 25define arm_aapcs_vfpcc <4 x i32> @vcmpz_slt(<4 x i32> %0, <4 x i32> %b) {26; CHECK-LABEL: vcmpz_slt:27; CHECK: @ %bb.0:28; CHECK-NEXT: vcgt.s32 q0, q1, q029; CHECK-NEXT: bx lr30 %2 = icmp slt <4 x i32> %0, %b31 %3 = sext <4 x i1> %2 to <4 x i32>32 ret <4 x i32> %333}34 35define arm_aapcs_vfpcc <4 x i32> @vcmpz_sle(<4 x i32> %0, <4 x i32> %b) {36; CHECK-LABEL: vcmpz_sle:37; CHECK: @ %bb.0:38; CHECK-NEXT: vcge.s32 q0, q1, q039; CHECK-NEXT: bx lr40 %2 = icmp sle <4 x i32> %0, %b41 %3 = sext <4 x i1> %2 to <4 x i32>42 ret <4 x i32> %343}44 45define arm_aapcs_vfpcc <4 x i32> @vcmpz_sgt(<4 x i32> %0, <4 x i32> %b) {46; CHECK-LABEL: vcmpz_sgt:47; CHECK: @ %bb.0:48; CHECK-NEXT: vcgt.s32 q0, q0, q149; CHECK-NEXT: bx lr50 %2 = icmp sgt <4 x i32> %0, %b51 %3 = sext <4 x i1> %2 to <4 x i32>52 ret <4 x i32> %353}54 55define arm_aapcs_vfpcc <4 x i32> @vcmpz_sge(<4 x i32> %0, <4 x i32> %b) {56; CHECK-LABEL: vcmpz_sge:57; CHECK: @ %bb.0:58; CHECK-NEXT: vcge.s32 q0, q0, q159; CHECK-NEXT: bx lr60 %2 = icmp sge <4 x i32> %0, %b61 %3 = sext <4 x i1> %2 to <4 x i32>62 ret <4 x i32> %363}64 65define arm_aapcs_vfpcc <4 x i32> @vcmpz_ult(<4 x i32> %0, <4 x i32> %b) {66; CHECK-LABEL: vcmpz_ult:67; CHECK: @ %bb.0:68; CHECK-NEXT: vcgt.u32 q0, q1, q069; CHECK-NEXT: bx lr70 %2 = icmp ult <4 x i32> %0, %b71 %3 = sext <4 x i1> %2 to <4 x i32>72 ret <4 x i32> %373}74 75define arm_aapcs_vfpcc <4 x i32> @vcmpz_ule(<4 x i32> %0, <4 x i32> %b) {76; CHECK-LABEL: vcmpz_ule:77; CHECK: @ %bb.0:78; CHECK-NEXT: vcge.u32 q0, q1, q079; CHECK-NEXT: bx lr80 %2 = icmp ule <4 x i32> %0, %b81 %3 = sext <4 x i1> %2 to <4 x i32>82 ret <4 x i32> %383}84 85define arm_aapcs_vfpcc <4 x i32> @vcmpz_ugt(<4 x i32> %0, <4 x i32> %b) {86; CHECK-LABEL: vcmpz_ugt:87; CHECK: @ %bb.0:88; CHECK-NEXT: vcgt.u32 q0, q0, q189; CHECK-NEXT: bx lr90 %2 = icmp ugt <4 x i32> %0, %b91 %3 = sext <4 x i1> %2 to <4 x i32>92 ret <4 x i32> %393}94 95define arm_aapcs_vfpcc <4 x i32> @vcmpz_uge(<4 x i32> %0, <4 x i32> %b) {96; CHECK-LABEL: vcmpz_uge:97; CHECK: @ %bb.0:98; CHECK-NEXT: vcge.u32 q0, q0, q199; CHECK-NEXT: bx lr100 %2 = icmp uge <4 x i32> %0, %b101 %3 = sext <4 x i1> %2 to <4 x i32>102 ret <4 x i32> %3103}104 105 106define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_eq(<4 x i32> %0) {107; CHECK-LABEL: vcmpz_zr_eq:108; CHECK: @ %bb.0:109; CHECK-NEXT: vceq.i32 q0, q0, #0110; CHECK-NEXT: bx lr111 %2 = icmp eq <4 x i32> %0, zeroinitializer112 %3 = sext <4 x i1> %2 to <4 x i32>113 ret <4 x i32> %3114}115 116define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_ne(<4 x i32> %0) {117; CHECK-LABEL: vcmpz_zr_ne:118; CHECK: @ %bb.0:119; CHECK-NEXT: vceq.i32 q8, q0, #0120; CHECK-NEXT: vmvn q0, q8121; CHECK-NEXT: bx lr122 %2 = icmp ne <4 x i32> %0, zeroinitializer123 %3 = sext <4 x i1> %2 to <4 x i32>124 ret <4 x i32> %3125}126 127define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_slt(<4 x i32> %0) {128; CHECK-LABEL: vcmpz_zr_slt:129; CHECK: @ %bb.0:130; CHECK-NEXT: vclt.s32 q0, q0, #0131; CHECK-NEXT: bx lr132 %2 = icmp slt <4 x i32> %0, zeroinitializer133 %3 = sext <4 x i1> %2 to <4 x i32>134 ret <4 x i32> %3135}136 137define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_sle(<4 x i32> %0) {138; CHECK-LABEL: vcmpz_zr_sle:139; CHECK: @ %bb.0:140; CHECK-NEXT: vcle.s32 q0, q0, #0141; CHECK-NEXT: bx lr142 %2 = icmp sle <4 x i32> %0, zeroinitializer143 %3 = sext <4 x i1> %2 to <4 x i32>144 ret <4 x i32> %3145}146 147define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_sgt(<4 x i32> %0) {148; CHECK-LABEL: vcmpz_zr_sgt:149; CHECK: @ %bb.0:150; CHECK-NEXT: vcgt.s32 q0, q0, #0151; CHECK-NEXT: bx lr152 %2 = icmp sgt <4 x i32> %0, zeroinitializer153 %3 = sext <4 x i1> %2 to <4 x i32>154 ret <4 x i32> %3155}156 157define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_sge(<4 x i32> %0) {158; CHECK-LABEL: vcmpz_zr_sge:159; CHECK: @ %bb.0:160; CHECK-NEXT: vcge.s32 q0, q0, #0161; CHECK-NEXT: bx lr162 %2 = icmp sge <4 x i32> %0, zeroinitializer163 %3 = sext <4 x i1> %2 to <4 x i32>164 ret <4 x i32> %3165}166 167define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_ult(<4 x i32> %0) {168; CHECK-LABEL: vcmpz_zr_ult:169; CHECK: @ %bb.0:170; CHECK-NEXT: vmov.i32 q0, #0x0171; CHECK-NEXT: bx lr172 %2 = icmp ult <4 x i32> %0, zeroinitializer173 %3 = sext <4 x i1> %2 to <4 x i32>174 ret <4 x i32> %3175}176 177define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_ule(<4 x i32> %0) {178; CHECK-LABEL: vcmpz_zr_ule:179; CHECK: @ %bb.0:180; CHECK-NEXT: vmov.i32 q8, #0x0181; CHECK-NEXT: vcge.u32 q0, q8, q0182; CHECK-NEXT: bx lr183 %2 = icmp ule <4 x i32> %0, zeroinitializer184 %3 = sext <4 x i1> %2 to <4 x i32>185 ret <4 x i32> %3186}187 188define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_ugt(<4 x i32> %0) {189; CHECK-LABEL: vcmpz_zr_ugt:190; CHECK: @ %bb.0:191; CHECK-NEXT: vceq.i32 q8, q0, #0192; CHECK-NEXT: vmvn q0, q8193; CHECK-NEXT: bx lr194 %2 = icmp ugt <4 x i32> %0, zeroinitializer195 %3 = sext <4 x i1> %2 to <4 x i32>196 ret <4 x i32> %3197}198 199define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_uge(<4 x i32> %0) {200; CHECK-LABEL: vcmpz_zr_uge:201; CHECK: @ %bb.0:202; CHECK-NEXT: vmov.i8 q0, #0xff203; CHECK-NEXT: bx lr204 %2 = icmp uge <4 x i32> %0, zeroinitializer205 %3 = sext <4 x i1> %2 to <4 x i32>206 ret <4 x i32> %3207}208 209 210define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_eq(<4 x i32> %0) {211; CHECK-LABEL: vcmpz_zl_eq:212; CHECK: @ %bb.0:213; CHECK-NEXT: vceq.i32 q0, q0, #0214; CHECK-NEXT: bx lr215 %2 = icmp eq <4 x i32> zeroinitializer, %0216 %3 = sext <4 x i1> %2 to <4 x i32>217 ret <4 x i32> %3218}219 220define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_ne(<4 x i32> %0) {221; CHECK-LABEL: vcmpz_zl_ne:222; CHECK: @ %bb.0:223; CHECK-NEXT: vceq.i32 q8, q0, #0224; CHECK-NEXT: vmvn q0, q8225; CHECK-NEXT: bx lr226 %2 = icmp ne <4 x i32> zeroinitializer, %0227 %3 = sext <4 x i1> %2 to <4 x i32>228 ret <4 x i32> %3229}230 231define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_slt(<4 x i32> %0) {232; CHECK-LABEL: vcmpz_zl_slt:233; CHECK: @ %bb.0:234; CHECK-NEXT: vcgt.s32 q0, q0, #0235; CHECK-NEXT: bx lr236 %2 = icmp slt <4 x i32> zeroinitializer, %0237 %3 = sext <4 x i1> %2 to <4 x i32>238 ret <4 x i32> %3239}240 241define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_sle(<4 x i32> %0) {242; CHECK-LABEL: vcmpz_zl_sle:243; CHECK: @ %bb.0:244; CHECK-NEXT: vcge.s32 q0, q0, #0245; CHECK-NEXT: bx lr246 %2 = icmp sle <4 x i32> zeroinitializer, %0247 %3 = sext <4 x i1> %2 to <4 x i32>248 ret <4 x i32> %3249}250 251define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_sgt(<4 x i32> %0) {252; CHECK-LABEL: vcmpz_zl_sgt:253; CHECK: @ %bb.0:254; CHECK-NEXT: vclt.s32 q0, q0, #0255; CHECK-NEXT: bx lr256 %2 = icmp sgt <4 x i32> zeroinitializer, %0257 %3 = sext <4 x i1> %2 to <4 x i32>258 ret <4 x i32> %3259}260 261define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_sge(<4 x i32> %0) {262; CHECK-LABEL: vcmpz_zl_sge:263; CHECK: @ %bb.0:264; CHECK-NEXT: vcle.s32 q0, q0, #0265; CHECK-NEXT: bx lr266 %2 = icmp sge <4 x i32> zeroinitializer, %0267 %3 = sext <4 x i1> %2 to <4 x i32>268 ret <4 x i32> %3269}270 271define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_ult(<4 x i32> %0) {272; CHECK-LABEL: vcmpz_zl_ult:273; CHECK: @ %bb.0:274; CHECK-NEXT: vceq.i32 q8, q0, #0275; CHECK-NEXT: vmvn q0, q8276; CHECK-NEXT: bx lr277 %2 = icmp ult <4 x i32> zeroinitializer, %0278 %3 = sext <4 x i1> %2 to <4 x i32>279 ret <4 x i32> %3280}281 282define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_ule(<4 x i32> %0) {283; CHECK-LABEL: vcmpz_zl_ule:284; CHECK: @ %bb.0:285; CHECK-NEXT: vmov.i8 q0, #0xff286; CHECK-NEXT: bx lr287 %2 = icmp ule <4 x i32> zeroinitializer, %0288 %3 = sext <4 x i1> %2 to <4 x i32>289 ret <4 x i32> %3290}291 292define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_ugt(<4 x i32> %0) {293; CHECK-LABEL: vcmpz_zl_ugt:294; CHECK: @ %bb.0:295; CHECK-NEXT: vmov.i32 q0, #0x0296; CHECK-NEXT: bx lr297 %2 = icmp ugt <4 x i32> zeroinitializer, %0298 %3 = sext <4 x i1> %2 to <4 x i32>299 ret <4 x i32> %3300}301 302define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_uge(<4 x i32> %0) {303; CHECK-LABEL: vcmpz_zl_uge:304; CHECK: @ %bb.0:305; CHECK-NEXT: vmov.i32 q8, #0x0306; CHECK-NEXT: vcge.u32 q0, q8, q0307; CHECK-NEXT: bx lr308 %2 = icmp uge <4 x i32> zeroinitializer, %0309 %3 = sext <4 x i1> %2 to <4 x i32>310 ret <4 x i32> %3311}312