146 lines · plain
1; RUN: llc < %s -mtriple=armv8 -mattr=+neon | FileCheck %s2define <4 x i32> @vcvtasq(ptr %A) {3; CHECK: vcvtasq4; CHECK: vcvta.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}5 %tmp1 = load <4 x float>, ptr %A6 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %tmp1)7 ret <4 x i32> %tmp28}9 10define <2 x i32> @vcvtasd(ptr %A) {11; CHECK: vcvtasd12; CHECK: vcvta.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}13 %tmp1 = load <2 x float>, ptr %A14 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %tmp1)15 ret <2 x i32> %tmp216}17 18define <4 x i32> @vcvtnsq(ptr %A) {19; CHECK: vcvtnsq20; CHECK: vcvtn.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}21 %tmp1 = load <4 x float>, ptr %A22 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %tmp1)23 ret <4 x i32> %tmp224}25 26define <2 x i32> @vcvtnsd(ptr %A) {27; CHECK: vcvtnsd28; CHECK: vcvtn.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}29 %tmp1 = load <2 x float>, ptr %A30 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %tmp1)31 ret <2 x i32> %tmp232}33 34define <4 x i32> @vcvtpsq(ptr %A) {35; CHECK: vcvtpsq36; CHECK: vcvtp.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}37 %tmp1 = load <4 x float>, ptr %A38 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %tmp1)39 ret <4 x i32> %tmp240}41 42define <2 x i32> @vcvtpsd(ptr %A) {43; CHECK: vcvtpsd44; CHECK: vcvtp.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}45 %tmp1 = load <2 x float>, ptr %A46 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %tmp1)47 ret <2 x i32> %tmp248}49 50define <4 x i32> @vcvtmsq(ptr %A) {51; CHECK: vcvtmsq52; CHECK: vcvtm.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}53 %tmp1 = load <4 x float>, ptr %A54 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float> %tmp1)55 ret <4 x i32> %tmp256}57 58define <2 x i32> @vcvtmsd(ptr %A) {59; CHECK: vcvtmsd60; CHECK: vcvtm.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}61 %tmp1 = load <2 x float>, ptr %A62 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float> %tmp1)63 ret <2 x i32> %tmp264}65 66define <4 x i32> @vcvtauq(ptr %A) {67; CHECK: vcvtauq68; CHECK: vcvta.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}69 %tmp1 = load <4 x float>, ptr %A70 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %tmp1)71 ret <4 x i32> %tmp272}73 74define <2 x i32> @vcvtaud(ptr %A) {75; CHECK: vcvtaud76; CHECK: vcvta.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}77 %tmp1 = load <2 x float>, ptr %A78 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %tmp1)79 ret <2 x i32> %tmp280}81 82define <4 x i32> @vcvtnuq(ptr %A) {83; CHECK: vcvtnuq84; CHECK: vcvtn.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}85 %tmp1 = load <4 x float>, ptr %A86 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %tmp1)87 ret <4 x i32> %tmp288}89 90define <2 x i32> @vcvtnud(ptr %A) {91; CHECK: vcvtnud92; CHECK: vcvtn.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}93 %tmp1 = load <2 x float>, ptr %A94 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %tmp1)95 ret <2 x i32> %tmp296}97 98define <4 x i32> @vcvtpuq(ptr %A) {99; CHECK: vcvtpuq100; CHECK: vcvtp.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}101 %tmp1 = load <4 x float>, ptr %A102 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %tmp1)103 ret <4 x i32> %tmp2104}105 106define <2 x i32> @vcvtpud(ptr %A) {107; CHECK: vcvtpud108; CHECK: vcvtp.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}109 %tmp1 = load <2 x float>, ptr %A110 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %tmp1)111 ret <2 x i32> %tmp2112}113 114define <4 x i32> @vcvtmuq(ptr %A) {115; CHECK: vcvtmuq116; CHECK: vcvtm.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}117 %tmp1 = load <4 x float>, ptr %A118 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float> %tmp1)119 ret <4 x i32> %tmp2120}121 122define <2 x i32> @vcvtmud(ptr %A) {123; CHECK: vcvtmud124; CHECK: vcvtm.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}125 %tmp1 = load <2 x float>, ptr %A126 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtmu.v2i32.v2f32(<2 x float> %tmp1)127 ret <2 x i32> %tmp2128}129 130declare <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float>) nounwind readnone131declare <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float>) nounwind readnone132declare <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float>) nounwind readnone133declare <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float>) nounwind readnone134declare <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float>) nounwind readnone135declare <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float>) nounwind readnone136declare <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float>) nounwind readnone137declare <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float>) nounwind readnone138declare <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float>) nounwind readnone139declare <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float>) nounwind readnone140declare <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float>) nounwind readnone141declare <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float>) nounwind readnone142declare <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float>) nounwind readnone143declare <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float>) nounwind readnone144declare <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float>) nounwind readnone145declare <2 x i32> @llvm.arm.neon.vcvtmu.v2i32.v2f32(<2 x float>) nounwind readnone146