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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s3 4; Test signed conversion.5define arm_aapcs_vfpcc <2 x float> @t1(<2 x i32> %vecinit2.i) nounwind {6; CHECK-LABEL: t1:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: vcvt.f32.s32 d0, d0, #39; CHECK-NEXT: bx lr10entry:11 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>12 %div.i = fdiv <2 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00>13 ret <2 x float> %div.i14}15 16; Test unsigned conversion.17define arm_aapcs_vfpcc <2 x float> @t2(<2 x i32> %vecinit2.i) nounwind {18; CHECK-LABEL: t2:19; CHECK: @ %bb.0: @ %entry20; CHECK-NEXT: vcvt.f32.u32 d0, d0, #321; CHECK-NEXT: bx lr22entry:23 %vcvt.i = uitofp <2 x i32> %vecinit2.i to <2 x float>24 %div.i = fdiv <2 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00>25 ret <2 x float> %div.i26}27 28; Test which should not fold due to non-power of 2.29define arm_aapcs_vfpcc <2 x float> @t3(<2 x i32> %vecinit2.i) nounwind {30; CHECK-LABEL: t3:31; CHECK: @ %bb.0: @ %entry32; CHECK-NEXT: vcvt.f32.s32 d2, d033; CHECK-NEXT: vldr s2, LCPI2_034; CHECK-NEXT: vdiv.f32 s1, s5, s235; CHECK-NEXT: vdiv.f32 s0, s4, s236; CHECK-NEXT: bx lr37; CHECK-NEXT: .p2align 238; CHECK-NEXT: @ %bb.1:39; CHECK-NEXT: .data_region40; CHECK-NEXT: LCPI2_0:41; CHECK-NEXT: .long 0x40d9999a @ float 6.8000001942; CHECK-NEXT: .end_data_region43entry:44 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>45 %div.i = fdiv <2 x float> %vcvt.i, <float 0x401B333340000000, float 0x401B333340000000>46 ret <2 x float> %div.i47}48 49; Test which should not fold due to power of 2 out of range.50define arm_aapcs_vfpcc <2 x float> @t4(<2 x i32> %vecinit2.i) nounwind {51; CHECK-LABEL: t4:52; CHECK: @ %bb.0: @ %entry53; CHECK-NEXT: vcvt.f32.s32 d16, d054; CHECK-NEXT: vmov.i32 d17, #0x2f00000055; CHECK-NEXT: vmul.f32 d0, d16, d1756; CHECK-NEXT: bx lr57entry:58 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>59 %div.i = fdiv <2 x float> %vcvt.i, <float 0x4200000000000000, float 0x4200000000000000>60 ret <2 x float> %div.i61}62 63; Test case where const is max power of 2 (i.e., 2^32).64define arm_aapcs_vfpcc <2 x float> @t5(<2 x i32> %vecinit2.i) nounwind {65; CHECK-LABEL: t5:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vcvt.f32.s32 d0, d0, #3268; CHECK-NEXT: bx lr69entry:70 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>71 %div.i = fdiv <2 x float> %vcvt.i, <float 0x41F0000000000000, float 0x41F0000000000000>72 ret <2 x float> %div.i73}74 75; Test quadword.76define arm_aapcs_vfpcc <4 x float> @t6(<4 x i32> %vecinit6.i) nounwind {77; CHECK-LABEL: t6:78; CHECK: @ %bb.0: @ %entry79; CHECK-NEXT: vcvt.f32.s32 q0, q0, #380; CHECK-NEXT: bx lr81entry:82 %vcvt.i = sitofp <4 x i32> %vecinit6.i to <4 x float>83 %div.i = fdiv <4 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>84 ret <4 x float> %div.i85}86 87define arm_aapcs_vfpcc <4 x float> @fix_unsigned_i16_to_float(<4 x i16> %in) {88; CHECK-LABEL: fix_unsigned_i16_to_float:89; CHECK: @ %bb.0:90; CHECK-NEXT: vmovl.u16 q8, d091; CHECK-NEXT: vcvt.f32.u32 q0, q8, #192; CHECK-NEXT: bx lr93 %conv = uitofp <4 x i16> %in to <4 x float>94 %shift = fdiv <4 x float> %conv, <float 2.0, float 2.0, float 2.0, float 2.0>95 ret <4 x float> %shift96}97 98define arm_aapcs_vfpcc <4 x float> @fix_signed_i16_to_float(<4 x i16> %in) {99; CHECK-LABEL: fix_signed_i16_to_float:100; CHECK: @ %bb.0:101; CHECK-NEXT: vmovl.s16 q8, d0102; CHECK-NEXT: vcvt.f32.s32 q0, q8, #1103; CHECK-NEXT: bx lr104 %conv = sitofp <4 x i16> %in to <4 x float>105 %shift = fdiv <4 x float> %conv, <float 2.0, float 2.0, float 2.0, float 2.0>106 ret <4 x float> %shift107}108 109define arm_aapcs_vfpcc <2 x float> @fix_i64_to_float(<2 x i64> %in) {110; CHECK-LABEL: fix_i64_to_float:111; CHECK: @ %bb.0:112; CHECK-NEXT: push {lr}113; CHECK-NEXT: vpush {d8, d9}114; CHECK-NEXT: vorr q4, q0, q0115; CHECK-NEXT: vmov r0, r1, d9116; CHECK-NEXT: bl ___floatundisf117; CHECK-NEXT: vmov r2, r1, d8118; CHECK-NEXT: vmov s19, r0119; CHECK-NEXT: vmov.i32 d8, #0x3f000000120; CHECK-NEXT: mov r0, r2121; CHECK-NEXT: bl ___floatundisf122; CHECK-NEXT: vmov s18, r0123; CHECK-NEXT: vmul.f32 d0, d9, d8124; CHECK-NEXT: vpop {d8, d9}125; CHECK-NEXT: pop {lr}126; CHECK-NEXT: bx lr127 %conv = uitofp <2 x i64> %in to <2 x float>128 %shift = fdiv <2 x float> %conv, <float 2.0, float 2.0>129 ret <2 x float> %shift130}131 132define arm_aapcs_vfpcc <2 x double> @fix_i64_to_double(<2 x i64> %in) {133; CHECK-LABEL: fix_i64_to_double:134; CHECK: @ %bb.0:135; CHECK-NEXT: push {lr}136; CHECK-NEXT: vpush {d8, d9}137; CHECK-NEXT: vorr q4, q0, q0138; CHECK-NEXT: vmov r0, r1, d9139; CHECK-NEXT: bl ___floatundidf140; CHECK-NEXT: vmov r2, r3, d8141; CHECK-NEXT: vmov d9, r0, r1142; CHECK-NEXT: vmov.f64 d8, #5.000000e-01143; CHECK-NEXT: mov r0, r2144; CHECK-NEXT: mov r1, r3145; CHECK-NEXT: bl ___floatundidf146; CHECK-NEXT: vmov d16, r0, r1147; CHECK-NEXT: vmul.f64 d1, d9, d8148; CHECK-NEXT: vmul.f64 d0, d16, d8149; CHECK-NEXT: vpop {d8, d9}150; CHECK-NEXT: pop {lr}151; CHECK-NEXT: bx lr152 %conv = uitofp <2 x i64> %in to <2 x double>153 %shift = fdiv <2 x double> %conv, <double 2.0, double 2.0>154 ret <2 x double> %shift155}156 157; Don't combine with 8 lanes. Just make sure things don't crash.158define arm_aapcs_vfpcc <8 x float> @test7(<8 x i32> %in) nounwind {159; CHECK-LABEL: test7:160; CHECK: @ %bb.0: @ %entry161; CHECK-NEXT: vcvt.f32.s32 q0, q0, #3162; CHECK-NEXT: vcvt.f32.s32 q1, q1, #3163; CHECK-NEXT: bx lr164entry:165 %vcvt.i = sitofp <8 x i32> %in to <8 x float>166 %div.i = fdiv <8 x float> %vcvt.i, <float 8.0, float 8.0, float 8.0, float 8.0, float 8.0, float 8.0, float 8.0, float 8.0>167 ret <8 x float> %div.i168}169 170; Can combine splat with an undef.171define arm_aapcs_vfpcc <4 x float> @test8(<4 x i32> %in) {172; CHECK-LABEL: test8:173; CHECK: @ %bb.0:174; CHECK-NEXT: vcvt.f32.s32 q0, q0, #1175; CHECK-NEXT: bx lr176 %vcvt.i = sitofp <4 x i32> %in to <4 x float>177 %div.i = fdiv <4 x float> %vcvt.i, <float 2.0, float 2.0, float 2.0, float undef>178 ret <4 x float> %div.i179}180 181define arm_aapcs_vfpcc <3 x float> @test_illegal_int_to_fp(<3 x i32> %in) {182; CHECK-LABEL: test_illegal_int_to_fp:183; CHECK: @ %bb.0:184; CHECK-NEXT: vcvt.f32.s32 q0, q0, #2185; CHECK-NEXT: bx lr186 %conv = sitofp <3 x i32> %in to <3 x float>187 %res = fdiv <3 x float> %conv, <float 4.0, float 4.0, float 4.0>188 ret <3 x float> %res189}190 191 192define arm_aapcs_vfpcc <2 x float> @t1_mul(<2 x i32> %vecinit2.i) local_unnamed_addr #0 {193; CHECK-LABEL: t1_mul:194; CHECK: @ %bb.0: @ %entry195; CHECK-NEXT: vcvt.f32.s32 d0, d0, #3196; CHECK-NEXT: bx lr197entry:198 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>199 %div.i = fmul <2 x float> %vcvt.i, <float 1.250000e-01, float 1.250000e-01>200 ret <2 x float> %div.i201}202 203define arm_aapcs_vfpcc <2 x float> @t2_mul(<2 x i32> %vecinit2.i) local_unnamed_addr #0 {204; CHECK-LABEL: t2_mul:205; CHECK: @ %bb.0: @ %entry206; CHECK-NEXT: vcvt.f32.u32 d0, d0, #3207; CHECK-NEXT: bx lr208entry:209 %vcvt.i = uitofp <2 x i32> %vecinit2.i to <2 x float>210 %div.i = fmul <2 x float> %vcvt.i, <float 1.250000e-01, float 1.250000e-01>211 ret <2 x float> %div.i212}213 214define arm_aapcs_vfpcc <2 x float> @t4_mul(<2 x i32> %vecinit2.i) local_unnamed_addr #0 {215; CHECK-LABEL: t4_mul:216; CHECK: @ %bb.0: @ %entry217; CHECK-NEXT: vcvt.f32.s32 d16, d0218; CHECK-NEXT: vmov.i32 d17, #0x2f000000219; CHECK-NEXT: vmul.f32 d0, d16, d17220; CHECK-NEXT: bx lr221entry:222 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>223 %div.i = fmul <2 x float> %vcvt.i, <float 0x3DE0000000000000, float 0x3DE0000000000000>224 ret <2 x float> %div.i225}226 227define arm_aapcs_vfpcc <2 x float> @t5_mul(<2 x i32> %vecinit2.i) local_unnamed_addr #0 {228; CHECK-LABEL: t5_mul:229; CHECK: @ %bb.0: @ %entry230; CHECK-NEXT: vcvt.f32.s32 d0, d0, #32231; CHECK-NEXT: bx lr232entry:233 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>234 %div.i = fmul <2 x float> %vcvt.i, <float 0x3DF0000000000000, float 0x3DF0000000000000>235 ret <2 x float> %div.i236}237 238define arm_aapcs_vfpcc <4 x float> @t6_mul(<4 x i32> %vecinit6.i) local_unnamed_addr #0 {239; CHECK-LABEL: t6_mul:240; CHECK: @ %bb.0: @ %entry241; CHECK-NEXT: vcvt.f32.s32 q0, q0, #3242; CHECK-NEXT: bx lr243entry:244 %vcvt.i = sitofp <4 x i32> %vecinit6.i to <4 x float>245 %div.i = fmul <4 x float> %vcvt.i, <float 1.250000e-01, float 1.250000e-01, float 1.250000e-01, float 1.250000e-01>246 ret <4 x float> %div.i247}248 249define arm_aapcs_vfpcc <4 x float> @fix_unsigned_i16_to_float_mul(<4 x i16> %in) local_unnamed_addr #0 {250; CHECK-LABEL: fix_unsigned_i16_to_float_mul:251; CHECK: @ %bb.0:252; CHECK-NEXT: vmovl.u16 q8, d0253; CHECK-NEXT: vcvt.f32.u32 q0, q8, #1254; CHECK-NEXT: bx lr255 %conv = uitofp <4 x i16> %in to <4 x float>256 %shift = fmul <4 x float> %conv, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01>257 ret <4 x float> %shift258}259 260define arm_aapcs_vfpcc <4 x float> @fix_signed_i16_to_float_mul(<4 x i16> %in) local_unnamed_addr #0 {261; CHECK-LABEL: fix_signed_i16_to_float_mul:262; CHECK: @ %bb.0:263; CHECK-NEXT: vmovl.s16 q8, d0264; CHECK-NEXT: vcvt.f32.s32 q0, q8, #1265; CHECK-NEXT: bx lr266 %conv = sitofp <4 x i16> %in to <4 x float>267 %shift = fmul <4 x float> %conv, <float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01>268 ret <4 x float> %shift269}270 271define arm_aapcs_vfpcc <2 x float> @fix_i64_to_float_mul(<2 x i64> %in) local_unnamed_addr #0 {272; CHECK-LABEL: fix_i64_to_float_mul:273; CHECK: @ %bb.0:274; CHECK-NEXT: push {lr}275; CHECK-NEXT: vpush {d8, d9}276; CHECK-NEXT: vorr q4, q0, q0277; CHECK-NEXT: vmov r0, r1, d9278; CHECK-NEXT: bl ___floatundisf279; CHECK-NEXT: vmov r2, r1, d8280; CHECK-NEXT: vmov s19, r0281; CHECK-NEXT: vmov.i32 d8, #0x3f000000282; CHECK-NEXT: mov r0, r2283; CHECK-NEXT: bl ___floatundisf284; CHECK-NEXT: vmov s18, r0285; CHECK-NEXT: vmul.f32 d0, d9, d8286; CHECK-NEXT: vpop {d8, d9}287; CHECK-NEXT: pop {lr}288; CHECK-NEXT: bx lr289 %conv = uitofp <2 x i64> %in to <2 x float>290 %shift = fmul <2 x float> %conv, <float 5.000000e-01, float 5.000000e-01>291 ret <2 x float> %shift292}293 294define arm_aapcs_vfpcc <2 x double> @fix_i64_to_double_mul(<2 x i64> %in) local_unnamed_addr #0 {295; CHECK-LABEL: fix_i64_to_double_mul:296; CHECK: @ %bb.0:297; CHECK-NEXT: push {lr}298; CHECK-NEXT: vpush {d8, d9}299; CHECK-NEXT: vorr q4, q0, q0300; CHECK-NEXT: vmov r0, r1, d9301; CHECK-NEXT: bl ___floatundidf302; CHECK-NEXT: vmov r2, r3, d8303; CHECK-NEXT: vmov d9, r0, r1304; CHECK-NEXT: vmov.f64 d8, #5.000000e-01305; CHECK-NEXT: mov r0, r2306; CHECK-NEXT: mov r1, r3307; CHECK-NEXT: bl ___floatundidf308; CHECK-NEXT: vmov d16, r0, r1309; CHECK-NEXT: vmul.f64 d1, d9, d8310; CHECK-NEXT: vmul.f64 d0, d16, d8311; CHECK-NEXT: vpop {d8, d9}312; CHECK-NEXT: pop {lr}313; CHECK-NEXT: bx lr314 %conv = uitofp <2 x i64> %in to <2 x double>315 %shift = fmul <2 x double> %conv, <double 5.000000e-01, double 5.000000e-01>316 ret <2 x double> %shift317}318 319define arm_aapcs_vfpcc <8 x float> @test7_mul(<8 x i32> %in) local_unnamed_addr #0 {320; CHECK-LABEL: test7_mul:321; CHECK: @ %bb.0: @ %entry322; CHECK-NEXT: vcvt.f32.s32 q0, q0, #3323; CHECK-NEXT: vcvt.f32.s32 q1, q1, #3324; CHECK-NEXT: bx lr325entry:326 %vcvt.i = sitofp <8 x i32> %in to <8 x float>327 %div.i = fmul <8 x float> %vcvt.i, <float 1.250000e-01, float 1.250000e-01, float 1.250000e-01, float 1.250000e-01, float 1.250000e-01, float 1.250000e-01, float 1.250000e-01, float 1.250000e-01>328 ret <8 x float> %div.i329}330 331define arm_aapcs_vfpcc <3 x float> @test_illegal_int_to_fp_mul(<3 x i32> %in) local_unnamed_addr #0 {332; CHECK-LABEL: test_illegal_int_to_fp_mul:333; CHECK: @ %bb.0:334; CHECK-NEXT: vcvt.f32.s32 q0, q0, #2335; CHECK-NEXT: bx lr336 %conv = sitofp <3 x i32> %in to <3 x float>337 %res = fmul <3 x float> %conv, <float 2.500000e-01, float 2.500000e-01, float 2.500000e-01>338 ret <3 x float> %res339}340