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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm-none-eabi -mattr=-neon | FileCheck %s --check-prefix=CHECK3 4declare half @llvm.vector.reduce.fadd.f16.v4f16(half, <4 x half>)5declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)6declare double @llvm.vector.reduce.fadd.f64.v2f64(double, <2 x double>)7declare fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128, <2 x fp128>)8 9define half @test_v4f16_reassoc(<4 x half> %a) nounwind {10; CHECK-LABEL: test_v4f16_reassoc:11; CHECK: @ %bb.0:12; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}13; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}14; CHECK-NEXT: mov r8, #25515; CHECK-NEXT: mov r4, r316; CHECK-NEXT: orr r8, r8, #6528017; CHECK-NEXT: mov r5, r218; CHECK-NEXT: and r0, r0, r819; CHECK-NEXT: mov r6, r120; CHECK-NEXT: bl __aeabi_h2f21; CHECK-NEXT: mov r7, r022; CHECK-NEXT: and r0, r6, r823; CHECK-NEXT: bl __aeabi_h2f24; CHECK-NEXT: mov r1, r025; CHECK-NEXT: mov r0, r726; CHECK-NEXT: bl __aeabi_fadd27; CHECK-NEXT: bl __aeabi_f2h28; CHECK-NEXT: mov r6, r029; CHECK-NEXT: and r0, r5, r830; CHECK-NEXT: bl __aeabi_h2f31; CHECK-NEXT: mov r5, r032; CHECK-NEXT: and r0, r6, r833; CHECK-NEXT: bl __aeabi_h2f34; CHECK-NEXT: mov r1, r535; CHECK-NEXT: bl __aeabi_fadd36; CHECK-NEXT: bl __aeabi_f2h37; CHECK-NEXT: mov r5, r038; CHECK-NEXT: and r0, r4, r839; CHECK-NEXT: bl __aeabi_h2f40; CHECK-NEXT: mov r4, r041; CHECK-NEXT: and r0, r5, r842; CHECK-NEXT: bl __aeabi_h2f43; CHECK-NEXT: mov r1, r444; CHECK-NEXT: bl __aeabi_fadd45; CHECK-NEXT: bl __aeabi_f2h46; CHECK-NEXT: pop {r4, r5, r6, r7, r8, lr}47; CHECK-NEXT: mov pc, lr48 %b = call reassoc half @llvm.vector.reduce.fadd.f16.v4f16(half -0.0, <4 x half> %a)49 ret half %b50}51 52define half @test_v4f16_seq(<4 x half> %a) nounwind {53; CHECK-LABEL: test_v4f16_seq:54; CHECK: @ %bb.0:55; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}56; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}57; CHECK-NEXT: mov r8, #25558; CHECK-NEXT: mov r4, r359; CHECK-NEXT: orr r8, r8, #6528060; CHECK-NEXT: mov r5, r261; CHECK-NEXT: and r0, r0, r862; CHECK-NEXT: mov r6, r163; CHECK-NEXT: bl __aeabi_h2f64; CHECK-NEXT: mov r7, r065; CHECK-NEXT: and r0, r6, r866; CHECK-NEXT: bl __aeabi_h2f67; CHECK-NEXT: mov r1, r068; CHECK-NEXT: mov r0, r769; CHECK-NEXT: bl __aeabi_fadd70; CHECK-NEXT: bl __aeabi_f2h71; CHECK-NEXT: mov r6, r072; CHECK-NEXT: and r0, r5, r873; CHECK-NEXT: bl __aeabi_h2f74; CHECK-NEXT: mov r5, r075; CHECK-NEXT: and r0, r6, r876; CHECK-NEXT: bl __aeabi_h2f77; CHECK-NEXT: mov r1, r578; CHECK-NEXT: bl __aeabi_fadd79; CHECK-NEXT: bl __aeabi_f2h80; CHECK-NEXT: mov r5, r081; CHECK-NEXT: and r0, r4, r882; CHECK-NEXT: bl __aeabi_h2f83; CHECK-NEXT: mov r4, r084; CHECK-NEXT: and r0, r5, r885; CHECK-NEXT: bl __aeabi_h2f86; CHECK-NEXT: mov r1, r487; CHECK-NEXT: bl __aeabi_fadd88; CHECK-NEXT: bl __aeabi_f2h89; CHECK-NEXT: pop {r4, r5, r6, r7, r8, lr}90; CHECK-NEXT: mov pc, lr91 %b = call half @llvm.vector.reduce.fadd.f16.v4f16(half -0.0, <4 x half> %a)92 ret half %b93}94 95define float @test_v4f32_reassoc(<4 x float> %a) nounwind {96; CHECK-LABEL: test_v4f32_reassoc:97; CHECK: @ %bb.0:98; CHECK-NEXT: .save {r4, r5, r11, lr}99; CHECK-NEXT: push {r4, r5, r11, lr}100; CHECK-NEXT: mov r4, r3101; CHECK-NEXT: mov r5, r2102; CHECK-NEXT: bl __aeabi_fadd103; CHECK-NEXT: mov r1, r5104; CHECK-NEXT: bl __aeabi_fadd105; CHECK-NEXT: mov r1, r4106; CHECK-NEXT: bl __aeabi_fadd107; CHECK-NEXT: pop {r4, r5, r11, lr}108; CHECK-NEXT: mov pc, lr109 %b = call reassoc float @llvm.vector.reduce.fadd.f32.v4f32(float -0.0, <4 x float> %a)110 ret float %b111}112 113define float @test_v4f32_seq(<4 x float> %a) nounwind {114; CHECK-LABEL: test_v4f32_seq:115; CHECK: @ %bb.0:116; CHECK-NEXT: .save {r4, r5, r11, lr}117; CHECK-NEXT: push {r4, r5, r11, lr}118; CHECK-NEXT: mov r4, r3119; CHECK-NEXT: mov r5, r2120; CHECK-NEXT: bl __aeabi_fadd121; CHECK-NEXT: mov r1, r5122; CHECK-NEXT: bl __aeabi_fadd123; CHECK-NEXT: mov r1, r4124; CHECK-NEXT: bl __aeabi_fadd125; CHECK-NEXT: pop {r4, r5, r11, lr}126; CHECK-NEXT: mov pc, lr127 %b = call float @llvm.vector.reduce.fadd.f32.v4f32(float -0.0, <4 x float> %a)128 ret float %b129}130 131define double @test_v2f64_reassoc(<2 x double> %a) nounwind {132; CHECK-LABEL: test_v2f64_reassoc:133; CHECK: @ %bb.0:134; CHECK-NEXT: .save {r11, lr}135; CHECK-NEXT: push {r11, lr}136; CHECK-NEXT: bl __aeabi_dadd137; CHECK-NEXT: pop {r11, lr}138; CHECK-NEXT: mov pc, lr139 %b = call reassoc double @llvm.vector.reduce.fadd.f64.v2f64(double -0.0, <2 x double> %a)140 ret double %b141}142 143define double @test_v2f64_seq(<2 x double> %a) nounwind {144; CHECK-LABEL: test_v2f64_seq:145; CHECK: @ %bb.0:146; CHECK-NEXT: .save {r11, lr}147; CHECK-NEXT: push {r11, lr}148; CHECK-NEXT: bl __aeabi_dadd149; CHECK-NEXT: pop {r11, lr}150; CHECK-NEXT: mov pc, lr151 %b = call double @llvm.vector.reduce.fadd.f64.v2f64(double -0.0, <2 x double> %a)152 ret double %b153}154 155define fp128 @test_v2f128_reassoc(<2 x fp128> %a) nounwind {156; CHECK-LABEL: test_v2f128_reassoc:157; CHECK: @ %bb.0:158; CHECK-NEXT: .save {r11, lr}159; CHECK-NEXT: push {r11, lr}160; CHECK-NEXT: .pad #16161; CHECK-NEXT: sub sp, sp, #16162; CHECK-NEXT: ldr r12, [sp, #36]163; CHECK-NEXT: str r12, [sp, #12]164; CHECK-NEXT: ldr r12, [sp, #32]165; CHECK-NEXT: str r12, [sp, #8]166; CHECK-NEXT: ldr r12, [sp, #28]167; CHECK-NEXT: str r12, [sp, #4]168; CHECK-NEXT: ldr r12, [sp, #24]169; CHECK-NEXT: str r12, [sp]170; CHECK-NEXT: bl __addtf3171; CHECK-NEXT: add sp, sp, #16172; CHECK-NEXT: pop {r11, lr}173; CHECK-NEXT: mov pc, lr174 %b = call reassoc fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 0xL00000000000000008000000000000000, <2 x fp128> %a)175 ret fp128 %b176}177 178define fp128 @test_v2f128_seq(<2 x fp128> %a) nounwind {179; CHECK-LABEL: test_v2f128_seq:180; CHECK: @ %bb.0:181; CHECK-NEXT: .save {r11, lr}182; CHECK-NEXT: push {r11, lr}183; CHECK-NEXT: .pad #16184; CHECK-NEXT: sub sp, sp, #16185; CHECK-NEXT: ldr r12, [sp, #36]186; CHECK-NEXT: str r12, [sp, #12]187; CHECK-NEXT: ldr r12, [sp, #32]188; CHECK-NEXT: str r12, [sp, #8]189; CHECK-NEXT: ldr r12, [sp, #28]190; CHECK-NEXT: str r12, [sp, #4]191; CHECK-NEXT: ldr r12, [sp, #24]192; CHECK-NEXT: str r12, [sp]193; CHECK-NEXT: bl __addtf3194; CHECK-NEXT: add sp, sp, #16195; CHECK-NEXT: pop {r11, lr}196; CHECK-NEXT: mov pc, lr197 %b = call fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 0xL00000000000000008000000000000000, <2 x fp128> %a)198 ret fp128 %b199}200