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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+neon | FileCheck %s --check-prefix=CHECK3 4declare half @llvm.vector.reduce.fadd.f16.v1f16(half, <1 x half>)5declare float @llvm.vector.reduce.fadd.f32.v1f32(float, <1 x float>)6declare double @llvm.vector.reduce.fadd.f64.v1f64(double, <1 x double>)7declare fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128, <1 x fp128>)8 9declare float @llvm.vector.reduce.fadd.f32.v3f32(float, <3 x float>)10declare float @llvm.vector.reduce.fadd.f32.v5f32(float, <5 x float>)11declare fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128, <2 x fp128>)12declare float @llvm.vector.reduce.fadd.f32.v16f32(float, <16 x float>)13 14define half @test_v1f16(<1 x half> %a, half %s) nounwind {15; CHECK-LABEL: test_v1f16:16; CHECK: @ %bb.0:17; CHECK-NEXT: .save {r4, r5, r11, lr}18; CHECK-NEXT: push {r4, r5, r11, lr}19; CHECK-NEXT: .vsave {d8}20; CHECK-NEXT: vpush {d8}21; CHECK-NEXT: mov r4, r022; CHECK-NEXT: mov r0, r123; CHECK-NEXT: bl __aeabi_h2f24; CHECK-NEXT: mov r5, r025; CHECK-NEXT: mov r0, r426; CHECK-NEXT: bl __aeabi_f2h27; CHECK-NEXT: vmov s16, r528; CHECK-NEXT: bl __aeabi_h2f29; CHECK-NEXT: vmov s0, r030; CHECK-NEXT: vadd.f32 s0, s16, s031; CHECK-NEXT: vmov r0, s032; CHECK-NEXT: bl __aeabi_f2h33; CHECK-NEXT: vpop {d8}34; CHECK-NEXT: pop {r4, r5, r11, lr}35; CHECK-NEXT: mov pc, lr36 %b = call half @llvm.vector.reduce.fadd.f16.v1f16(half %s, <1 x half> %a)37 ret half %b38}39 40define half @test_v1f16_neutral(<1 x half> %a) nounwind {41; CHECK-LABEL: test_v1f16_neutral:42; CHECK: @ %bb.0:43; CHECK-NEXT: .save {r11, lr}44; CHECK-NEXT: push {r11, lr}45; CHECK-NEXT: bl __aeabi_f2h46; CHECK-NEXT: pop {r11, lr}47; CHECK-NEXT: mov pc, lr48 %b = call half @llvm.vector.reduce.fadd.f16.v1f16(half -0.0, <1 x half> %a)49 ret half %b50}51 52define float @test_v1f32(<1 x float> %a, float %s) nounwind {53; CHECK-LABEL: test_v1f32:54; CHECK: @ %bb.0:55; CHECK-NEXT: vmov s0, r056; CHECK-NEXT: vmov s2, r157; CHECK-NEXT: vadd.f32 s0, s2, s058; CHECK-NEXT: vmov r0, s059; CHECK-NEXT: mov pc, lr60 %b = call float @llvm.vector.reduce.fadd.f32.v1f32(float %s, <1 x float> %a)61 ret float %b62}63 64define float @test_v1f32_neutral(<1 x float> %a) nounwind {65; CHECK-LABEL: test_v1f32_neutral:66; CHECK: @ %bb.0:67; CHECK-NEXT: mov pc, lr68 %b = call float @llvm.vector.reduce.fadd.f32.v1f32(float -0.0, <1 x float> %a)69 ret float %b70}71 72define double @test_v1f64(<1 x double> %a, double %s) nounwind {73; CHECK-LABEL: test_v1f64:74; CHECK: @ %bb.0:75; CHECK-NEXT: vmov d16, r0, r176; CHECK-NEXT: vmov d17, r2, r377; CHECK-NEXT: vadd.f64 d16, d17, d1678; CHECK-NEXT: vmov r0, r1, d1679; CHECK-NEXT: mov pc, lr80 %b = call double @llvm.vector.reduce.fadd.f64.v1f64(double %s, <1 x double> %a)81 ret double %b82}83 84define double @test_v1f64_neutral(<1 x double> %a) nounwind {85; CHECK-LABEL: test_v1f64_neutral:86; CHECK: @ %bb.0:87; CHECK-NEXT: mov pc, lr88 %b = call double @llvm.vector.reduce.fadd.f64.v1f64(double -0.0, <1 x double> %a)89 ret double %b90}91 92define fp128 @test_v1f128(<1 x fp128> %a, fp128 %s) nounwind {93; CHECK-LABEL: test_v1f128:94; CHECK: @ %bb.0:95; CHECK-NEXT: .save {r4, r5, r11, lr}96; CHECK-NEXT: push {r4, r5, r11, lr}97; CHECK-NEXT: .pad #1698; CHECK-NEXT: sub sp, sp, #1699; CHECK-NEXT: ldr r12, [sp, #32]100; CHECK-NEXT: ldr lr, [sp, #36]101; CHECK-NEXT: ldr r4, [sp, #40]102; CHECK-NEXT: ldr r5, [sp, #44]103; CHECK-NEXT: stm sp, {r0, r1, r2, r3}104; CHECK-NEXT: mov r0, r12105; CHECK-NEXT: mov r1, lr106; CHECK-NEXT: mov r2, r4107; CHECK-NEXT: mov r3, r5108; CHECK-NEXT: bl __addtf3109; CHECK-NEXT: add sp, sp, #16110; CHECK-NEXT: pop {r4, r5, r11, lr}111; CHECK-NEXT: mov pc, lr112 %b = call fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128 %s, <1 x fp128> %a)113 ret fp128 %b114}115 116define fp128 @test_v1f128_neutral(<1 x fp128> %a) nounwind {117; CHECK-LABEL: test_v1f128_neutral:118; CHECK: @ %bb.0:119; CHECK-NEXT: mov pc, lr120 %b = call fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128 0xL00000000000000008000000000000000, <1 x fp128> %a)121 ret fp128 %b122}123 124define float @test_v3f32(<3 x float> %a, float %s) nounwind {125; CHECK-LABEL: test_v3f32:126; CHECK: @ %bb.0:127; CHECK-NEXT: vmov d3, r2, r3128; CHECK-NEXT: vldr s0, [sp]129; CHECK-NEXT: vmov d2, r0, r1130; CHECK-NEXT: vadd.f32 s0, s0, s4131; CHECK-NEXT: vadd.f32 s0, s0, s5132; CHECK-NEXT: vadd.f32 s0, s0, s6133; CHECK-NEXT: vmov r0, s0134; CHECK-NEXT: mov pc, lr135 %b = call float @llvm.vector.reduce.fadd.f32.v3f32(float %s, <3 x float> %a)136 ret float %b137}138 139define float @test_v3f32_neutral(<3 x float> %a) nounwind {140; CHECK-LABEL: test_v3f32_neutral:141; CHECK: @ %bb.0:142; CHECK-NEXT: vmov d1, r2, r3143; CHECK-NEXT: vmov d0, r0, r1144; CHECK-NEXT: vadd.f32 s4, s0, s1145; CHECK-NEXT: vadd.f32 s0, s4, s2146; CHECK-NEXT: vmov r0, s0147; CHECK-NEXT: mov pc, lr148 %b = call float @llvm.vector.reduce.fadd.f32.v3f32(float -0.0, <3 x float> %a)149 ret float %b150}151 152define float @test_v5f32(<5 x float> %a, float %s) nounwind {153; CHECK-LABEL: test_v5f32:154; CHECK: @ %bb.0:155; CHECK-NEXT: vldr s0, [sp, #4]156; CHECK-NEXT: vmov s2, r0157; CHECK-NEXT: vadd.f32 s0, s0, s2158; CHECK-NEXT: vmov s2, r1159; CHECK-NEXT: vadd.f32 s0, s0, s2160; CHECK-NEXT: vmov s2, r2161; CHECK-NEXT: vadd.f32 s0, s0, s2162; CHECK-NEXT: vmov s2, r3163; CHECK-NEXT: vadd.f32 s0, s0, s2164; CHECK-NEXT: vldr s2, [sp]165; CHECK-NEXT: vadd.f32 s0, s0, s2166; CHECK-NEXT: vmov r0, s0167; CHECK-NEXT: mov pc, lr168 %b = call float @llvm.vector.reduce.fadd.f32.v5f32(float %s, <5 x float> %a)169 ret float %b170}171 172define float @test_v5f32_neutral(<5 x float> %a) nounwind {173; CHECK-LABEL: test_v5f32_neutral:174; CHECK: @ %bb.0:175; CHECK-NEXT: vmov s0, r1176; CHECK-NEXT: vmov s2, r0177; CHECK-NEXT: vadd.f32 s0, s2, s0178; CHECK-NEXT: vmov s2, r2179; CHECK-NEXT: vadd.f32 s0, s0, s2180; CHECK-NEXT: vmov s2, r3181; CHECK-NEXT: vadd.f32 s0, s0, s2182; CHECK-NEXT: vldr s2, [sp]183; CHECK-NEXT: vadd.f32 s0, s0, s2184; CHECK-NEXT: vmov r0, s0185; CHECK-NEXT: mov pc, lr186 %b = call float @llvm.vector.reduce.fadd.f32.v5f32(float -0.0, <5 x float> %a)187 ret float %b188}189 190define fp128 @test_v2f128(<2 x fp128> %a, fp128 %s) nounwind {191; CHECK-LABEL: test_v2f128:192; CHECK: @ %bb.0:193; CHECK-NEXT: .save {r4, r5, r11, lr}194; CHECK-NEXT: push {r4, r5, r11, lr}195; CHECK-NEXT: .pad #16196; CHECK-NEXT: sub sp, sp, #16197; CHECK-NEXT: ldr r12, [sp, #48]198; CHECK-NEXT: ldr lr, [sp, #52]199; CHECK-NEXT: ldr r4, [sp, #56]200; CHECK-NEXT: ldr r5, [sp, #60]201; CHECK-NEXT: stm sp, {r0, r1, r2, r3}202; CHECK-NEXT: mov r0, r12203; CHECK-NEXT: mov r1, lr204; CHECK-NEXT: mov r2, r4205; CHECK-NEXT: mov r3, r5206; CHECK-NEXT: bl __addtf3207; CHECK-NEXT: ldr r4, [sp, #32]208; CHECK-NEXT: ldr r5, [sp, #40]209; CHECK-NEXT: ldr lr, [sp, #44]210; CHECK-NEXT: ldr r12, [sp, #36]211; CHECK-NEXT: stm sp, {r4, r12}212; CHECK-NEXT: str r5, [sp, #8]213; CHECK-NEXT: str lr, [sp, #12]214; CHECK-NEXT: bl __addtf3215; CHECK-NEXT: add sp, sp, #16216; CHECK-NEXT: pop {r4, r5, r11, lr}217; CHECK-NEXT: mov pc, lr218 %b = call fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 %s, <2 x fp128> %a)219 ret fp128 %b220}221 222define fp128 @test_v2f128_neutral(<2 x fp128> %a) nounwind {223; CHECK-LABEL: test_v2f128_neutral:224; CHECK: @ %bb.0:225; CHECK-NEXT: .save {r4, r5, r11, lr}226; CHECK-NEXT: push {r4, r5, r11, lr}227; CHECK-NEXT: .pad #16228; CHECK-NEXT: sub sp, sp, #16229; CHECK-NEXT: ldr r12, [sp, #36]230; CHECK-NEXT: ldr lr, [sp, #32]231; CHECK-NEXT: ldr r4, [sp, #40]232; CHECK-NEXT: ldr r5, [sp, #44]233; CHECK-NEXT: str lr, [sp]234; CHECK-NEXT: str r12, [sp, #4]235; CHECK-NEXT: str r4, [sp, #8]236; CHECK-NEXT: str r5, [sp, #12]237; CHECK-NEXT: bl __addtf3238; CHECK-NEXT: add sp, sp, #16239; CHECK-NEXT: pop {r4, r5, r11, lr}240; CHECK-NEXT: mov pc, lr241 %b = call fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 0xL00000000000000008000000000000000, <2 x fp128> %a)242 ret fp128 %b243}244 245define float @test_v16f32(<16 x float> %a, float %s) nounwind {246; CHECK-LABEL: test_v16f32:247; CHECK: @ %bb.0:248; CHECK-NEXT: vmov d3, r2, r3249; CHECK-NEXT: vldr s0, [sp, #48]250; CHECK-NEXT: vmov d2, r0, r1251; CHECK-NEXT: mov r0, sp252; CHECK-NEXT: vadd.f32 s0, s0, s4253; CHECK-NEXT: vadd.f32 s0, s0, s5254; CHECK-NEXT: vadd.f32 s0, s0, s6255; CHECK-NEXT: vadd.f32 s0, s0, s7256; CHECK-NEXT: vld1.64 {d2, d3}, [r0]257; CHECK-NEXT: add r0, sp, #16258; CHECK-NEXT: vadd.f32 s0, s0, s4259; CHECK-NEXT: vadd.f32 s0, s0, s5260; CHECK-NEXT: vadd.f32 s0, s0, s6261; CHECK-NEXT: vadd.f32 s0, s0, s7262; CHECK-NEXT: vld1.64 {d2, d3}, [r0]263; CHECK-NEXT: add r0, sp, #32264; CHECK-NEXT: vadd.f32 s0, s0, s4265; CHECK-NEXT: vadd.f32 s0, s0, s5266; CHECK-NEXT: vadd.f32 s0, s0, s6267; CHECK-NEXT: vadd.f32 s0, s0, s7268; CHECK-NEXT: vld1.64 {d2, d3}, [r0]269; CHECK-NEXT: vadd.f32 s0, s0, s4270; CHECK-NEXT: vadd.f32 s0, s0, s5271; CHECK-NEXT: vadd.f32 s0, s0, s6272; CHECK-NEXT: vadd.f32 s0, s0, s7273; CHECK-NEXT: vmov r0, s0274; CHECK-NEXT: mov pc, lr275 %b = call float @llvm.vector.reduce.fadd.f32.v16f32(float %s, <16 x float> %a)276 ret float %b277}278 279define float @test_v16f32_neutral(<16 x float> %a) nounwind {280; CHECK-LABEL: test_v16f32_neutral:281; CHECK: @ %bb.0:282; CHECK-NEXT: vmov d1, r2, r3283; CHECK-NEXT: vmov d0, r0, r1284; CHECK-NEXT: mov r0, sp285; CHECK-NEXT: vadd.f32 s4, s0, s1286; CHECK-NEXT: vadd.f32 s4, s4, s2287; CHECK-NEXT: vadd.f32 s0, s4, s3288; CHECK-NEXT: vld1.64 {d2, d3}, [r0]289; CHECK-NEXT: add r0, sp, #16290; CHECK-NEXT: vadd.f32 s0, s0, s4291; CHECK-NEXT: vadd.f32 s0, s0, s5292; CHECK-NEXT: vadd.f32 s0, s0, s6293; CHECK-NEXT: vadd.f32 s0, s0, s7294; CHECK-NEXT: vld1.64 {d2, d3}, [r0]295; CHECK-NEXT: add r0, sp, #32296; CHECK-NEXT: vadd.f32 s0, s0, s4297; CHECK-NEXT: vadd.f32 s0, s0, s5298; CHECK-NEXT: vadd.f32 s0, s0, s6299; CHECK-NEXT: vadd.f32 s0, s0, s7300; CHECK-NEXT: vld1.64 {d2, d3}, [r0]301; CHECK-NEXT: vadd.f32 s0, s0, s4302; CHECK-NEXT: vadd.f32 s0, s0, s5303; CHECK-NEXT: vadd.f32 s0, s0, s6304; CHECK-NEXT: vadd.f32 s0, s0, s7305; CHECK-NEXT: vmov r0, s0306; CHECK-NEXT: mov pc, lr307 %b = call float @llvm.vector.reduce.fadd.f32.v16f32(float -0.0, <16 x float> %a)308 ret float %b309}310