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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm-none-eabi -mattr=-neon | FileCheck %s --check-prefix=CHECK3 4declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>)5declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)6declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)7declare fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128>)8 9define half @test_v4f16(<4 x half> %a) nounwind {10; CHECK-LABEL: test_v4f16:11; CHECK: @ %bb.0:12; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}13; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}14; CHECK-NEXT: mov r4, #25515; CHECK-NEXT: mov r8, r316; CHECK-NEXT: orr r4, r4, #6528017; CHECK-NEXT: mov r5, r218; CHECK-NEXT: and r0, r0, r419; CHECK-NEXT: mov r6, r120; CHECK-NEXT: bl __aeabi_h2f21; CHECK-NEXT: mov r7, r022; CHECK-NEXT: and r0, r6, r423; CHECK-NEXT: bl __aeabi_h2f24; CHECK-NEXT: mov r6, r025; CHECK-NEXT: mov r0, r726; CHECK-NEXT: mov r1, r627; CHECK-NEXT: bl __aeabi_fcmplt28; CHECK-NEXT: cmp r0, #029; CHECK-NEXT: movne r6, r730; CHECK-NEXT: mov r0, r631; CHECK-NEXT: bl __aeabi_f2h32; CHECK-NEXT: mov r6, r033; CHECK-NEXT: and r0, r5, r434; CHECK-NEXT: bl __aeabi_h2f35; CHECK-NEXT: mov r5, r036; CHECK-NEXT: and r0, r6, r437; CHECK-NEXT: bl __aeabi_h2f38; CHECK-NEXT: mov r1, r539; CHECK-NEXT: mov r6, r040; CHECK-NEXT: bl __aeabi_fcmplt41; CHECK-NEXT: cmp r0, #042; CHECK-NEXT: movne r5, r643; CHECK-NEXT: mov r0, r544; CHECK-NEXT: bl __aeabi_f2h45; CHECK-NEXT: and r0, r0, r446; CHECK-NEXT: bl __aeabi_h2f47; CHECK-NEXT: mov r5, r048; CHECK-NEXT: and r0, r8, r449; CHECK-NEXT: bl __aeabi_h2f50; CHECK-NEXT: mov r4, r051; CHECK-NEXT: mov r0, r552; CHECK-NEXT: mov r1, r453; CHECK-NEXT: bl __aeabi_fcmplt54; CHECK-NEXT: cmp r0, #055; CHECK-NEXT: movne r4, r556; CHECK-NEXT: mov r0, r457; CHECK-NEXT: bl __aeabi_f2h58; CHECK-NEXT: pop {r4, r5, r6, r7, r8, lr}59; CHECK-NEXT: mov pc, lr60 %b = call fast half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)61 ret half %b62}63 64define float @test_v4f32(<4 x float> %a) nounwind {65; CHECK-LABEL: test_v4f32:66; CHECK: @ %bb.0:67; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}68; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}69; CHECK-NEXT: mov r4, r370; CHECK-NEXT: mov r6, r271; CHECK-NEXT: mov r5, r172; CHECK-NEXT: mov r7, r073; CHECK-NEXT: bl __aeabi_fcmplt74; CHECK-NEXT: cmp r0, #075; CHECK-NEXT: mov r1, r676; CHECK-NEXT: movne r5, r777; CHECK-NEXT: mov r0, r578; CHECK-NEXT: bl __aeabi_fcmplt79; CHECK-NEXT: cmp r0, #080; CHECK-NEXT: mov r1, r481; CHECK-NEXT: moveq r5, r682; CHECK-NEXT: mov r0, r583; CHECK-NEXT: bl __aeabi_fcmplt84; CHECK-NEXT: cmp r0, #085; CHECK-NEXT: moveq r5, r486; CHECK-NEXT: mov r0, r587; CHECK-NEXT: pop {r4, r5, r6, r7, r11, lr}88; CHECK-NEXT: mov pc, lr89 %b = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)90 ret float %b91}92 93define double @test_v2f64(<2 x double> %a) nounwind {94; CHECK-LABEL: test_v2f64:95; CHECK: @ %bb.0:96; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}97; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}98; CHECK-NEXT: mov r4, r399; CHECK-NEXT: mov r6, r2100; CHECK-NEXT: mov r8, r1101; CHECK-NEXT: mov r7, r0102; CHECK-NEXT: bl __aeabi_dcmplt103; CHECK-NEXT: cmp r0, #0104; CHECK-NEXT: mov r5, r6105; CHECK-NEXT: mov r0, r7106; CHECK-NEXT: mov r1, r8107; CHECK-NEXT: mov r2, r6108; CHECK-NEXT: mov r3, r4109; CHECK-NEXT: movne r5, r7110; CHECK-NEXT: bl __aeabi_dcmplt111; CHECK-NEXT: cmp r0, #0112; CHECK-NEXT: mov r0, r5113; CHECK-NEXT: movne r4, r8114; CHECK-NEXT: mov r1, r4115; CHECK-NEXT: pop {r4, r5, r6, r7, r8, lr}116; CHECK-NEXT: mov pc, lr117 %b = call fast double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)118 ret double %b119}120 121define fp128 @test_v2f128(<2 x fp128> %a) nounwind {122; CHECK-LABEL: test_v2f128:123; CHECK: @ %bb.0:124; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}125; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}126; CHECK-NEXT: .pad #28127; CHECK-NEXT: sub sp, sp, #28128; CHECK-NEXT: ldr r5, [sp, #76]129; CHECK-NEXT: mov r8, r3130; CHECK-NEXT: ldr r6, [sp, #72]131; CHECK-NEXT: mov r9, r2132; CHECK-NEXT: ldr r4, [sp, #68]133; CHECK-NEXT: mov r10, r1134; CHECK-NEXT: ldr r7, [sp, #64]135; CHECK-NEXT: mov r11, r0136; CHECK-NEXT: str r5, [sp, #12]137; CHECK-NEXT: str r6, [sp, #8]138; CHECK-NEXT: str r4, [sp, #4]139; CHECK-NEXT: str r7, [sp]140; CHECK-NEXT: bl __lttf2141; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill142; CHECK-NEXT: mov r0, r11143; CHECK-NEXT: mov r1, r10144; CHECK-NEXT: mov r2, r9145; CHECK-NEXT: mov r3, r8146; CHECK-NEXT: str r7, [sp]147; CHECK-NEXT: stmib sp, {r4, r6}148; CHECK-NEXT: str r5, [sp, #12]149; CHECK-NEXT: bl __lttf2150; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill151; CHECK-NEXT: mov r0, r11152; CHECK-NEXT: mov r1, r10153; CHECK-NEXT: mov r2, r9154; CHECK-NEXT: mov r3, r8155; CHECK-NEXT: str r7, [sp]156; CHECK-NEXT: stmib sp, {r4, r6}157; CHECK-NEXT: str r5, [sp, #12]158; CHECK-NEXT: bl __lttf2159; CHECK-NEXT: cmp r0, #0160; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload161; CHECK-NEXT: str r7, [sp]162; CHECK-NEXT: movmi r7, r11163; CHECK-NEXT: cmp r0, #0164; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload165; CHECK-NEXT: stmib sp, {r4, r6}166; CHECK-NEXT: movmi r4, r10167; CHECK-NEXT: cmp r0, #0168; CHECK-NEXT: mov r0, r11169; CHECK-NEXT: mov r1, r10170; CHECK-NEXT: mov r2, r9171; CHECK-NEXT: mov r3, r8172; CHECK-NEXT: str r5, [sp, #12]173; CHECK-NEXT: movmi r6, r9174; CHECK-NEXT: bl __lttf2175; CHECK-NEXT: cmp r0, #0176; CHECK-NEXT: mov r0, r7177; CHECK-NEXT: movmi r5, r8178; CHECK-NEXT: mov r1, r4179; CHECK-NEXT: mov r2, r6180; CHECK-NEXT: mov r3, r5181; CHECK-NEXT: add sp, sp, #28182; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, lr}183; CHECK-NEXT: mov pc, lr184 %b = call fast fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)185 ret fp128 %b186}187