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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+neon | FileCheck %s --check-prefix=CHECK3 4declare half @llvm.vector.reduce.fmul.f16.v1f16(half, <1 x half>)5declare float @llvm.vector.reduce.fmul.f32.v1f32(float, <1 x float>)6declare double @llvm.vector.reduce.fmul.f64.v1f64(double, <1 x double>)7declare fp128 @llvm.vector.reduce.fmul.f128.v1f128(fp128, <1 x fp128>)8 9declare float @llvm.vector.reduce.fmul.f32.v3f32(float, <3 x float>)10declare fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128, <2 x fp128>)11declare float @llvm.vector.reduce.fmul.f32.v16f32(float, <16 x float>)12 13define half @test_v1f16(<1 x half> %a) nounwind {14; CHECK-LABEL: test_v1f16:15; CHECK: @ %bb.0:16; CHECK-NEXT: .save {r11, lr}17; CHECK-NEXT: push {r11, lr}18; CHECK-NEXT: bl __aeabi_f2h19; CHECK-NEXT: pop {r11, lr}20; CHECK-NEXT: mov pc, lr21 %b = call half @llvm.vector.reduce.fmul.f16.v1f16(half 1.0, <1 x half> %a)22 ret half %b23}24 25define float @test_v1f32(<1 x float> %a) nounwind {26; CHECK-LABEL: test_v1f32:27; CHECK: @ %bb.0:28; CHECK-NEXT: mov pc, lr29 %b = call float @llvm.vector.reduce.fmul.f32.v1f32(float 1.0, <1 x float> %a)30 ret float %b31}32 33define double @test_v1f64(<1 x double> %a) nounwind {34; CHECK-LABEL: test_v1f64:35; CHECK: @ %bb.0:36; CHECK-NEXT: mov pc, lr37 %b = call double @llvm.vector.reduce.fmul.f64.v1f64(double 1.0, <1 x double> %a)38 ret double %b39}40 41define fp128 @test_v1f128(<1 x fp128> %a) nounwind {42; CHECK-LABEL: test_v1f128:43; CHECK: @ %bb.0:44; CHECK-NEXT: mov pc, lr45 %b = call fp128 @llvm.vector.reduce.fmul.f128.v1f128(fp128 0xL00000000000000003fff00000000000000, <1 x fp128> %a)46 ret fp128 %b47}48 49define float @test_v3f32(<3 x float> %a) nounwind {50; CHECK-LABEL: test_v3f32:51; CHECK: @ %bb.0:52; CHECK-NEXT: vmov d1, r2, r353; CHECK-NEXT: vmov d0, r0, r154; CHECK-NEXT: vmul.f32 s4, s0, s155; CHECK-NEXT: vmul.f32 s0, s4, s256; CHECK-NEXT: vmov r0, s057; CHECK-NEXT: mov pc, lr58 %b = call float @llvm.vector.reduce.fmul.f32.v3f32(float 1.0, <3 x float> %a)59 ret float %b60}61 62define fp128 @test_v2f128(<2 x fp128> %a) nounwind {63; CHECK-LABEL: test_v2f128:64; CHECK: @ %bb.0:65; CHECK-NEXT: .save {r4, r5, r11, lr}66; CHECK-NEXT: push {r4, r5, r11, lr}67; CHECK-NEXT: .pad #1668; CHECK-NEXT: sub sp, sp, #1669; CHECK-NEXT: ldr r12, [sp, #36]70; CHECK-NEXT: ldr lr, [sp, #32]71; CHECK-NEXT: ldr r4, [sp, #40]72; CHECK-NEXT: ldr r5, [sp, #44]73; CHECK-NEXT: str lr, [sp]74; CHECK-NEXT: str r12, [sp, #4]75; CHECK-NEXT: str r4, [sp, #8]76; CHECK-NEXT: str r5, [sp, #12]77; CHECK-NEXT: bl __multf378; CHECK-NEXT: add sp, sp, #1679; CHECK-NEXT: pop {r4, r5, r11, lr}80; CHECK-NEXT: mov pc, lr81 %b = call fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128 0xL00000000000000003fff00000000000000, <2 x fp128> %a)82 ret fp128 %b83}84 85define float @test_v16f32(<16 x float> %a) nounwind {86; CHECK-LABEL: test_v16f32:87; CHECK: @ %bb.0:88; CHECK-NEXT: vmov d1, r2, r389; CHECK-NEXT: vmov d0, r0, r190; CHECK-NEXT: mov r0, sp91; CHECK-NEXT: vmul.f32 s4, s0, s192; CHECK-NEXT: vmul.f32 s4, s4, s293; CHECK-NEXT: vmul.f32 s0, s4, s394; CHECK-NEXT: vld1.64 {d2, d3}, [r0]95; CHECK-NEXT: add r0, sp, #1696; CHECK-NEXT: vmul.f32 s0, s0, s497; CHECK-NEXT: vmul.f32 s0, s0, s598; CHECK-NEXT: vmul.f32 s0, s0, s699; CHECK-NEXT: vmul.f32 s0, s0, s7100; CHECK-NEXT: vld1.64 {d2, d3}, [r0]101; CHECK-NEXT: add r0, sp, #32102; CHECK-NEXT: vmul.f32 s0, s0, s4103; CHECK-NEXT: vmul.f32 s0, s0, s5104; CHECK-NEXT: vmul.f32 s0, s0, s6105; CHECK-NEXT: vmul.f32 s0, s0, s7106; CHECK-NEXT: vld1.64 {d2, d3}, [r0]107; CHECK-NEXT: vmul.f32 s0, s0, s4108; CHECK-NEXT: vmul.f32 s0, s0, s5109; CHECK-NEXT: vmul.f32 s0, s0, s6110; CHECK-NEXT: vmul.f32 s0, s0, s7111; CHECK-NEXT: vmov r0, s0112; CHECK-NEXT: mov pc, lr113 %b = call float @llvm.vector.reduce.fmul.f32.v16f32(float 1.0, <16 x float> %a)114 ret float %b115}116