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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=armv7-none-eabi -float-abi=hard -mattr=+neon -verify-machineinstrs | FileCheck %s3 4define i8 @test_umin_v8i8(<8 x i8> %x) {5; CHECK-LABEL: test_umin_v8i8:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vpmin.u8 d16, d0, d08; CHECK-NEXT: vpmin.u8 d16, d16, d169; CHECK-NEXT: vpmin.u8 d16, d16, d1610; CHECK-NEXT: vmov.u8 r0, d16[0]11; CHECK-NEXT: bx lr12entry:13 %z = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> %x)14 ret i8 %z15}16 17define i8 @test_smin_v8i8(<8 x i8> %x) {18; CHECK-LABEL: test_smin_v8i8:19; CHECK: @ %bb.0: @ %entry20; CHECK-NEXT: vpmin.s8 d16, d0, d021; CHECK-NEXT: vpmin.s8 d16, d16, d1622; CHECK-NEXT: vpmin.s8 d16, d16, d1623; CHECK-NEXT: vmov.s8 r0, d16[0]24; CHECK-NEXT: bx lr25entry:26 %z = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> %x)27 ret i8 %z28}29 30define i8 @test_umax_v8i8(<8 x i8> %x) {31; CHECK-LABEL: test_umax_v8i8:32; CHECK: @ %bb.0: @ %entry33; CHECK-NEXT: vpmax.u8 d16, d0, d034; CHECK-NEXT: vpmax.u8 d16, d16, d1635; CHECK-NEXT: vpmax.u8 d16, d16, d1636; CHECK-NEXT: vmov.u8 r0, d16[0]37; CHECK-NEXT: bx lr38entry:39 %z = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> %x)40 ret i8 %z41}42 43define i8 @test_smax_v8i8(<8 x i8> %x) {44; CHECK-LABEL: test_smax_v8i8:45; CHECK: @ %bb.0: @ %entry46; CHECK-NEXT: vpmax.s8 d16, d0, d047; CHECK-NEXT: vpmax.s8 d16, d16, d1648; CHECK-NEXT: vpmax.s8 d16, d16, d1649; CHECK-NEXT: vmov.s8 r0, d16[0]50; CHECK-NEXT: bx lr51entry:52 %z = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> %x)53 ret i8 %z54}55 56define i16 @test_umin_v4i16(<4 x i16> %x) {57; CHECK-LABEL: test_umin_v4i16:58; CHECK: @ %bb.0: @ %entry59; CHECK-NEXT: vpmin.u16 d16, d0, d060; CHECK-NEXT: vpmin.u16 d16, d16, d1661; CHECK-NEXT: vmov.u16 r0, d16[0]62; CHECK-NEXT: bx lr63entry:64 %z = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> %x)65 ret i16 %z66}67 68define i16 @test_smin_v4i16(<4 x i16> %x) {69; CHECK-LABEL: test_smin_v4i16:70; CHECK: @ %bb.0: @ %entry71; CHECK-NEXT: vpmin.s16 d16, d0, d072; CHECK-NEXT: vpmin.s16 d16, d16, d1673; CHECK-NEXT: vmov.s16 r0, d16[0]74; CHECK-NEXT: bx lr75entry:76 %z = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %x)77 ret i16 %z78}79 80define i16 @test_umax_v4i16(<4 x i16> %x) {81; CHECK-LABEL: test_umax_v4i16:82; CHECK: @ %bb.0: @ %entry83; CHECK-NEXT: vpmax.u16 d16, d0, d084; CHECK-NEXT: vpmax.u16 d16, d16, d1685; CHECK-NEXT: vmov.u16 r0, d16[0]86; CHECK-NEXT: bx lr87entry:88 %z = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %x)89 ret i16 %z90}91 92define i16 @test_smax_v4i16(<4 x i16> %x) {93; CHECK-LABEL: test_smax_v4i16:94; CHECK: @ %bb.0: @ %entry95; CHECK-NEXT: vpmax.s16 d16, d0, d096; CHECK-NEXT: vpmax.s16 d16, d16, d1697; CHECK-NEXT: vmov.s16 r0, d16[0]98; CHECK-NEXT: bx lr99entry:100 %z = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %x)101 ret i16 %z102}103 104define i32 @test_umin_v2i32(<2 x i32> %x) {105; CHECK-LABEL: test_umin_v2i32:106; CHECK: @ %bb.0: @ %entry107; CHECK-NEXT: vpmin.u32 d16, d0, d0108; CHECK-NEXT: vmov.32 r0, d16[0]109; CHECK-NEXT: bx lr110entry:111 %z = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> %x)112 ret i32 %z113}114 115define i32 @test_smin_v2i32(<2 x i32> %x) {116; CHECK-LABEL: test_smin_v2i32:117; CHECK: @ %bb.0: @ %entry118; CHECK-NEXT: vpmin.s32 d16, d0, d0119; CHECK-NEXT: vmov.32 r0, d16[0]120; CHECK-NEXT: bx lr121entry:122 %z = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> %x)123 ret i32 %z124}125 126define i32 @test_umax_v2i32(<2 x i32> %x) {127; CHECK-LABEL: test_umax_v2i32:128; CHECK: @ %bb.0: @ %entry129; CHECK-NEXT: vpmax.u32 d16, d0, d0130; CHECK-NEXT: vmov.32 r0, d16[0]131; CHECK-NEXT: bx lr132entry:133 %z = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %x)134 ret i32 %z135}136 137define i32 @test_smax_v2i32(<2 x i32> %x) {138; CHECK-LABEL: test_smax_v2i32:139; CHECK: @ %bb.0: @ %entry140; CHECK-NEXT: vpmax.s32 d16, d0, d0141; CHECK-NEXT: vmov.32 r0, d16[0]142; CHECK-NEXT: bx lr143entry:144 %z = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> %x)145 ret i32 %z146}147 148define i8 @test_umin_v16i8(<16 x i8> %x) {149; CHECK-LABEL: test_umin_v16i8:150; CHECK: @ %bb.0: @ %entry151; CHECK-NEXT: vpmin.u8 d16, d0, d1152; CHECK-NEXT: vpmin.u8 d16, d16, d16153; CHECK-NEXT: vpmin.u8 d16, d16, d16154; CHECK-NEXT: vpmin.u8 d16, d16, d16155; CHECK-NEXT: vmov.u8 r0, d16[0]156; CHECK-NEXT: bx lr157entry:158 %z = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %x)159 ret i8 %z160}161 162define i16 @test_smin_v8i16(<8 x i16> %x) {163; CHECK-LABEL: test_smin_v8i16:164; CHECK: @ %bb.0: @ %entry165; CHECK-NEXT: vpmin.s16 d16, d0, d1166; CHECK-NEXT: vpmin.s16 d16, d16, d16167; CHECK-NEXT: vpmin.s16 d16, d16, d16168; CHECK-NEXT: vmov.s16 r0, d16[0]169; CHECK-NEXT: bx lr170entry:171 %z = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %x)172 ret i16 %z173}174 175define i32 @test_umax_v4i32(<4 x i32> %x) {176; CHECK-LABEL: test_umax_v4i32:177; CHECK: @ %bb.0: @ %entry178; CHECK-NEXT: vpmax.u32 d16, d0, d1179; CHECK-NEXT: vpmax.u32 d16, d16, d16180; CHECK-NEXT: vmov.32 r0, d16[0]181; CHECK-NEXT: bx lr182entry:183 %z = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %x)184 ret i32 %z185}186 187define i8 @test_umin_v32i8(<32 x i8> %x) {188; CHECK-LABEL: test_umin_v32i8:189; CHECK: @ %bb.0: @ %entry190; CHECK-NEXT: vmin.u8 q8, q0, q1191; CHECK-NEXT: vpmin.u8 d16, d16, d17192; CHECK-NEXT: vpmin.u8 d16, d16, d16193; CHECK-NEXT: vpmin.u8 d16, d16, d16194; CHECK-NEXT: vpmin.u8 d16, d16, d16195; CHECK-NEXT: vmov.u8 r0, d16[0]196; CHECK-NEXT: bx lr197entry:198 %z = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> %x)199 ret i8 %z200}201 202declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>)203declare i8 @llvm.vector.reduce.smin.v8i8(<8 x i8>)204declare i8 @llvm.vector.reduce.umax.v8i8(<8 x i8>)205declare i8 @llvm.vector.reduce.smax.v8i8(<8 x i8>)206declare i16 @llvm.vector.reduce.umin.v4i16(<4 x i16>)207declare i16 @llvm.vector.reduce.smin.v4i16(<4 x i16>)208declare i16 @llvm.vector.reduce.umax.v4i16(<4 x i16>)209declare i16 @llvm.vector.reduce.smax.v4i16(<4 x i16>)210declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>)211declare i32 @llvm.vector.reduce.smin.v2i32(<2 x i32>)212declare i32 @llvm.vector.reduce.umax.v2i32(<2 x i32>)213declare i32 @llvm.vector.reduce.smax.v2i32(<2 x i32>)214 215declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)216declare i16 @llvm.vector.reduce.smin.v8i16(<8 x i16>)217declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)218 219declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>)220