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1; RUN: llc -mtriple armv7 %s -o - | FileCheck %s2 3; CHECK-LABEL: f:4define float @f(ptr nocapture %in) {5 ; CHECK: vld16 ; CHECK: vmovl.u167 %1 = load <4 x i16>, ptr %in8 ; CHECK: vcvt.f32.u329 %2 = uitofp <4 x i16> %1 to <4 x float>10 %3 = extractelement <4 x float> %2, i32 011 %4 = extractelement <4 x float> %2, i32 112 %5 = extractelement <4 x float> %2, i32 213 14 ; CHECK: vadd.f3215 %6 = fadd float %3, %416 %7 = fadd float %6, %517 18 ret float %719}20 21; CHECK-LABEL: g:22define float @g(ptr nocapture %in) {23; Note: vld1 here is reasonably important. Mixing VFP and NEON24; instructions is bad on some cores25 ; CHECK: vld126 ; CHECK: vmovl.u827 ; CHECK: vmovl.u1628 %1 = load <4 x i8>, ptr %in29 ; CHECK: vcvt.f32.u3230 %2 = uitofp <4 x i8> %1 to <4 x float>31 %3 = extractelement <4 x float> %2, i32 032 %4 = extractelement <4 x float> %2, i32 133 %5 = extractelement <4 x float> %2, i32 234 35 ; CHECK: vadd.f3236 %6 = fadd float %3, %437 %7 = fadd float %6, %538 39 ret float %740}41 42; CHECK-LABEL: h:43define <4 x i8> @h(<4 x float> %v) {44 ; CHECK: vcvt.{{[us]}}32.f3245 ; CHECK: vmovn.i3246 %1 = fptoui <4 x float> %v to <4 x i8>47 ret <4 x i8> %148}49 50; CHECK-LABEL: i:51define <4 x i8> @i(ptr %x, <4 x i8> %y) {52; Note: vld1 here is reasonably important. Mixing VFP and NEON53; instructions is bad on some cores54 ; CHECK: vld155 ; CHECK: vmovl.s856 ; CHECK: vmovl.s1657 ; CHECK: vrecpe58 ; CHECK: vrecps59 ; CHECK: vmul60 ; CHECK: vmovn61 %1 = load <4 x i8>, ptr %x, align 462 %2 = sdiv <4 x i8> %y, %163 ret <4 x i8> %264}65; CHECK-LABEL: j:66define <4 x i32> @j(ptr %in) nounwind {67 ; CHECK: vld168 ; CHECK: vmovl.u869 ; CHECK: vmovl.u1670 ; CHECK-NOT: vand71 %1 = load <4 x i8>, ptr %in, align 472 %2 = zext <4 x i8> %1 to <4 x i32>73 ret <4 x i32> %274}75 76