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1; RUN: llc < %s | FileCheck %s2 3target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"4target triple = "thumbv7s-apple-ios8.0.0"5 6define <8 x i8> @load_v8i8(ptr %ptr) {7;CHECK-LABEL: load_v8i8:8;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]9 %A = load ptr, ptr %ptr10 %lA = load <8 x i8>, ptr %A, align 111 ret <8 x i8> %lA12}13 14define <8 x i8> @load_v8i8_update(ptr %ptr) {15;CHECK-LABEL: load_v8i8_update:16;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!17 %A = load ptr, ptr %ptr18 %lA = load <8 x i8>, ptr %A, align 119 %inc = getelementptr <8 x i8>, ptr %A, i38 120 store ptr %inc, ptr %ptr21 ret <8 x i8> %lA22}23 24define <4 x i16> @load_v4i16(ptr %ptr) {25;CHECK-LABEL: load_v4i16:26;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]27 %A = load ptr, ptr %ptr28 %lA = load <4 x i16>, ptr %A, align 129 ret <4 x i16> %lA30}31 32define <4 x i16> @load_v4i16_update(ptr %ptr) {33;CHECK-LABEL: load_v4i16_update:34;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!35 %A = load ptr, ptr %ptr36 %lA = load <4 x i16>, ptr %A, align 137 %inc = getelementptr <4 x i16>, ptr %A, i34 138 store ptr %inc, ptr %ptr39 ret <4 x i16> %lA40}41 42define <2 x i32> @load_v2i32(ptr %ptr) {43;CHECK-LABEL: load_v2i32:44;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]45 %A = load ptr, ptr %ptr46 %lA = load <2 x i32>, ptr %A, align 147 ret <2 x i32> %lA48}49 50define <2 x i32> @load_v2i32_update(ptr %ptr) {51;CHECK-LABEL: load_v2i32_update:52;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!53 %A = load ptr, ptr %ptr54 %lA = load <2 x i32>, ptr %A, align 155 %inc = getelementptr <2 x i32>, ptr %A, i32 156 store ptr %inc, ptr %ptr57 ret <2 x i32> %lA58}59 60define <2 x float> @load_v2f32(ptr %ptr) {61;CHECK-LABEL: load_v2f32:62;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]63 %A = load ptr, ptr %ptr64 %lA = load <2 x float>, ptr %A, align 165 ret <2 x float> %lA66}67 68define <2 x float> @load_v2f32_update(ptr %ptr) {69;CHECK-LABEL: load_v2f32_update:70;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!71 %A = load ptr, ptr %ptr72 %lA = load <2 x float>, ptr %A, align 173 %inc = getelementptr <2 x float>, ptr %A, i32 174 store ptr %inc, ptr %ptr75 ret <2 x float> %lA76}77 78define <1 x i64> @load_v1i64(ptr %ptr) {79;CHECK-LABEL: load_v1i64:80;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]81 %A = load ptr, ptr %ptr82 %lA = load <1 x i64>, ptr %A, align 183 ret <1 x i64> %lA84}85 86define <1 x i64> @load_v1i64_update(ptr %ptr) {87;CHECK-LABEL: load_v1i64_update:88;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!89 %A = load ptr, ptr %ptr90 %lA = load <1 x i64>, ptr %A, align 191 %inc = getelementptr <1 x i64>, ptr %A, i31 192 store ptr %inc, ptr %ptr93 ret <1 x i64> %lA94}95 96define <16 x i8> @load_v16i8(ptr %ptr) {97;CHECK-LABEL: load_v16i8:98;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]99 %A = load ptr, ptr %ptr100 %lA = load <16 x i8>, ptr %A, align 1101 ret <16 x i8> %lA102}103 104define <16 x i8> @load_v16i8_update(ptr %ptr) {105;CHECK-LABEL: load_v16i8_update:106;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!107 %A = load ptr, ptr %ptr108 %lA = load <16 x i8>, ptr %A, align 1109 %inc = getelementptr <16 x i8>, ptr %A, i316 1110 store ptr %inc, ptr %ptr111 ret <16 x i8> %lA112}113 114define <8 x i16> @load_v8i16(ptr %ptr) {115;CHECK-LABEL: load_v8i16:116;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]117 %A = load ptr, ptr %ptr118 %lA = load <8 x i16>, ptr %A, align 1119 ret <8 x i16> %lA120}121 122define <8 x i16> @load_v8i16_update(ptr %ptr) {123;CHECK-LABEL: load_v8i16_update:124;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!125 %A = load ptr, ptr %ptr126 %lA = load <8 x i16>, ptr %A, align 1127 %inc = getelementptr <8 x i16>, ptr %A, i38 1128 store ptr %inc, ptr %ptr129 ret <8 x i16> %lA130}131 132define <4 x i32> @load_v4i32(ptr %ptr) {133;CHECK-LABEL: load_v4i32:134;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]135 %A = load ptr, ptr %ptr136 %lA = load <4 x i32>, ptr %A, align 1137 ret <4 x i32> %lA138}139 140define <4 x i32> @load_v4i32_update(ptr %ptr) {141;CHECK-LABEL: load_v4i32_update:142;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!143 %A = load ptr, ptr %ptr144 %lA = load <4 x i32>, ptr %A, align 1145 %inc = getelementptr <4 x i32>, ptr %A, i34 1146 store ptr %inc, ptr %ptr147 ret <4 x i32> %lA148}149 150define <4 x float> @load_v4f32(ptr %ptr) {151;CHECK-LABEL: load_v4f32:152;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]153 %A = load ptr, ptr %ptr154 %lA = load <4 x float>, ptr %A, align 1155 ret <4 x float> %lA156}157 158define <4 x float> @load_v4f32_update(ptr %ptr) {159;CHECK-LABEL: load_v4f32_update:160;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!161 %A = load ptr, ptr %ptr162 %lA = load <4 x float>, ptr %A, align 1163 %inc = getelementptr <4 x float>, ptr %A, i34 1164 store ptr %inc, ptr %ptr165 ret <4 x float> %lA166}167 168define <2 x i64> @load_v2i64(ptr %ptr) {169;CHECK-LABEL: load_v2i64:170;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]171 %A = load ptr, ptr %ptr172 %lA = load <2 x i64>, ptr %A, align 1173 ret <2 x i64> %lA174}175 176define <2 x i64> @load_v2i64_update(ptr %ptr) {177;CHECK-LABEL: load_v2i64_update:178;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!179 %A = load ptr, ptr %ptr180 %lA = load <2 x i64>, ptr %A, align 1181 %inc = getelementptr <2 x i64>, ptr %A, i32 1182 store ptr %inc, ptr %ptr183 ret <2 x i64> %lA184}185 186; Make sure we change the type to match alignment if necessary.187define <2 x i64> @load_v2i64_update_aligned2(ptr %ptr) {188;CHECK-LABEL: load_v2i64_update_aligned2:189;CHECK: vld1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!190 %A = load ptr, ptr %ptr191 %lA = load <2 x i64>, ptr %A, align 2192 %inc = getelementptr <2 x i64>, ptr %A, i32 1193 store ptr %inc, ptr %ptr194 ret <2 x i64> %lA195}196 197define <2 x i64> @load_v2i64_update_aligned4(ptr %ptr) {198;CHECK-LABEL: load_v2i64_update_aligned4:199;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!200 %A = load ptr, ptr %ptr201 %lA = load <2 x i64>, ptr %A, align 4202 %inc = getelementptr <2 x i64>, ptr %A, i32 1203 store ptr %inc, ptr %ptr204 ret <2 x i64> %lA205}206 207define <2 x i64> @load_v2i64_update_aligned8(ptr %ptr) {208;CHECK-LABEL: load_v2i64_update_aligned8:209;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!210 %A = load ptr, ptr %ptr211 %lA = load <2 x i64>, ptr %A, align 8212 %inc = getelementptr <2 x i64>, ptr %A, i32 1213 store ptr %inc, ptr %ptr214 ret <2 x i64> %lA215}216 217define <2 x i64> @load_v2i64_update_aligned16(ptr %ptr) {218;CHECK-LABEL: load_v2i64_update_aligned16:219;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]!220 %A = load ptr, ptr %ptr221 %lA = load <2 x i64>, ptr %A, align 16222 %inc = getelementptr <2 x i64>, ptr %A, i32 1223 store ptr %inc, ptr %ptr224 ret <2 x i64> %lA225}226 227; Make sure we don't break smaller-than-dreg extloads.228define <4 x i32> @zextload_v8i8tov8i32(ptr %ptr) {229;CHECK-LABEL: zextload_v8i8tov8i32:230;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [{{r[0-9]+}}:32]231;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}232;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}233 %A = load ptr, ptr %ptr234 %lA = load <4 x i8>, ptr %A, align 4235 %zlA = zext <4 x i8> %lA to <4 x i32>236 ret <4 x i32> %zlA237}238 239define <4 x i32> @zextload_v8i8tov8i32_fake_update(ptr %ptr) {240;CHECK-LABEL: zextload_v8i8tov8i32_fake_update:241;CHECK: ldr r[[PTRREG:[0-9]+]], [r0]242;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r[[PTRREG]]:32]243;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}244;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}245;CHECK: add.w r[[INCREG:[0-9]+]], r[[PTRREG]], #16246;CHECK: str r[[INCREG]], [r0]247 %A = load ptr, ptr %ptr248 %lA = load <4 x i8>, ptr %A, align 4249 %inc = getelementptr <4 x i8>, ptr %A, i38 4250 store ptr %inc, ptr %ptr251 %zlA = zext <4 x i8> %lA to <4 x i32>252 ret <4 x i32> %zlA253}254 255; CHECK-LABEL: test_silly_load:256; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0:128]!257; CHECK: vld1.8 {d{{[0-9]+}}}, [r0:64]!258; CHECK: ldr {{r[0-9]+}}, [r0]259 260define void @test_silly_load(ptr %addr) {261 load volatile <28 x i8>, ptr %addr262 ret void263}264 265define ptr @test_vld1_immoffset(ptr %ptr.in, ptr %ptr.out) {266; CHECK-LABEL: test_vld1_immoffset:267; CHECK: movs [[INC:r[0-9]+]], #32268; CHECK: vld1.32 {{{d[0-9]+}}, {{d[0-9]+}}}, [r0], [[INC]]269 %val = load <4 x i32>, ptr %ptr.in270 store <4 x i32> %val, ptr %ptr.out271 %next = getelementptr <4 x i32>, ptr %ptr.in, i32 2272 ret ptr %next273}274