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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - -lower-interleaved-accesses=false | FileCheck %s3 4define <8 x i8> @test_vextd(ptr %A, ptr %B) nounwind {5; CHECK-LABEL: test_vextd:6; CHECK: @ %bb.0:7; CHECK-NEXT: vldr d16, [r1]8; CHECK-NEXT: vldr d17, [r0]9; CHECK-NEXT: vext.8 d16, d17, d16, #310; CHECK-NEXT: vmov r0, r1, d1611; CHECK-NEXT: mov pc, lr12 %tmp1 = load <8 x i8>, ptr %A13 %tmp2 = load <8 x i8>, ptr %B14 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>15 ret <8 x i8> %tmp316}17 18define <8 x i8> @test_vextRd(ptr %A, ptr %B) nounwind {19; CHECK-LABEL: test_vextRd:20; CHECK: @ %bb.0:21; CHECK-NEXT: vldr d16, [r0]22; CHECK-NEXT: vldr d17, [r1]23; CHECK-NEXT: vext.8 d16, d17, d16, #524; CHECK-NEXT: vmov r0, r1, d1625; CHECK-NEXT: mov pc, lr26 %tmp1 = load <8 x i8>, ptr %A27 %tmp2 = load <8 x i8>, ptr %B28 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>29 ret <8 x i8> %tmp330}31 32define <16 x i8> @test_vextq(ptr %A, ptr %B) nounwind {33; CHECK-LABEL: test_vextq:34; CHECK: @ %bb.0:35; CHECK-NEXT: vld1.64 {d16, d17}, [r1]36; CHECK-NEXT: vld1.64 {d18, d19}, [r0]37; CHECK-NEXT: vext.8 q8, q9, q8, #338; CHECK-NEXT: vmov r0, r1, d1639; CHECK-NEXT: vmov r2, r3, d1740; CHECK-NEXT: mov pc, lr41 %tmp1 = load <16 x i8>, ptr %A42 %tmp2 = load <16 x i8>, ptr %B43 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>44 ret <16 x i8> %tmp345}46 47define <16 x i8> @test_vextRq(ptr %A, ptr %B) nounwind {48; CHECK-LABEL: test_vextRq:49; CHECK: @ %bb.0:50; CHECK-NEXT: vld1.64 {d16, d17}, [r0]51; CHECK-NEXT: vld1.64 {d18, d19}, [r1]52; CHECK-NEXT: vext.8 q8, q9, q8, #753; CHECK-NEXT: vmov r0, r1, d1654; CHECK-NEXT: vmov r2, r3, d1755; CHECK-NEXT: mov pc, lr56 %tmp1 = load <16 x i8>, ptr %A57 %tmp2 = load <16 x i8>, ptr %B58 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>59 ret <16 x i8> %tmp360}61 62define <4 x i16> @test_vextd16(ptr %A, ptr %B) nounwind {63; CHECK-LABEL: test_vextd16:64; CHECK: @ %bb.0:65; CHECK-NEXT: vldr d16, [r1]66; CHECK-NEXT: vldr d17, [r0]67; CHECK-NEXT: vext.16 d16, d17, d16, #368; CHECK-NEXT: vmov r0, r1, d1669; CHECK-NEXT: mov pc, lr70 %tmp1 = load <4 x i16>, ptr %A71 %tmp2 = load <4 x i16>, ptr %B72 %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>73 ret <4 x i16> %tmp374}75 76define <4 x i32> @test_vextq32(ptr %A, ptr %B) nounwind {77; CHECK-LABEL: test_vextq32:78; CHECK: @ %bb.0:79; CHECK-NEXT: vld1.64 {d16, d17}, [r1]80; CHECK-NEXT: vld1.64 {d18, d19}, [r0]81; CHECK-NEXT: vext.32 q8, q9, q8, #382; CHECK-NEXT: vmov r0, r1, d1683; CHECK-NEXT: vmov r2, r3, d1784; CHECK-NEXT: mov pc, lr85 %tmp1 = load <4 x i32>, ptr %A86 %tmp2 = load <4 x i32>, ptr %B87 %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>88 ret <4 x i32> %tmp389}90 91; Undef shuffle indices should not prevent matching to VEXT:92 93define <8 x i8> @test_vextd_undef(ptr %A, ptr %B) nounwind {94; CHECK-LABEL: test_vextd_undef:95; CHECK: @ %bb.0:96; CHECK-NEXT: vldr d16, [r1]97; CHECK-NEXT: vldr d17, [r0]98; CHECK-NEXT: vext.8 d16, d17, d16, #399; CHECK-NEXT: vmov r0, r1, d16100; CHECK-NEXT: mov pc, lr101 %tmp1 = load <8 x i8>, ptr %A102 %tmp2 = load <8 x i8>, ptr %B103 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10>104 ret <8 x i8> %tmp3105}106 107define <16 x i8> @test_vextRq_undef(ptr %A, ptr %B) nounwind {108; CHECK-LABEL: test_vextRq_undef:109; CHECK: @ %bb.0:110; CHECK-NEXT: vld1.64 {d16, d17}, [r0]111; CHECK-NEXT: vld1.64 {d18, d19}, [r1]112; CHECK-NEXT: vext.8 q8, q9, q8, #7113; CHECK-NEXT: vmov r0, r1, d16114; CHECK-NEXT: vmov r2, r3, d17115; CHECK-NEXT: mov pc, lr116 %tmp1 = load <16 x i8>, ptr %A117 %tmp2 = load <16 x i8>, ptr %B118 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 undef, i32 undef, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6>119 ret <16 x i8> %tmp3120}121 122define <16 x i8> @test_vextq_undef_op2(<16 x i8> %a) nounwind {123; CHECK-LABEL: test_vextq_undef_op2:124; CHECK: @ %bb.0: @ %entry125; CHECK-NEXT: vmov d17, r2, r3126; CHECK-NEXT: vmov d16, r0, r1127; CHECK-NEXT: vext.8 q8, q8, q8, #2128; CHECK-NEXT: vmov r0, r1, d16129; CHECK-NEXT: vmov r2, r3, d17130; CHECK-NEXT: mov pc, lr131entry:132 %tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>133 ret <16 x i8> %tmp1134}135 136define <8 x i8> @test_vextd_undef_op2(<8 x i8> %a) nounwind {137; CHECK-LABEL: test_vextd_undef_op2:138; CHECK: @ %bb.0: @ %entry139; CHECK-NEXT: vmov d16, r0, r1140; CHECK-NEXT: vext.8 d16, d16, d16, #2141; CHECK-NEXT: vmov r0, r1, d16142; CHECK-NEXT: mov pc, lr143entry:144 %tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>145 ret <8 x i8> %tmp1146}147 148 149define <16 x i8> @test_vextq_undef_op2_undef(<16 x i8> %a) nounwind {150; CHECK-LABEL: test_vextq_undef_op2_undef:151; CHECK: @ %bb.0: @ %entry152; CHECK-NEXT: vmov d17, r2, r3153; CHECK-NEXT: vmov d16, r0, r1154; CHECK-NEXT: vext.8 q8, q8, q8, #2155; CHECK-NEXT: vmov r0, r1, d16156; CHECK-NEXT: vmov r2, r3, d17157; CHECK-NEXT: mov pc, lr158entry:159 %tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>160 ret <16 x i8> %tmp1161}162 163define <8 x i8> @test_vextd_undef_op2_undef(<8 x i8> %a) nounwind {164; CHECK-LABEL: test_vextd_undef_op2_undef:165; CHECK: @ %bb.0: @ %entry166; CHECK-NEXT: vmov d16, r0, r1167; CHECK-NEXT: vext.8 d16, d16, d16, #2168; CHECK-NEXT: vmov r0, r1, d16169; CHECK-NEXT: mov pc, lr170entry:171 %tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 1>172 ret <8 x i8> %tmp1173}174 175; Tests for ReconstructShuffle function. Indices have to be carefully176; chosen to reach lowering phase as a BUILD_VECTOR.177 178; One vector needs vext, the other can be handled by extract_subvector179; Also checks interleaving of sources is handled correctly.180; Essence: a vext is used on %A and something saner than stack load/store for final result.181define <4 x i16> @test_interleaved(ptr %A, ptr %B) nounwind {182; CHECK-LABEL: test_interleaved:183; CHECK: @ %bb.0:184; CHECK-NEXT: vld1.64 {d16, d17}, [r0]185; CHECK-NEXT: vext.16 d16, d16, d17, #3186; CHECK-NEXT: vorr d18, d16, d16187; CHECK-NEXT: vldr d17, [r1]188; CHECK-NEXT: vuzp.16 d16, d18189; CHECK-NEXT: vzip.16 d16, d17190; CHECK-NEXT: vmov r0, r1, d16191; CHECK-NEXT: mov pc, lr192 %tmp1 = load <8 x i16>, ptr %A193 %tmp2 = load <8 x i16>, ptr %B194 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 3, i32 8, i32 5, i32 9>195 ret <4 x i16> %tmp3196}197 198; An undef in the shuffle list should still be optimizable199define <4 x i16> @test_undef(ptr %A, ptr %B) nounwind {200; CHECK-LABEL: test_undef:201; CHECK: @ %bb.0:202; CHECK-NEXT: vldr d16, [r1]203; CHECK-NEXT: vldr d17, [r0, #8]204; CHECK-NEXT: vzip.16 d17, d16205; CHECK-NEXT: vmov r0, r1, d17206; CHECK-NEXT: mov pc, lr207 %tmp1 = load <8 x i16>, ptr %A208 %tmp2 = load <8 x i16>, ptr %B209 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9>210 ret <4 x i16> %tmp3211}212 213; We should ignore a build_vector with more than two sources.214; Use illegal <32 x i16> type to produce such a shuffle after legalizing types.215; Try to look for fallback to by-element inserts.216define <4 x i16> @test_multisource(ptr %B) nounwind {217; CHECK-LABEL: test_multisource:218; CHECK: @ %bb.0:219; CHECK-NEXT: vld1.16 {d16, d17}, [r0:128]!220; CHECK-NEXT: vld1.16 {d18, d19}, [r0:128]!221; CHECK-NEXT: vld1.16 {d20, d21}, [r0:128]!222; CHECK-NEXT: vorr d23, d20, d20223; CHECK-NEXT: vldr d22, [r0]224; CHECK-NEXT: vzip.16 d23, d22225; CHECK-NEXT: vtrn.16 d16, d18226; CHECK-NEXT: vext.16 d18, d20, d23, #2227; CHECK-NEXT: vext.16 d16, d18, d16, #2228; CHECK-NEXT: vext.16 d16, d16, d16, #2229; CHECK-NEXT: vmov r0, r1, d16230; CHECK-NEXT: mov pc, lr231 %tmp1 = load <32 x i16>, ptr %B232 %tmp2 = shufflevector <32 x i16> %tmp1, <32 x i16> undef, <4 x i32> <i32 0, i32 8, i32 16, i32 24>233 ret <4 x i16> %tmp2234}235 236; We don't handle shuffles using more than half of a 128-bit vector.237; Again, test for fallback to by-element inserts.238define <4 x i16> @test_largespan(ptr %B) nounwind {239; CHECK-LABEL: test_largespan:240; CHECK: @ %bb.0:241; CHECK-NEXT: vld1.64 {d16, d17}, [r0]242; CHECK-NEXT: vorr d18, d16, d16243; CHECK-NEXT: vuzp.16 d18, d17244; CHECK-NEXT: vmov r0, r1, d18245; CHECK-NEXT: mov pc, lr246 %tmp1 = load <8 x i16>, ptr %B247 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>248 ret <4 x i16> %tmp2249}250 251; The actual shuffle code only handles some cases, make sure we check252; this rather than blindly emitting a VECTOR_SHUFFLE (infinite253; lowering loop can result otherwise).254; (There are probably better ways to lower this shuffle, but it's not255; really important.)256define <8 x i16> @test_illegal(ptr %A, ptr %B) nounwind {257; CHECK-LABEL: test_illegal:258; CHECK: @ %bb.0:259; CHECK-NEXT: vld1.64 {d16, d17}, [r0]260; CHECK-NEXT: vorr d21, d16, d16261; CHECK-NEXT: vmov.u16 r0, d16[0]262; CHECK-NEXT: vorr d22, d16, d16263; CHECK-NEXT: vmov.u16 r2, d17[3]264; CHECK-NEXT: vmov.u16 r3, d17[1]265; CHECK-NEXT: vld1.64 {d18, d19}, [r1]266; CHECK-NEXT: vmov.u16 r1, d19[1]267; CHECK-NEXT: vuzp.16 d21, d22268; CHECK-NEXT: vuzp.16 d21, d18269; CHECK-NEXT: vext.16 d16, d16, d18, #3270; CHECK-NEXT: vmov.16 d20[0], r0271; CHECK-NEXT: vmov.16 d20[1], r2272; CHECK-NEXT: vmov.16 d20[2], r3273; CHECK-NEXT: vmov r2, r3, d16274; CHECK-NEXT: vmov.16 d20[3], r1275; CHECK-NEXT: vmov r0, r1, d20276; CHECK-NEXT: mov pc, lr277 %tmp1 = load <8 x i16>, ptr %A278 %tmp2 = load <8 x i16>, ptr %B279 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9>280 ret <8 x i16> %tmp3281}282 283; PR11129284; Make sure this doesn't crash285define arm_aapcscc void @test_elem_mismatch(ptr nocapture %src, ptr nocapture %dest) nounwind {286; CHECK-LABEL: test_elem_mismatch:287; CHECK: @ %bb.0:288; CHECK-NEXT: vld1.64 {d16, d17}, [r0:128]289; CHECK-NEXT: vmov.32 r0, d16[0]290; CHECK-NEXT: vmov.32 r2, d17[0]291; CHECK-NEXT: vmov.16 d16[0], r0292; CHECK-NEXT: vmov.16 d16[1], r2293; CHECK-NEXT: vstr d16, [r1]294; CHECK-NEXT: mov pc, lr295 %tmp0 = load <2 x i64>, ptr %src, align 16296 %tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32>297 %tmp2 = extractelement <4 x i32> %tmp1, i32 0298 %tmp3 = extractelement <4 x i32> %tmp1, i32 2299 %tmp4 = trunc i32 %tmp2 to i16300 %tmp5 = trunc i32 %tmp3 to i16301 %tmp6 = insertelement <4 x i16> undef, i16 %tmp4, i32 0302 %tmp7 = insertelement <4 x i16> %tmp6, i16 %tmp5, i32 1303 store <4 x i16> %tmp7, ptr %dest, align 4304 ret void305}306 307define <4 x i32> @test_reverse_and_extract(ptr %A) {308; CHECK-LABEL: test_reverse_and_extract:309; CHECK: @ %bb.0: @ %entry310; CHECK-NEXT: vldr d16, [r0]311; CHECK-NEXT: vrev64.32 q9, q8312; CHECK-NEXT: vext.32 q8, q8, q9, #2313; CHECK-NEXT: vmov r0, r1, d16314; CHECK-NEXT: vmov r2, r3, d17315; CHECK-NEXT: mov pc, lr316entry:317 %tmp1 = load <2 x i32>, ptr %A318 %0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 0>319 ret <4 x i32> %0320}321 322define <4 x i32> @test_dup_and_extract(ptr %A) {323; CHECK-LABEL: test_dup_and_extract:324; CHECK: @ %bb.0: @ %entry325; CHECK-NEXT: vldr d16, [r0]326; CHECK-NEXT: vdup.32 q9, d16[0]327; CHECK-NEXT: vext.32 q8, q9, q8, #2328; CHECK-NEXT: vmov r0, r1, d16329; CHECK-NEXT: vmov r2, r3, d17330; CHECK-NEXT: mov pc, lr331entry:332 %tmp1 = load <2 x i32>, ptr %A333 %0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 1>334 ret <4 x i32> %0335}336 337define <4 x i32> @test_zip_and_extract(ptr %A) {338; CHECK-LABEL: test_zip_and_extract:339; CHECK: @ %bb.0: @ %entry340; CHECK-NEXT: vldr d16, [r0]341; CHECK-NEXT: vorr q9, q8, q8342; CHECK-NEXT: vorr q10, q8, q8343; CHECK-NEXT: vzip.32 q9, q10344; CHECK-NEXT: vext.32 q8, q9, q8, #2345; CHECK-NEXT: vmov r0, r1, d16346; CHECK-NEXT: vmov r2, r3, d17347; CHECK-NEXT: mov pc, lr348entry:349 %tmp1 = load <2 x i32>, ptr %A350 %0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 1>351 ret <4 x i32> %0352}353