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1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3; This tests fcmp operations that do not map directly to NEON instructions.4 5; une is implemented with VCEQ/VMVN6define <2 x i32> @vcunef32(ptr %A, ptr %B) nounwind {7;CHECK-LABEL: vcunef32:8;CHECK: vceq.f329;CHECK-NEXT: vmvn10 %tmp1 = load <2 x float>, ptr %A11 %tmp2 = load <2 x float>, ptr %B12 %tmp3 = fcmp une <2 x float> %tmp1, %tmp213 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>14 ret <2 x i32> %tmp415}16 17; olt is implemented with VCGT18define <2 x i32> @vcoltf32(ptr %A, ptr %B) nounwind {19;CHECK-LABEL: vcoltf32:20;CHECK: vcgt.f3221 %tmp1 = load <2 x float>, ptr %A22 %tmp2 = load <2 x float>, ptr %B23 %tmp3 = fcmp olt <2 x float> %tmp1, %tmp224 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>25 ret <2 x i32> %tmp426}27 28; ole is implemented with VCGE29define <2 x i32> @vcolef32(ptr %A, ptr %B) nounwind {30;CHECK-LABEL: vcolef32:31;CHECK: vcge.f3232 %tmp1 = load <2 x float>, ptr %A33 %tmp2 = load <2 x float>, ptr %B34 %tmp3 = fcmp ole <2 x float> %tmp1, %tmp235 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>36 ret <2 x i32> %tmp437}38 39; uge is implemented with VCGT/VMVN40define <2 x i32> @vcugef32(ptr %A, ptr %B) nounwind {41;CHECK-LABEL: vcugef32:42;CHECK: vcgt.f3243;CHECK-NEXT: vmvn44 %tmp1 = load <2 x float>, ptr %A45 %tmp2 = load <2 x float>, ptr %B46 %tmp3 = fcmp uge <2 x float> %tmp1, %tmp247 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>48 ret <2 x i32> %tmp449}50 51; ule is implemented with VCGT/VMVN52define <2 x i32> @vculef32(ptr %A, ptr %B) nounwind {53;CHECK-LABEL: vculef32:54;CHECK: vcgt.f3255;CHECK-NEXT: vmvn56 %tmp1 = load <2 x float>, ptr %A57 %tmp2 = load <2 x float>, ptr %B58 %tmp3 = fcmp ule <2 x float> %tmp1, %tmp259 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>60 ret <2 x i32> %tmp461}62 63; ugt is implemented with VCGE/VMVN64define <2 x i32> @vcugtf32(ptr %A, ptr %B) nounwind {65;CHECK-LABEL: vcugtf32:66;CHECK: vcge.f3267;CHECK-NEXT: vmvn68 %tmp1 = load <2 x float>, ptr %A69 %tmp2 = load <2 x float>, ptr %B70 %tmp3 = fcmp ugt <2 x float> %tmp1, %tmp271 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>72 ret <2 x i32> %tmp473}74 75; ult is implemented with VCGE/VMVN76define <2 x i32> @vcultf32(ptr %A, ptr %B) nounwind {77;CHECK-LABEL: vcultf32:78;CHECK: vcge.f3279;CHECK-NEXT: vmvn80 %tmp1 = load <2 x float>, ptr %A81 %tmp2 = load <2 x float>, ptr %B82 %tmp3 = fcmp ult <2 x float> %tmp1, %tmp283 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>84 ret <2 x i32> %tmp485}86 87; ueq is implemented with VCGT/VCGT/VORR/VMVN88define <2 x i32> @vcueqf32(ptr %A, ptr %B) nounwind {89;CHECK-LABEL: vcueqf32:90;CHECK: vcgt.f3291;CHECK-NEXT: vcgt.f3292;CHECK-NEXT: vorr93;CHECK-NEXT: vmvn94 %tmp1 = load <2 x float>, ptr %A95 %tmp2 = load <2 x float>, ptr %B96 %tmp3 = fcmp ueq <2 x float> %tmp1, %tmp297 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>98 ret <2 x i32> %tmp499}100 101; one is implemented with VCGT/VCGT/VORR102define <2 x i32> @vconef32(ptr %A, ptr %B) nounwind {103;CHECK-LABEL: vconef32:104;CHECK: vcgt.f32105;CHECK-NEXT: vcgt.f32106;CHECK-NEXT: vorr107 %tmp1 = load <2 x float>, ptr %A108 %tmp2 = load <2 x float>, ptr %B109 %tmp3 = fcmp one <2 x float> %tmp1, %tmp2110 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>111 ret <2 x i32> %tmp4112}113 114; uno is implemented with VCGT/VCGE/VORR/VMVN115define <2 x i32> @vcunof32(ptr %A, ptr %B) nounwind {116;CHECK-LABEL: vcunof32:117;CHECK: vcge.f32118;CHECK-NEXT: vcgt.f32119;CHECK-NEXT: vorr120;CHECK-NEXT: vmvn121 %tmp1 = load <2 x float>, ptr %A122 %tmp2 = load <2 x float>, ptr %B123 %tmp3 = fcmp uno <2 x float> %tmp1, %tmp2124 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>125 ret <2 x i32> %tmp4126}127 128; ord is implemented with VCGT/VCGE/VORR129define <2 x i32> @vcordf32(ptr %A, ptr %B) nounwind {130;CHECK-LABEL: vcordf32:131;CHECK: vcge.f32132;CHECK-NEXT: vcgt.f32133;CHECK-NEXT: vorr134 %tmp1 = load <2 x float>, ptr %A135 %tmp2 = load <2 x float>, ptr %B136 %tmp3 = fcmp ord <2 x float> %tmp1, %tmp2137 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>138 ret <2 x i32> %tmp4139}140