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1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3define <8 x i8> @vhadds8(ptr %A, ptr %B) nounwind {4;CHECK-LABEL: vhadds8:5;CHECK: vhadd.s86 %tmp1 = load <8 x i8>, ptr %A7 %tmp2 = load <8 x i8>, ptr %B8 %tmp3 = call <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)9 ret <8 x i8> %tmp310}11 12define <4 x i16> @vhadds16(ptr %A, ptr %B) nounwind {13;CHECK-LABEL: vhadds16:14;CHECK: vhadd.s1615 %tmp1 = load <4 x i16>, ptr %A16 %tmp2 = load <4 x i16>, ptr %B17 %tmp3 = call <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)18 ret <4 x i16> %tmp319}20 21define <2 x i32> @vhadds32(ptr %A, ptr %B) nounwind {22;CHECK-LABEL: vhadds32:23;CHECK: vhadd.s3224 %tmp1 = load <2 x i32>, ptr %A25 %tmp2 = load <2 x i32>, ptr %B26 %tmp3 = call <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)27 ret <2 x i32> %tmp328}29 30define <8 x i8> @vhaddu8(ptr %A, ptr %B) nounwind {31;CHECK-LABEL: vhaddu8:32;CHECK: vhadd.u833 %tmp1 = load <8 x i8>, ptr %A34 %tmp2 = load <8 x i8>, ptr %B35 %tmp3 = call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)36 ret <8 x i8> %tmp337}38 39define <4 x i16> @vhaddu16(ptr %A, ptr %B) nounwind {40;CHECK-LABEL: vhaddu16:41;CHECK: vhadd.u1642 %tmp1 = load <4 x i16>, ptr %A43 %tmp2 = load <4 x i16>, ptr %B44 %tmp3 = call <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)45 ret <4 x i16> %tmp346}47 48define <2 x i32> @vhaddu32(ptr %A, ptr %B) nounwind {49;CHECK-LABEL: vhaddu32:50;CHECK: vhadd.u3251 %tmp1 = load <2 x i32>, ptr %A52 %tmp2 = load <2 x i32>, ptr %B53 %tmp3 = call <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)54 ret <2 x i32> %tmp355}56 57define <16 x i8> @vhaddQs8(ptr %A, ptr %B) nounwind {58;CHECK-LABEL: vhaddQs8:59;CHECK: vhadd.s860 %tmp1 = load <16 x i8>, ptr %A61 %tmp2 = load <16 x i8>, ptr %B62 %tmp3 = call <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)63 ret <16 x i8> %tmp364}65 66define <8 x i16> @vhaddQs16(ptr %A, ptr %B) nounwind {67;CHECK-LABEL: vhaddQs16:68;CHECK: vhadd.s1669 %tmp1 = load <8 x i16>, ptr %A70 %tmp2 = load <8 x i16>, ptr %B71 %tmp3 = call <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)72 ret <8 x i16> %tmp373}74 75define <4 x i32> @vhaddQs32(ptr %A, ptr %B) nounwind {76;CHECK-LABEL: vhaddQs32:77;CHECK: vhadd.s3278 %tmp1 = load <4 x i32>, ptr %A79 %tmp2 = load <4 x i32>, ptr %B80 %tmp3 = call <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)81 ret <4 x i32> %tmp382}83 84define <16 x i8> @vhaddQu8(ptr %A, ptr %B) nounwind {85;CHECK-LABEL: vhaddQu8:86;CHECK: vhadd.u887 %tmp1 = load <16 x i8>, ptr %A88 %tmp2 = load <16 x i8>, ptr %B89 %tmp3 = call <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)90 ret <16 x i8> %tmp391}92 93define <8 x i16> @vhaddQu16(ptr %A, ptr %B) nounwind {94;CHECK-LABEL: vhaddQu16:95;CHECK: vhadd.u1696 %tmp1 = load <8 x i16>, ptr %A97 %tmp2 = load <8 x i16>, ptr %B98 %tmp3 = call <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)99 ret <8 x i16> %tmp3100}101 102define <4 x i32> @vhaddQu32(ptr %A, ptr %B) nounwind {103;CHECK-LABEL: vhaddQu32:104;CHECK: vhadd.u32105 %tmp1 = load <4 x i32>, ptr %A106 %tmp2 = load <4 x i32>, ptr %B107 %tmp3 = call <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)108 ret <4 x i32> %tmp3109}110 111declare <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone112declare <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone113declare <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone114 115declare <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone116declare <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone117declare <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone118 119declare <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone120declare <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone121declare <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone122 123declare <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone124declare <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone125declare <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone126 127define <8 x i8> @vrhadds8(ptr %A, ptr %B) nounwind {128;CHECK-LABEL: vrhadds8:129;CHECK: vrhadd.s8130 %tmp1 = load <8 x i8>, ptr %A131 %tmp2 = load <8 x i8>, ptr %B132 %tmp3 = call <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)133 ret <8 x i8> %tmp3134}135 136define <4 x i16> @vrhadds16(ptr %A, ptr %B) nounwind {137;CHECK-LABEL: vrhadds16:138;CHECK: vrhadd.s16139 %tmp1 = load <4 x i16>, ptr %A140 %tmp2 = load <4 x i16>, ptr %B141 %tmp3 = call <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)142 ret <4 x i16> %tmp3143}144 145define <2 x i32> @vrhadds32(ptr %A, ptr %B) nounwind {146;CHECK-LABEL: vrhadds32:147;CHECK: vrhadd.s32148 %tmp1 = load <2 x i32>, ptr %A149 %tmp2 = load <2 x i32>, ptr %B150 %tmp3 = call <2 x i32> @llvm.arm.neon.vrhadds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)151 ret <2 x i32> %tmp3152}153 154define <8 x i8> @vrhaddu8(ptr %A, ptr %B) nounwind {155;CHECK-LABEL: vrhaddu8:156;CHECK: vrhadd.u8157 %tmp1 = load <8 x i8>, ptr %A158 %tmp2 = load <8 x i8>, ptr %B159 %tmp3 = call <8 x i8> @llvm.arm.neon.vrhaddu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)160 ret <8 x i8> %tmp3161}162 163define <4 x i16> @vrhaddu16(ptr %A, ptr %B) nounwind {164;CHECK-LABEL: vrhaddu16:165;CHECK: vrhadd.u16166 %tmp1 = load <4 x i16>, ptr %A167 %tmp2 = load <4 x i16>, ptr %B168 %tmp3 = call <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)169 ret <4 x i16> %tmp3170}171 172define <2 x i32> @vrhaddu32(ptr %A, ptr %B) nounwind {173;CHECK-LABEL: vrhaddu32:174;CHECK: vrhadd.u32175 %tmp1 = load <2 x i32>, ptr %A176 %tmp2 = load <2 x i32>, ptr %B177 %tmp3 = call <2 x i32> @llvm.arm.neon.vrhaddu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)178 ret <2 x i32> %tmp3179}180 181define <16 x i8> @vrhaddQs8(ptr %A, ptr %B) nounwind {182;CHECK-LABEL: vrhaddQs8:183;CHECK: vrhadd.s8184 %tmp1 = load <16 x i8>, ptr %A185 %tmp2 = load <16 x i8>, ptr %B186 %tmp3 = call <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)187 ret <16 x i8> %tmp3188}189 190define <8 x i16> @vrhaddQs16(ptr %A, ptr %B) nounwind {191;CHECK-LABEL: vrhaddQs16:192;CHECK: vrhadd.s16193 %tmp1 = load <8 x i16>, ptr %A194 %tmp2 = load <8 x i16>, ptr %B195 %tmp3 = call <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)196 ret <8 x i16> %tmp3197}198 199define <4 x i32> @vrhaddQs32(ptr %A, ptr %B) nounwind {200;CHECK-LABEL: vrhaddQs32:201;CHECK: vrhadd.s32202 %tmp1 = load <4 x i32>, ptr %A203 %tmp2 = load <4 x i32>, ptr %B204 %tmp3 = call <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)205 ret <4 x i32> %tmp3206}207 208define <16 x i8> @vrhaddQu8(ptr %A, ptr %B) nounwind {209;CHECK-LABEL: vrhaddQu8:210;CHECK: vrhadd.u8211 %tmp1 = load <16 x i8>, ptr %A212 %tmp2 = load <16 x i8>, ptr %B213 %tmp3 = call <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)214 ret <16 x i8> %tmp3215}216 217define <8 x i16> @vrhaddQu16(ptr %A, ptr %B) nounwind {218;CHECK-LABEL: vrhaddQu16:219;CHECK: vrhadd.u16220 %tmp1 = load <8 x i16>, ptr %A221 %tmp2 = load <8 x i16>, ptr %B222 %tmp3 = call <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)223 ret <8 x i16> %tmp3224}225 226define <4 x i32> @vrhaddQu32(ptr %A, ptr %B) nounwind {227;CHECK-LABEL: vrhaddQu32:228;CHECK: vrhadd.u32229 %tmp1 = load <4 x i32>, ptr %A230 %tmp2 = load <4 x i32>, ptr %B231 %tmp3 = call <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)232 ret <4 x i32> %tmp3233}234 235declare <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone236declare <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone237declare <2 x i32> @llvm.arm.neon.vrhadds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone238 239declare <8 x i8> @llvm.arm.neon.vrhaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone240declare <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone241declare <2 x i32> @llvm.arm.neon.vrhaddu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone242 243declare <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone244declare <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone245declare <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone246 247declare <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone248declare <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone249declare <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone250