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1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3define <8 x i8> @vhsubs8(ptr %A, ptr %B) nounwind {4;CHECK-LABEL: vhsubs8:5;CHECK: vhsub.s86 %tmp1 = load <8 x i8>, ptr %A7 %tmp2 = load <8 x i8>, ptr %B8 %tmp3 = call <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)9 ret <8 x i8> %tmp310}11 12define <4 x i16> @vhsubs16(ptr %A, ptr %B) nounwind {13;CHECK-LABEL: vhsubs16:14;CHECK: vhsub.s1615 %tmp1 = load <4 x i16>, ptr %A16 %tmp2 = load <4 x i16>, ptr %B17 %tmp3 = call <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)18 ret <4 x i16> %tmp319}20 21define <2 x i32> @vhsubs32(ptr %A, ptr %B) nounwind {22;CHECK-LABEL: vhsubs32:23;CHECK: vhsub.s3224 %tmp1 = load <2 x i32>, ptr %A25 %tmp2 = load <2 x i32>, ptr %B26 %tmp3 = call <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)27 ret <2 x i32> %tmp328}29 30define <8 x i8> @vhsubu8(ptr %A, ptr %B) nounwind {31;CHECK-LABEL: vhsubu8:32;CHECK: vhsub.u833 %tmp1 = load <8 x i8>, ptr %A34 %tmp2 = load <8 x i8>, ptr %B35 %tmp3 = call <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)36 ret <8 x i8> %tmp337}38 39define <4 x i16> @vhsubu16(ptr %A, ptr %B) nounwind {40;CHECK-LABEL: vhsubu16:41;CHECK: vhsub.u1642 %tmp1 = load <4 x i16>, ptr %A43 %tmp2 = load <4 x i16>, ptr %B44 %tmp3 = call <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)45 ret <4 x i16> %tmp346}47 48define <2 x i32> @vhsubu32(ptr %A, ptr %B) nounwind {49;CHECK-LABEL: vhsubu32:50;CHECK: vhsub.u3251 %tmp1 = load <2 x i32>, ptr %A52 %tmp2 = load <2 x i32>, ptr %B53 %tmp3 = call <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)54 ret <2 x i32> %tmp355}56 57define <16 x i8> @vhsubQs8(ptr %A, ptr %B) nounwind {58;CHECK-LABEL: vhsubQs8:59;CHECK: vhsub.s860 %tmp1 = load <16 x i8>, ptr %A61 %tmp2 = load <16 x i8>, ptr %B62 %tmp3 = call <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)63 ret <16 x i8> %tmp364}65 66define <8 x i16> @vhsubQs16(ptr %A, ptr %B) nounwind {67;CHECK-LABEL: vhsubQs16:68;CHECK: vhsub.s1669 %tmp1 = load <8 x i16>, ptr %A70 %tmp2 = load <8 x i16>, ptr %B71 %tmp3 = call <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)72 ret <8 x i16> %tmp373}74 75define <4 x i32> @vhsubQs32(ptr %A, ptr %B) nounwind {76;CHECK-LABEL: vhsubQs32:77;CHECK: vhsub.s3278 %tmp1 = load <4 x i32>, ptr %A79 %tmp2 = load <4 x i32>, ptr %B80 %tmp3 = call <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)81 ret <4 x i32> %tmp382}83 84define <16 x i8> @vhsubQu8(ptr %A, ptr %B) nounwind {85;CHECK-LABEL: vhsubQu8:86;CHECK: vhsub.u887 %tmp1 = load <16 x i8>, ptr %A88 %tmp2 = load <16 x i8>, ptr %B89 %tmp3 = call <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)90 ret <16 x i8> %tmp391}92 93define <8 x i16> @vhsubQu16(ptr %A, ptr %B) nounwind {94;CHECK-LABEL: vhsubQu16:95;CHECK: vhsub.u1696 %tmp1 = load <8 x i16>, ptr %A97 %tmp2 = load <8 x i16>, ptr %B98 %tmp3 = call <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)99 ret <8 x i16> %tmp3100}101 102define <4 x i32> @vhsubQu32(ptr %A, ptr %B) nounwind {103;CHECK-LABEL: vhsubQu32:104;CHECK: vhsub.u32105 %tmp1 = load <4 x i32>, ptr %A106 %tmp2 = load <4 x i32>, ptr %B107 %tmp3 = call <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)108 ret <4 x i32> %tmp3109}110 111declare <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone112declare <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone113declare <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone114 115declare <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone116declare <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone117declare <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone118 119declare <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone120declare <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone121declare <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone122 123declare <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone124declare <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone125declare <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone126