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1; RUN: llc -mtriple=arm -mattr=+neon %s -o - | FileCheck %s2 3; Check codegen for 64-bit icmp operations, which don't directly map to any4; instruction.5 6define <2 x i64> @vne(ptr %A, ptr %B) nounwind {7;CHECK-LABEL: vne:8;CHECK: vceq.i329;CHECK-NEXT: vrev64.3210;CHECK-NEXT: vand11;CHECK-NEXT: vmvn12;CHECK-NEXT: vmov13;CHECK-NEXT: vmov14;CHECK-NEXT: mov pc, lr15 %tmp1 = load <2 x i64>, ptr %A16 %tmp2 = load <2 x i64>, ptr %B17 %tmp3 = icmp ne <2 x i64> %tmp1, %tmp218 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>19 ret <2 x i64> %tmp420}21 22define <2 x i64> @veq(ptr %A, ptr %B) nounwind {23;CHECK-LABEL: veq:24;CHECK: vceq.i3225;CHECK-NEXT: vrev64.3226;CHECK-NEXT: vand27;CHECK-NEXT: vmov28;CHECK-NEXT: vmov29;CHECK-NEXT: mov pc, lr30 %tmp1 = load <2 x i64>, ptr %A31 %tmp2 = load <2 x i64>, ptr %B32 %tmp3 = icmp eq <2 x i64> %tmp1, %tmp233 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>34 ret <2 x i64> %tmp435}36 37; FIXME: We currently generate terrible code for this.38; (Atop < Btop) | ((ATop == BTop) & (ABottom < BBottom))39; would come out to roughly 6 instructions, but we currently40; scalarize it.41define <2 x i64> @vult(ptr %A, ptr %B) nounwind {42;CHECK-LABEL: vult:43;CHECK: subs44;CHECK: sbcs45;CHECK: subs46;CHECK: sbcs47 %tmp1 = load <2 x i64>, ptr %A48 %tmp2 = load <2 x i64>, ptr %B49 %tmp3 = icmp ult <2 x i64> %tmp1, %tmp250 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>51 ret <2 x i64> %tmp452}53