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1; RUN: llc -mtriple=arm -mattr=+neon %s -o - | FileCheck %s2 3; This tests icmp operations that do not map directly to NEON instructions.4; Not-equal (ne) operations are implemented by VCEQ/VMVN. Less-than (lt/ult)5; and less-than-or-equal (le/ule) are implemented by swapping the arguments6; to VCGT and VCGE. Test all the operand types for not-equal but only sample7; the other operations.8 9define <8 x i8> @vcnei8(ptr %A, ptr %B) nounwind {10;CHECK-LABEL: vcnei8:11;CHECK: vceq.i812;CHECK-NEXT: vmvn13 %tmp1 = load <8 x i8>, ptr %A14 %tmp2 = load <8 x i8>, ptr %B15 %tmp3 = icmp ne <8 x i8> %tmp1, %tmp216 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>17 ret <8 x i8> %tmp418}19 20define <4 x i16> @vcnei16(ptr %A, ptr %B) nounwind {21;CHECK-LABEL: vcnei16:22;CHECK: vceq.i1623;CHECK-NEXT: vmvn24 %tmp1 = load <4 x i16>, ptr %A25 %tmp2 = load <4 x i16>, ptr %B26 %tmp3 = icmp ne <4 x i16> %tmp1, %tmp227 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>28 ret <4 x i16> %tmp429}30 31define <2 x i32> @vcnei32(ptr %A, ptr %B) nounwind {32;CHECK-LABEL: vcnei32:33;CHECK: vceq.i3234;CHECK-NEXT: vmvn35 %tmp1 = load <2 x i32>, ptr %A36 %tmp2 = load <2 x i32>, ptr %B37 %tmp3 = icmp ne <2 x i32> %tmp1, %tmp238 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>39 ret <2 x i32> %tmp440}41 42define <16 x i8> @vcneQi8(ptr %A, ptr %B) nounwind {43;CHECK-LABEL: vcneQi8:44;CHECK: vceq.i845;CHECK-NEXT: vmvn46 %tmp1 = load <16 x i8>, ptr %A47 %tmp2 = load <16 x i8>, ptr %B48 %tmp3 = icmp ne <16 x i8> %tmp1, %tmp249 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>50 ret <16 x i8> %tmp451}52 53define <8 x i16> @vcneQi16(ptr %A, ptr %B) nounwind {54;CHECK-LABEL: vcneQi16:55;CHECK: vceq.i1656;CHECK-NEXT: vmvn57 %tmp1 = load <8 x i16>, ptr %A58 %tmp2 = load <8 x i16>, ptr %B59 %tmp3 = icmp ne <8 x i16> %tmp1, %tmp260 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>61 ret <8 x i16> %tmp462}63 64define <4 x i32> @vcneQi32(ptr %A, ptr %B) nounwind {65;CHECK-LABEL: vcneQi32:66;CHECK: vceq.i3267;CHECK-NEXT: vmvn68 %tmp1 = load <4 x i32>, ptr %A69 %tmp2 = load <4 x i32>, ptr %B70 %tmp3 = icmp ne <4 x i32> %tmp1, %tmp271 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>72 ret <4 x i32> %tmp473}74 75define <16 x i8> @vcltQs8(ptr %A, ptr %B) nounwind {76;CHECK-LABEL: vcltQs8:77;CHECK: vcgt.s878 %tmp1 = load <16 x i8>, ptr %A79 %tmp2 = load <16 x i8>, ptr %B80 %tmp3 = icmp slt <16 x i8> %tmp1, %tmp281 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>82 ret <16 x i8> %tmp483}84 85define <4 x i16> @vcles16(ptr %A, ptr %B) nounwind {86;CHECK-LABEL: vcles16:87;CHECK: vcge.s1688 %tmp1 = load <4 x i16>, ptr %A89 %tmp2 = load <4 x i16>, ptr %B90 %tmp3 = icmp sle <4 x i16> %tmp1, %tmp291 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>92 ret <4 x i16> %tmp493}94 95define <4 x i16> @vcltu16(ptr %A, ptr %B) nounwind {96;CHECK-LABEL: vcltu16:97;CHECK: vcgt.u1698 %tmp1 = load <4 x i16>, ptr %A99 %tmp2 = load <4 x i16>, ptr %B100 %tmp3 = icmp ult <4 x i16> %tmp1, %tmp2101 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>102 ret <4 x i16> %tmp4103}104 105define <4 x i32> @vcleQu32(ptr %A, ptr %B) nounwind {106;CHECK-LABEL: vcleQu32:107;CHECK: vcge.u32108 %tmp1 = load <4 x i32>, ptr %A109 %tmp2 = load <4 x i32>, ptr %B110 %tmp3 = icmp ule <4 x i32> %tmp1, %tmp2111 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>112 ret <4 x i32> %tmp4113}114