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1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }4%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }5%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }6%struct.__neon_float32x2x4_t = type { <2 x float>, <2 x float>, <2 x float>, <2 x float> }7%struct.__neon_int64x1x4_t = type { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> }8 9%struct.__neon_int8x16x4_t = type { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }10%struct.__neon_int16x8x4_t = type { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }11%struct.__neon_int32x4x4_t = type { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> }12%struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }13 14define <8 x i8> @vld4i8(ptr %A) nounwind {15;CHECK-LABEL: vld4i8:16;Check the alignment value. Max for this instruction is 256 bits:17;CHECK: vld4.8 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:64]18 %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0(ptr %A, i32 8)19 %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 020 %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 221 %tmp4 = add <8 x i8> %tmp2, %tmp322 ret <8 x i8> %tmp423}24 25;Check for a post-increment updating load with register increment.26define <8 x i8> @vld4i8_update(ptr %ptr, i32 %inc) nounwind {27;CHECK-LABEL: vld4i8_update:28;CHECK: vld4.8 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:128], r129 %A = load ptr, ptr %ptr30 %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0(ptr %A, i32 16)31 %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 032 %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 233 %tmp4 = add <8 x i8> %tmp2, %tmp334 %tmp5 = getelementptr i8, ptr %A, i32 %inc35 store ptr %tmp5, ptr %ptr36 ret <8 x i8> %tmp437}38 39define <4 x i16> @vld4i16(ptr %A) nounwind {40;CHECK-LABEL: vld4i16:41;Check the alignment value. Max for this instruction is 256 bits:42;CHECK: vld4.16 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:128]43 %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16.p0(ptr %A, i32 16)44 %tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 045 %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 246 %tmp4 = add <4 x i16> %tmp2, %tmp347 ret <4 x i16> %tmp448}49 50define <2 x i32> @vld4i32(ptr %A) nounwind {51;CHECK-LABEL: vld4i32:52;Check the alignment value. Max for this instruction is 256 bits:53;CHECK: vld4.32 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:256]54 %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32.p0(ptr %A, i32 32)55 %tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 056 %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 257 %tmp4 = add <2 x i32> %tmp2, %tmp358 ret <2 x i32> %tmp459}60 61define <2 x float> @vld4f(ptr %A) nounwind {62;CHECK-LABEL: vld4f:63;CHECK: vld4.3264 %tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32.p0(ptr %A, i32 1)65 %tmp2 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 066 %tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 267 %tmp4 = fadd <2 x float> %tmp2, %tmp368 ret <2 x float> %tmp469}70 71define <1 x i64> @vld4i64(ptr %A) nounwind {72;CHECK-LABEL: vld4i64:73;Check the alignment value. Max for this instruction is 256 bits:74;CHECK: vld1.64 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:256]75 %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0(ptr %A, i32 64)76 %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 077 %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 278 %tmp4 = add <1 x i64> %tmp2, %tmp379 ret <1 x i64> %tmp480}81 82define <1 x i64> @vld4i64_update(ptr %ptr, ptr %A) nounwind {83;CHECK-LABEL: vld4i64_update:84;CHECK: vld1.64 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:256]!85 %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0(ptr %A, i32 64)86 %tmp5 = getelementptr i64, ptr %A, i32 487 store ptr %tmp5, ptr %ptr88 %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 089 %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 290 %tmp4 = add <1 x i64> %tmp2, %tmp391 ret <1 x i64> %tmp492}93 94define <1 x i64> @vld4i64_reg_update(ptr %ptr, ptr %A) nounwind {95;CHECK-LABEL: vld4i64_reg_update:96;CHECK: vld1.64 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:256], {{r[0-9]+|lr}}97 %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0(ptr %A, i32 64)98 %tmp5 = getelementptr i64, ptr %A, i32 199 store ptr %tmp5, ptr %ptr100 %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0101 %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2102 %tmp4 = add <1 x i64> %tmp2, %tmp3103 ret <1 x i64> %tmp4104}105 106define <16 x i8> @vld4Qi8(ptr %A) nounwind {107;CHECK-LABEL: vld4Qi8:108;Check the alignment value. Max for this instruction is 256 bits:109;CHECK: vld4.8 {d16, d18, d20, d22}, [{{r[0-9]+|lr}}:256]!110;CHECK: vld4.8 {d17, d19, d21, d23}, [{{r[0-9]+|lr}}:256]111 %tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8.p0(ptr %A, i32 64)112 %tmp2 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 0113 %tmp3 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 2114 %tmp4 = add <16 x i8> %tmp2, %tmp3115 ret <16 x i8> %tmp4116}117 118define <8 x i16> @vld4Qi16(ptr %A) nounwind {119;CHECK-LABEL: vld4Qi16:120;Check for no alignment specifier.121;CHECK: vld4.16 {d16, d18, d20, d22}, [{{r[0-9]+|lr}}]!122;CHECK: vld4.16 {d17, d19, d21, d23}, [{{r[0-9]+|lr}}]123 %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16.p0(ptr %A, i32 1)124 %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0125 %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2126 %tmp4 = add <8 x i16> %tmp2, %tmp3127 ret <8 x i16> %tmp4128}129 130;Check for a post-increment updating load. 131define <8 x i16> @vld4Qi16_update(ptr %ptr) nounwind {132;CHECK-LABEL: vld4Qi16_update:133;CHECK: vld4.16 {d16, d18, d20, d22}, [{{r[0-9]+|lr}}:64]!134;CHECK: vld4.16 {d17, d19, d21, d23}, [{{r[0-9]+|lr}}:64]!135 %A = load ptr, ptr %ptr136 %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16.p0(ptr %A, i32 8)137 %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0138 %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2139 %tmp4 = add <8 x i16> %tmp2, %tmp3140 %tmp5 = getelementptr i16, ptr %A, i32 32141 store ptr %tmp5, ptr %ptr142 ret <8 x i16> %tmp4143}144 145define <4 x i32> @vld4Qi32(ptr %A) nounwind {146;CHECK-LABEL: vld4Qi32:147;CHECK: vld4.32148;CHECK: vld4.32149 %tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0(ptr %A, i32 1)150 %tmp2 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 0151 %tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 2152 %tmp4 = add <4 x i32> %tmp2, %tmp3153 ret <4 x i32> %tmp4154}155 156define <4 x float> @vld4Qf(ptr %A) nounwind {157;CHECK-LABEL: vld4Qf:158;CHECK: vld4.32159;CHECK: vld4.32160 %tmp1 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32.p0(ptr %A, i32 1)161 %tmp2 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 0162 %tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 2163 %tmp4 = fadd <4 x float> %tmp2, %tmp3164 ret <4 x float> %tmp4165}166 167declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0(ptr, i32) nounwind readonly168declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16.p0(ptr, i32) nounwind readonly169declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32.p0(ptr, i32) nounwind readonly170declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32.p0(ptr, i32) nounwind readonly171declare %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0(ptr, i32) nounwind readonly172 173declare %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8.p0(ptr, i32) nounwind readonly174declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16.p0(ptr, i32) nounwind readonly175declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0(ptr, i32) nounwind readonly176declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32.p0(ptr, i32) nounwind readonly177