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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s3 4define <8 x i8> @vld1dupi8(ptr %A) nounwind {5; CHECK-LABEL: vld1dupi8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vld1.8 {d16[]}, [r0]8; CHECK-NEXT: vmov r0, r1, d169; CHECK-NEXT: mov pc, lr10;Check the (default) alignment value.11 %tmp1 = load i8, ptr %A, align 812 %tmp2 = insertelement <8 x i8> undef, i8 %tmp1, i32 013 %tmp3 = shufflevector <8 x i8> %tmp2, <8 x i8> undef, <8 x i32> zeroinitializer14 ret <8 x i8> %tmp315}16 17define <8 x i8> @vld1dupi8_preinc(ptr noalias nocapture %a, i32 %b) nounwind {18; CHECK-LABEL: vld1dupi8_preinc:19; CHECK: @ %bb.0: @ %entry20; CHECK-NEXT: ldr r2, [r0]21; CHECK-NEXT: add r3, r2, r122; CHECK-NEXT: str r3, [r0]23; CHECK-NEXT: vld1.8 {d16[]}, [r3]24; CHECK-NEXT: vmov r2, r1, d1625; CHECK-NEXT: mov r0, r226; CHECK-NEXT: mov pc, lr27entry:28 %0 = load ptr, ptr %a, align 429 %add.ptr = getelementptr inbounds i8, ptr %0, i32 %b30 %1 = load i8, ptr %add.ptr, align 131 %2 = insertelement <8 x i8> undef, i8 %1, i32 032 %lane = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer33 store ptr %add.ptr, ptr %a, align 434 ret <8 x i8> %lane35}36 37define <8 x i8> @vld1dupi8_postinc_fixed(ptr noalias nocapture %a) nounwind {38; CHECK-LABEL: vld1dupi8_postinc_fixed:39; CHECK: @ %bb.0: @ %entry40; CHECK-NEXT: ldr r3, [r0]41; CHECK-NEXT: vld1.8 {d16[]}, [r3]!42; CHECK-NEXT: str r3, [r0]43; CHECK-NEXT: vmov r2, r1, d1644; CHECK-NEXT: mov r0, r245; CHECK-NEXT: mov pc, lr46entry:47 %0 = load ptr, ptr %a, align 448 %1 = load i8, ptr %0, align 149 %2 = insertelement <8 x i8> undef, i8 %1, i32 050 %lane = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer51 %add.ptr = getelementptr inbounds i8, ptr %0, i32 152 store ptr %add.ptr, ptr %a, align 453 ret <8 x i8> %lane54}55 56define <8 x i8> @vld1dupi8_postinc_register(ptr noalias nocapture %a, i32 %n) nounwind {57; CHECK-LABEL: vld1dupi8_postinc_register:58; CHECK: @ %bb.0: @ %entry59; CHECK-NEXT: ldr r3, [r0]60; CHECK-NEXT: vld1.8 {d16[]}, [r3], r161; CHECK-NEXT: str r3, [r0]62; CHECK-NEXT: vmov r2, r1, d1663; CHECK-NEXT: mov r0, r264; CHECK-NEXT: mov pc, lr65entry:66 %0 = load ptr, ptr %a, align 467 %1 = load i8, ptr %0, align 168 %2 = insertelement <8 x i8> undef, i8 %1, i32 069 %lane = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer70 %add.ptr = getelementptr inbounds i8, ptr %0, i32 %n71 store ptr %add.ptr, ptr %a, align 472 ret <8 x i8> %lane73}74 75define <16 x i8> @vld1dupqi8_preinc(ptr noalias nocapture %a, i32 %b) nounwind {76; CHECK-LABEL: vld1dupqi8_preinc:77; CHECK: @ %bb.0: @ %entry78; CHECK-NEXT: .save {r11, lr}79; CHECK-NEXT: push {r11, lr}80; CHECK-NEXT: ldr r2, [r0]81; CHECK-NEXT: add lr, r2, r182; CHECK-NEXT: str lr, [r0]83; CHECK-NEXT: vld1.8 {d16[], d17[]}, [lr]84; CHECK-NEXT: vmov r12, r1, d1685; CHECK-NEXT: vmov r2, r3, d1786; CHECK-NEXT: mov r0, r1287; CHECK-NEXT: pop {r11, lr}88; CHECK-NEXT: mov pc, lr89entry:90 %0 = load ptr, ptr %a, align 491 %add.ptr = getelementptr inbounds i8, ptr %0, i32 %b92 %1 = load i8, ptr %add.ptr, align 193 %2 = insertelement <16 x i8> undef, i8 %1, i32 094 %lane = shufflevector <16 x i8> %2, <16 x i8> undef, <16 x i32> zeroinitializer95 store ptr %add.ptr, ptr %a, align 496 ret <16 x i8> %lane97}98 99define <16 x i8> @vld1dupqi8_postinc_fixed(ptr noalias nocapture %a) nounwind {100; CHECK-LABEL: vld1dupqi8_postinc_fixed:101; CHECK: @ %bb.0: @ %entry102; CHECK-NEXT: .save {r11, lr}103; CHECK-NEXT: push {r11, lr}104; CHECK-NEXT: ldr lr, [r0]105; CHECK-NEXT: vld1.8 {d16[], d17[]}, [lr]!106; CHECK-NEXT: str lr, [r0]107; CHECK-NEXT: vmov r12, r1, d16108; CHECK-NEXT: vmov r2, r3, d17109; CHECK-NEXT: mov r0, r12110; CHECK-NEXT: pop {r11, lr}111; CHECK-NEXT: mov pc, lr112entry:113 %0 = load ptr, ptr %a, align 4114 %1 = load i8, ptr %0, align 1115 %2 = insertelement <16 x i8> undef, i8 %1, i32 0116 %lane = shufflevector <16 x i8> %2, <16 x i8> undef, <16 x i32> zeroinitializer117 %add.ptr = getelementptr inbounds i8, ptr %0, i32 1118 store ptr %add.ptr, ptr %a, align 4119 ret <16 x i8> %lane120}121 122define <16 x i8> @vld1dupqi8_postinc_register(ptr noalias nocapture %a, i32 %n) nounwind {123; CHECK-LABEL: vld1dupqi8_postinc_register:124; CHECK: @ %bb.0: @ %entry125; CHECK-NEXT: .save {r11, lr}126; CHECK-NEXT: push {r11, lr}127; CHECK-NEXT: ldr lr, [r0]128; CHECK-NEXT: vld1.8 {d16[], d17[]}, [lr], r1129; CHECK-NEXT: str lr, [r0]130; CHECK-NEXT: vmov r12, r1, d16131; CHECK-NEXT: vmov r2, r3, d17132; CHECK-NEXT: mov r0, r12133; CHECK-NEXT: pop {r11, lr}134; CHECK-NEXT: mov pc, lr135entry:136 %0 = load ptr, ptr %a, align 4137 %1 = load i8, ptr %0, align 1138 %2 = insertelement <16 x i8> undef, i8 %1, i32 0139 %lane = shufflevector <16 x i8> %2, <16 x i8> undef, <16 x i32> zeroinitializer140 %add.ptr = getelementptr inbounds i8, ptr %0, i32 %n141 store ptr %add.ptr, ptr %a, align 4142 ret <16 x i8> %lane143}144 145define <4 x i16> @vld1dupi16(ptr %A) nounwind {146; CHECK-LABEL: vld1dupi16:147; CHECK: @ %bb.0:148; CHECK-NEXT: vld1.16 {d16[]}, [r0:16]149; CHECK-NEXT: vmov r0, r1, d16150; CHECK-NEXT: mov pc, lr151;Check the alignment value. Max for this instruction is 16 bits:152 %tmp1 = load i16, ptr %A, align 8153 %tmp2 = insertelement <4 x i16> undef, i16 %tmp1, i32 0154 %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> undef, <4 x i32> zeroinitializer155 ret <4 x i16> %tmp3156}157 158define <4 x i16> @vld1dupi16_misaligned(ptr %A) nounwind {159; CHECK-LABEL: vld1dupi16_misaligned:160; CHECK: @ %bb.0:161; CHECK-NEXT: vld1.16 {d16[]}, [r0]162; CHECK-NEXT: vmov r0, r1, d16163; CHECK-NEXT: mov pc, lr164 %tmp1 = load i16, ptr %A, align 1165 %tmp2 = insertelement <4 x i16> undef, i16 %tmp1, i32 0166 %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> undef, <4 x i32> zeroinitializer167 ret <4 x i16> %tmp3168}169 170; This sort of looks like a vld1dup, but there's an extension in the way.171define <4 x i16> @load_i16_dup_zext(ptr %A) nounwind {172; CHECK-LABEL: load_i16_dup_zext:173; CHECK: @ %bb.0:174; CHECK-NEXT: ldrb r0, [r0]175; CHECK-NEXT: vdup.16 d16, r0176; CHECK-NEXT: vmov r0, r1, d16177; CHECK-NEXT: mov pc, lr178 %tmp1 = load i8, ptr %A, align 1179 %tmp2 = zext i8 %tmp1 to i16180 %tmp3 = insertelement <4 x i16> undef, i16 %tmp2, i32 0181 %tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer182 ret <4 x i16> %tmp4183}184 185; This sort of looks like a vld1dup, but there's an extension in the way.186define <4 x i16> @load_i16_dup_sext(ptr %A) nounwind {187; CHECK-LABEL: load_i16_dup_sext:188; CHECK: @ %bb.0:189; CHECK-NEXT: ldrsb r0, [r0]190; CHECK-NEXT: vdup.16 d16, r0191; CHECK-NEXT: vmov r0, r1, d16192; CHECK-NEXT: mov pc, lr193 %tmp1 = load i8, ptr %A, align 1194 %tmp2 = sext i8 %tmp1 to i16195 %tmp3 = insertelement <4 x i16> undef, i16 %tmp2, i32 0196 %tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer197 ret <4 x i16> %tmp4198}199 200; This sort of looks like a vld1dup, but there's an extension in the way.201define <8 x i16> @load_i16_dupq_zext(ptr %A) nounwind {202; CHECK-LABEL: load_i16_dupq_zext:203; CHECK: @ %bb.0:204; CHECK-NEXT: ldrb r0, [r0]205; CHECK-NEXT: vdup.16 q8, r0206; CHECK-NEXT: vmov r0, r1, d16207; CHECK-NEXT: vmov r2, r3, d17208; CHECK-NEXT: mov pc, lr209 %tmp1 = load i8, ptr %A, align 1210 %tmp2 = zext i8 %tmp1 to i16211 %tmp3 = insertelement <8 x i16> undef, i16 %tmp2, i32 0212 %tmp4 = shufflevector <8 x i16> %tmp3, <8 x i16> undef, <8 x i32> zeroinitializer213 ret <8 x i16> %tmp4214}215 216define <2 x i32> @vld1dupi32(ptr %A) nounwind {217; CHECK-LABEL: vld1dupi32:218; CHECK: @ %bb.0:219; CHECK-NEXT: vld1.32 {d16[]}, [r0:32]220; CHECK-NEXT: vmov r0, r1, d16221; CHECK-NEXT: mov pc, lr222;Check the alignment value. Max for this instruction is 32 bits:223 %tmp1 = load i32, ptr %A, align 8224 %tmp2 = insertelement <2 x i32> undef, i32 %tmp1, i32 0225 %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> undef, <2 x i32> zeroinitializer226 ret <2 x i32> %tmp3227}228 229; This sort of looks like a vld1dup, but there's an extension in the way.230define <4 x i32> @load_i32_dup_zext(ptr %A) nounwind {231; CHECK-LABEL: load_i32_dup_zext:232; CHECK: @ %bb.0:233; CHECK-NEXT: ldrb r0, [r0]234; CHECK-NEXT: vdup.32 q8, r0235; CHECK-NEXT: vmov r0, r1, d16236; CHECK-NEXT: vmov r2, r3, d17237; CHECK-NEXT: mov pc, lr238 %tmp1 = load i8, ptr %A, align 1239 %tmp2 = zext i8 %tmp1 to i32240 %tmp3 = insertelement <4 x i32> undef, i32 %tmp2, i32 0241 %tmp4 = shufflevector <4 x i32> %tmp3, <4 x i32> undef, <4 x i32> zeroinitializer242 ret <4 x i32> %tmp4243}244 245; This sort of looks like a vld1dup, but there's an extension in the way.246define <4 x i32> @load_i32_dup_sext(ptr %A) nounwind {247; CHECK-LABEL: load_i32_dup_sext:248; CHECK: @ %bb.0:249; CHECK-NEXT: ldrsb r0, [r0]250; CHECK-NEXT: vdup.32 q8, r0251; CHECK-NEXT: vmov r0, r1, d16252; CHECK-NEXT: vmov r2, r3, d17253; CHECK-NEXT: mov pc, lr254 %tmp1 = load i8, ptr %A, align 1255 %tmp2 = sext i8 %tmp1 to i32256 %tmp3 = insertelement <4 x i32> undef, i32 %tmp2, i32 0257 %tmp4 = shufflevector <4 x i32> %tmp3, <4 x i32> undef, <4 x i32> zeroinitializer258 ret <4 x i32> %tmp4259}260 261define <2 x float> @vld1dupf(ptr %A) nounwind {262; CHECK-LABEL: vld1dupf:263; CHECK: @ %bb.0:264; CHECK-NEXT: vld1.32 {d16[]}, [r0:32]265; CHECK-NEXT: vmov r0, r1, d16266; CHECK-NEXT: mov pc, lr267 %tmp0 = load float, ptr %A268 %tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0269 %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer270 ret <2 x float> %tmp2271}272 273define <16 x i8> @vld1dupQi8(ptr %A) nounwind {274; CHECK-LABEL: vld1dupQi8:275; CHECK: @ %bb.0:276; CHECK-NEXT: vld1.8 {d16[], d17[]}, [r0]277; CHECK-NEXT: vmov r0, r1, d16278; CHECK-NEXT: vmov r2, r3, d17279; CHECK-NEXT: mov pc, lr280;Check the (default) alignment value.281 %tmp1 = load i8, ptr %A, align 8282 %tmp2 = insertelement <16 x i8> undef, i8 %tmp1, i32 0283 %tmp3 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <16 x i32> zeroinitializer284 ret <16 x i8> %tmp3285}286 287define <4 x float> @vld1dupQf(ptr %A) nounwind {288; CHECK-LABEL: vld1dupQf:289; CHECK: @ %bb.0:290; CHECK-NEXT: vld1.32 {d16[], d17[]}, [r0:32]291; CHECK-NEXT: vmov r0, r1, d16292; CHECK-NEXT: vmov r2, r3, d17293; CHECK-NEXT: mov pc, lr294 %tmp0 = load float, ptr %A295 %tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0296 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer297 ret <4 x float> %tmp2298}299 300%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }301%struct.__neon_int4x16x2_t = type { <4 x i16>, <4 x i16> }302%struct.__neon_int2x32x2_t = type { <2 x i32>, <2 x i32> }303 304define <8 x i8> @vld2dupi8(ptr %A) nounwind {305; CHECK-LABEL: vld2dupi8:306; CHECK: @ %bb.0:307; CHECK-NEXT: vld2.8 {d16[0], d17[0]}, [r0]308; CHECK-NEXT: vadd.i8 d16, d16, d17309; CHECK-NEXT: vdup.8 d16, d16[0]310; CHECK-NEXT: vmov r0, r1, d16311; CHECK-NEXT: mov pc, lr312;Check the (default) alignment value.313 %tmp0 = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr %A, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)314 %tmp1 = extractvalue %struct.__neon_int8x8x2_t %tmp0, 0315 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer316 %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp0, 1317 %tmp4 = shufflevector <8 x i8> %tmp3, <8 x i8> undef, <8 x i32> zeroinitializer318 %tmp5 = add <8 x i8> %tmp2, %tmp4319 ret <8 x i8> %tmp5320}321 322define void @vld2dupi8_preinc(ptr noalias nocapture sret(%struct.__neon_int8x8x2_t) %agg.result, ptr noalias nocapture %a, i32 %b) nounwind {323; CHECK-LABEL: vld2dupi8_preinc:324; CHECK: @ %bb.0: @ %entry325; CHECK-NEXT: ldr r3, [r1]326; CHECK-NEXT: add r2, r3, r2327; CHECK-NEXT: str r2, [r1]328; CHECK-NEXT: vld2.8 {d16[], d17[]}, [r2]329; CHECK-NEXT: vst1.8 {d16}, [r0:64]!330; CHECK-NEXT: vstr d17, [r0]331; CHECK-NEXT: mov pc, lr332entry:333 %0 = load ptr, ptr %a, align 4334 %add.ptr = getelementptr inbounds i8, ptr %0, i32 %b335 %vld_dup = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr %add.ptr, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)336 %1 = extractvalue %struct.__neon_int8x8x2_t %vld_dup, 0337 %lane = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer338 %2 = extractvalue %struct.__neon_int8x8x2_t %vld_dup, 1339 %lane1 = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer340 store ptr %add.ptr, ptr %a, align 4341 store <8 x i8> %lane, ptr %agg.result, align 8342 %r11 = getelementptr inbounds %struct.__neon_int8x8x2_t, ptr %agg.result, i32 0, i32 1343 store <8 x i8> %lane1, ptr %r11, align 8344 ret void345}346 347define void @vld2dupi8_postinc_fixed(ptr noalias nocapture sret(%struct.__neon_int8x8x2_t) %agg.result, ptr noalias nocapture %a) nounwind {348; CHECK-LABEL: vld2dupi8_postinc_fixed:349; CHECK: @ %bb.0: @ %entry350; CHECK-NEXT: ldr r2, [r1]351; CHECK-NEXT: vld2.8 {d16[], d17[]}, [r2]!352; CHECK-NEXT: str r2, [r1]353; CHECK-NEXT: vst1.8 {d16}, [r0:64]!354; CHECK-NEXT: vstr d17, [r0]355; CHECK-NEXT: mov pc, lr356entry:357 %0 = load ptr, ptr %a, align 4358 %vld_dup = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr %0, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)359 %1 = extractvalue %struct.__neon_int8x8x2_t %vld_dup, 0360 %lane = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer361 %2 = extractvalue %struct.__neon_int8x8x2_t %vld_dup, 1362 %lane1 = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer363 %add.ptr = getelementptr inbounds i8, ptr %0, i32 2364 store ptr %add.ptr, ptr %a, align 4365 store <8 x i8> %lane, ptr %agg.result, align 8366 %r10 = getelementptr inbounds %struct.__neon_int8x8x2_t, ptr %agg.result, i32 0, i32 1367 store <8 x i8> %lane1, ptr %r10, align 8368 ret void369}370 371define void @vld2dupi8_postinc_variable(ptr noalias nocapture sret(%struct.__neon_int8x8x2_t) %agg.result, ptr noalias nocapture %a, i32 %n) nounwind {372; CHECK-LABEL: vld2dupi8_postinc_variable:373; CHECK: @ %bb.0: @ %entry374; CHECK-NEXT: ldr r3, [r1]375; CHECK-NEXT: vld2.8 {d16[], d17[]}, [r3], r2376; CHECK-NEXT: str r3, [r1]377; CHECK-NEXT: vst1.8 {d16}, [r0:64]!378; CHECK-NEXT: vstr d17, [r0]379; CHECK-NEXT: mov pc, lr380entry:381 %0 = load ptr, ptr %a, align 4382 %vld_dup = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr %0, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)383 %1 = extractvalue %struct.__neon_int8x8x2_t %vld_dup, 0384 %lane = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer385 %2 = extractvalue %struct.__neon_int8x8x2_t %vld_dup, 1386 %lane1 = shufflevector <8 x i8> %2, <8 x i8> undef, <8 x i32> zeroinitializer387 %add.ptr = getelementptr inbounds i8, ptr %0, i32 %n388 store ptr %add.ptr, ptr %a, align 4389 store <8 x i8> %lane, ptr %agg.result, align 8390 %r10 = getelementptr inbounds %struct.__neon_int8x8x2_t, ptr %agg.result, i32 0, i32 1391 store <8 x i8> %lane1, ptr %r10, align 8392 ret void393}394 395define <4 x i16> @vld2dupi16(ptr %A) nounwind {396; CHECK-LABEL: vld2dupi16:397; CHECK: @ %bb.0:398; CHECK-NEXT: vld2.16 {d16[0], d17[0]}, [r0]399; CHECK-NEXT: vadd.i16 d16, d16, d17400; CHECK-NEXT: vdup.16 d16, d16[0]401; CHECK-NEXT: vmov r0, r1, d16402; CHECK-NEXT: mov pc, lr403;Check that a power-of-two alignment smaller than the total size of the memory404;being loaded is ignored.405 %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0(ptr %A, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2)406 %tmp1 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 0407 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer408 %tmp3 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 1409 %tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer410 %tmp5 = add <4 x i16> %tmp2, %tmp4411 ret <4 x i16> %tmp5412}413 414;Check for a post-increment updating load.415define <4 x i16> @vld2dupi16_update(ptr %ptr) nounwind {416; CHECK-LABEL: vld2dupi16_update:417; CHECK: @ %bb.0:418; CHECK-NEXT: ldr r3, [r0]419; CHECK-NEXT: vld2.16 {d16[0], d17[0]}, [r3]!420; CHECK-NEXT: vadd.i16 d16, d16, d17421; CHECK-NEXT: str r3, [r0]422; CHECK-NEXT: vdup.16 d16, d16[0]423; CHECK-NEXT: vmov r2, r1, d16424; CHECK-NEXT: mov r0, r2425; CHECK-NEXT: mov pc, lr426 %A = load ptr, ptr %ptr427 %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0(ptr %A, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2)428 %tmp1 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 0429 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer430 %tmp3 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 1431 %tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer432 %tmp5 = add <4 x i16> %tmp2, %tmp4433 %tmp6 = getelementptr i16, ptr %A, i32 2434 store ptr %tmp6, ptr %ptr435 ret <4 x i16> %tmp5436}437 438define <4 x i16> @vld2dupi16_odd_update(ptr %ptr) nounwind {439; CHECK-LABEL: vld2dupi16_odd_update:440; CHECK: @ %bb.0:441; CHECK-NEXT: ldr r3, [r0]442; CHECK-NEXT: mov r1, #6443; CHECK-NEXT: vld2.16 {d16[0], d17[0]}, [r3], r1444; CHECK-NEXT: vadd.i16 d16, d16, d17445; CHECK-NEXT: str r3, [r0]446; CHECK-NEXT: vdup.16 d16, d16[0]447; CHECK-NEXT: vmov r2, r1, d16448; CHECK-NEXT: mov r0, r2449; CHECK-NEXT: mov pc, lr450 %A = load ptr, ptr %ptr451 %tmp0 = tail call %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0(ptr %A, <4 x i16> undef, <4 x i16> undef, i32 0, i32 2)452 %tmp1 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 0453 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer454 %tmp3 = extractvalue %struct.__neon_int4x16x2_t %tmp0, 1455 %tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer456 %tmp5 = add <4 x i16> %tmp2, %tmp4457 %tmp6 = getelementptr i16, ptr %A, i32 3458 store ptr %tmp6, ptr %ptr459 ret <4 x i16> %tmp5460}461 462define <2 x i32> @vld2dupi32(ptr %A) nounwind {463; CHECK-LABEL: vld2dupi32:464; CHECK: @ %bb.0:465; CHECK-NEXT: vld2.32 {d16[0], d17[0]}, [r0:64]466; CHECK-NEXT: vadd.i32 d16, d16, d17467; CHECK-NEXT: vdup.32 d16, d16[0]468; CHECK-NEXT: vmov r0, r1, d16469; CHECK-NEXT: mov pc, lr470;Check the alignment value. Max for this instruction is 64 bits:471 %tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32.p0(ptr %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16)472 %tmp1 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 0473 %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer474 %tmp3 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 1475 %tmp4 = shufflevector <2 x i32> %tmp3, <2 x i32> undef, <2 x i32> zeroinitializer476 %tmp5 = add <2 x i32> %tmp2, %tmp4477 ret <2 x i32> %tmp5478}479 480declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8.p0(ptr, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly481declare %struct.__neon_int4x16x2_t @llvm.arm.neon.vld2lane.v4i16.p0(ptr, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly482declare %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32.p0(ptr, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly483 484%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }485%struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> }486 487;Check for a post-increment updating load with register increment.488define <8 x i8> @vld3dupi8_update(ptr %ptr, i32 %inc) nounwind {489; CHECK-LABEL: vld3dupi8_update:490; CHECK: @ %bb.0:491; CHECK-NEXT: ldr r3, [r0]492; CHECK-NEXT: vld3.8 {d16[0], d17[0], d18[0]}, [r3], r1493; CHECK-NEXT: vadd.i8 d20, d16, d17494; CHECK-NEXT: vadd.i8 d16, d20, d18495; CHECK-NEXT: str r3, [r0]496; CHECK-NEXT: vdup.8 d16, d16[0]497; CHECK-NEXT: vmov r2, r1, d16498; CHECK-NEXT: mov r0, r2499; CHECK-NEXT: mov pc, lr500 %A = load ptr, ptr %ptr501 %tmp0 = tail call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0(ptr %A, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 8)502 %tmp1 = extractvalue %struct.__neon_int8x8x3_t %tmp0, 0503 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer504 %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp0, 1505 %tmp4 = shufflevector <8 x i8> %tmp3, <8 x i8> undef, <8 x i32> zeroinitializer506 %tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp0, 2507 %tmp6 = shufflevector <8 x i8> %tmp5, <8 x i8> undef, <8 x i32> zeroinitializer508 %tmp7 = add <8 x i8> %tmp2, %tmp4509 %tmp8 = add <8 x i8> %tmp7, %tmp6510 %tmp9 = getelementptr i8, ptr %A, i32 %inc511 store ptr %tmp9, ptr %ptr512 ret <8 x i8> %tmp8513}514 515define <4 x i16> @vld3dupi16(ptr %A) nounwind {516; CHECK-LABEL: vld3dupi16:517; CHECK: @ %bb.0:518; CHECK-NEXT: vld3.16 {d16[0], d17[0], d18[0]}, [r0]519; CHECK-NEXT: vadd.i16 d20, d16, d17520; CHECK-NEXT: vadd.i16 d16, d20, d18521; CHECK-NEXT: vdup.16 d16, d16[0]522; CHECK-NEXT: vmov r0, r1, d16523; CHECK-NEXT: mov pc, lr524;Check the (default) alignment value. VLD3 does not support alignment.525 %tmp0 = tail call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0(ptr %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 8)526 %tmp1 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 0527 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer528 %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 1529 %tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer530 %tmp5 = extractvalue %struct.__neon_int16x4x3_t %tmp0, 2531 %tmp6 = shufflevector <4 x i16> %tmp5, <4 x i16> undef, <4 x i32> zeroinitializer532 %tmp7 = add <4 x i16> %tmp2, %tmp4533 %tmp8 = add <4 x i16> %tmp7, %tmp6534 ret <4 x i16> %tmp8535}536 537declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8.p0(ptr, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind readonly538declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16.p0(ptr, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly539 540%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }541%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }542 543;Check for a post-increment updating load.544define <4 x i16> @vld4dupi16_update(ptr %ptr) nounwind {545; CHECK-LABEL: vld4dupi16_update:546; CHECK: @ %bb.0:547; CHECK-NEXT: ldr r3, [r0]548; CHECK-NEXT: vld4.16 {d16[0], d17[0], d18[0], d19[0]}, [r3]!549; CHECK-NEXT: vadd.i16 d16, d16, d17550; CHECK-NEXT: vadd.i16 d20, d18, d19551; CHECK-NEXT: str r3, [r0]552; CHECK-NEXT: vadd.i16 d16, d16, d20553; CHECK-NEXT: vdup.16 d16, d16[0]554; CHECK-NEXT: vmov r2, r1, d16555; CHECK-NEXT: mov r0, r2556; CHECK-NEXT: mov pc, lr557 %A = load ptr, ptr %ptr558 %tmp0 = tail call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16.p0(ptr %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 1)559 %tmp1 = extractvalue %struct.__neon_int16x4x4_t %tmp0, 0560 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer561 %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp0, 1562 %tmp4 = shufflevector <4 x i16> %tmp3, <4 x i16> undef, <4 x i32> zeroinitializer563 %tmp5 = extractvalue %struct.__neon_int16x4x4_t %tmp0, 2564 %tmp6 = shufflevector <4 x i16> %tmp5, <4 x i16> undef, <4 x i32> zeroinitializer565 %tmp7 = extractvalue %struct.__neon_int16x4x4_t %tmp0, 3566 %tmp8 = shufflevector <4 x i16> %tmp7, <4 x i16> undef, <4 x i32> zeroinitializer567 %tmp9 = add <4 x i16> %tmp2, %tmp4568 %tmp10 = add <4 x i16> %tmp6, %tmp8569 %tmp11 = add <4 x i16> %tmp9, %tmp10570 %tmp12 = getelementptr i16, ptr %A, i32 4571 store ptr %tmp12, ptr %ptr572 ret <4 x i16> %tmp11573}574 575define <2 x i32> @vld4dupi32(ptr %A) nounwind {576; CHECK-LABEL: vld4dupi32:577; CHECK: @ %bb.0:578; CHECK-NEXT: vld4.32 {d16[0], d17[0], d18[0], d19[0]}, [r0:64]579; CHECK-NEXT: vadd.i32 d16, d16, d17580; CHECK-NEXT: vadd.i32 d20, d18, d19581; CHECK-NEXT: vadd.i32 d16, d16, d20582; CHECK-NEXT: vdup.32 d16, d16[0]583; CHECK-NEXT: vmov r0, r1, d16584; CHECK-NEXT: mov pc, lr585;Check the alignment value. An 8-byte alignment is allowed here even though586;it is smaller than the total size of the memory being loaded.587 %tmp0 = tail call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32.p0(ptr %A, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 8)588 %tmp1 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 0589 %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer590 %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 1591 %tmp4 = shufflevector <2 x i32> %tmp3, <2 x i32> undef, <2 x i32> zeroinitializer592 %tmp5 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 2593 %tmp6 = shufflevector <2 x i32> %tmp5, <2 x i32> undef, <2 x i32> zeroinitializer594 %tmp7 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 3595 %tmp8 = shufflevector <2 x i32> %tmp7, <2 x i32> undef, <2 x i32> zeroinitializer596 %tmp9 = add <2 x i32> %tmp2, %tmp4597 %tmp10 = add <2 x i32> %tmp6, %tmp8598 %tmp11 = add <2 x i32> %tmp9, %tmp10599 ret <2 x i32> %tmp11600}601 602declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16.p0(ptr, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly603declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32.p0(ptr, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly604