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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -run-pass arm-ldst-opt -verify-machineinstrs %s -o - | FileCheck %s3# ARM load store optimizer was dealing with a sequence like:4# s1 = VLDRS [r0, 1], implicit-def Q05# s3 = VLDRS [r0, 2], implicit killed Q0, implicit-def Q06# s0 = VLDRS [r0, 0], implicit killed Q0, implicit-def Q07# s2 = VLDRS [r0, 4], implicit killed Q0, implicit-def Q08#9# It decided to combine the {s0, s1} loads into a single instruction in the10# third position. However, this leaves the instruction defining s3 with a stray11# imp-use of Q0, which is undefined.12#13# The verifier catches this, so this test just makes sure that appropriate14# liveness flags are added.15--- |16 target triple = "thumbv7-apple-ios"17 define arm_aapcs_vfpcc <4 x float> @foo(ptr %ptr) {18 ret <4 x float> undef19 }20...21---22name: foo23alignment: 224liveins:25 - { reg: '$r0' }26body: |27 bb.0 (%ir-block.0):28 liveins: $r029 30 ; CHECK-LABEL: name: foo31 ; CHECK: $s3 = VLDRS $r0, 2, 14 /* CC::al */, $noreg, implicit killed undef $q0, implicit-def $q0 :: (load (s32))32 ; CHECK: VLDMSIA $r0, 14 /* CC::al */, $noreg, def $s0, def $s1, implicit-def $noreg :: (load (s32))33 ; CHECK: $s2 = VLDRS killed $r0, 4, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s32))34 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q035 $s1 = VLDRS $r0, 1, 14, $noreg, implicit-def $q0 :: (load (s32))36 $s3 = VLDRS $r0, 2, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s32))37 38 $s0 = VLDRS $r0, 0, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s32))39 40 $s2 = VLDRS killed $r0, 4, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s32))41 42 tBX_RET 14, $noreg, implicit $q043...44