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1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3define <8 x i8> @vmins8(ptr %A, ptr %B) nounwind {4;CHECK-LABEL: vmins8:5;CHECK: vmin.s86 %tmp1 = load <8 x i8>, ptr %A7 %tmp2 = load <8 x i8>, ptr %B8 %tmp3 = call <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)9 ret <8 x i8> %tmp310}11 12define <4 x i16> @vmins16(ptr %A, ptr %B) nounwind {13;CHECK-LABEL: vmins16:14;CHECK: vmin.s1615 %tmp1 = load <4 x i16>, ptr %A16 %tmp2 = load <4 x i16>, ptr %B17 %tmp3 = call <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)18 ret <4 x i16> %tmp319}20 21define <2 x i32> @vmins32(ptr %A, ptr %B) nounwind {22;CHECK-LABEL: vmins32:23;CHECK: vmin.s3224 %tmp1 = load <2 x i32>, ptr %A25 %tmp2 = load <2 x i32>, ptr %B26 %tmp3 = call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)27 ret <2 x i32> %tmp328}29 30define <8 x i8> @vminu8(ptr %A, ptr %B) nounwind {31;CHECK-LABEL: vminu8:32;CHECK: vmin.u833 %tmp1 = load <8 x i8>, ptr %A34 %tmp2 = load <8 x i8>, ptr %B35 %tmp3 = call <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)36 ret <8 x i8> %tmp337}38 39define <4 x i16> @vminu16(ptr %A, ptr %B) nounwind {40;CHECK-LABEL: vminu16:41;CHECK: vmin.u1642 %tmp1 = load <4 x i16>, ptr %A43 %tmp2 = load <4 x i16>, ptr %B44 %tmp3 = call <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)45 ret <4 x i16> %tmp346}47 48define <2 x i32> @vminu32(ptr %A, ptr %B) nounwind {49;CHECK-LABEL: vminu32:50;CHECK: vmin.u3251 %tmp1 = load <2 x i32>, ptr %A52 %tmp2 = load <2 x i32>, ptr %B53 %tmp3 = call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)54 ret <2 x i32> %tmp355}56 57define <2 x float> @vminf32(ptr %A, ptr %B) nounwind {58;CHECK-LABEL: vminf32:59;CHECK: vmin.f3260 %tmp1 = load <2 x float>, ptr %A61 %tmp2 = load <2 x float>, ptr %B62 %tmp3 = call <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)63 ret <2 x float> %tmp364}65 66define <16 x i8> @vminQs8(ptr %A, ptr %B) nounwind {67;CHECK-LABEL: vminQs8:68;CHECK: vmin.s869 %tmp1 = load <16 x i8>, ptr %A70 %tmp2 = load <16 x i8>, ptr %B71 %tmp3 = call <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)72 ret <16 x i8> %tmp373}74 75define <8 x i16> @vminQs16(ptr %A, ptr %B) nounwind {76;CHECK-LABEL: vminQs16:77;CHECK: vmin.s1678 %tmp1 = load <8 x i16>, ptr %A79 %tmp2 = load <8 x i16>, ptr %B80 %tmp3 = call <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)81 ret <8 x i16> %tmp382}83 84define <4 x i32> @vminQs32(ptr %A, ptr %B) nounwind {85;CHECK-LABEL: vminQs32:86;CHECK: vmin.s3287 %tmp1 = load <4 x i32>, ptr %A88 %tmp2 = load <4 x i32>, ptr %B89 %tmp3 = call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)90 ret <4 x i32> %tmp391}92 93define <16 x i8> @vminQu8(ptr %A, ptr %B) nounwind {94;CHECK-LABEL: vminQu8:95;CHECK: vmin.u896 %tmp1 = load <16 x i8>, ptr %A97 %tmp2 = load <16 x i8>, ptr %B98 %tmp3 = call <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)99 ret <16 x i8> %tmp3100}101 102define <8 x i16> @vminQu16(ptr %A, ptr %B) nounwind {103;CHECK-LABEL: vminQu16:104;CHECK: vmin.u16105 %tmp1 = load <8 x i16>, ptr %A106 %tmp2 = load <8 x i16>, ptr %B107 %tmp3 = call <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)108 ret <8 x i16> %tmp3109}110 111define <4 x i32> @vminQu32(ptr %A, ptr %B) nounwind {112;CHECK-LABEL: vminQu32:113;CHECK: vmin.u32114 %tmp1 = load <4 x i32>, ptr %A115 %tmp2 = load <4 x i32>, ptr %B116 %tmp3 = call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)117 ret <4 x i32> %tmp3118}119 120define <4 x float> @vminQf32(ptr %A, ptr %B) nounwind {121;CHECK-LABEL: vminQf32:122;CHECK: vmin.f32123 %tmp1 = load <4 x float>, ptr %A124 %tmp2 = load <4 x float>, ptr %B125 %tmp3 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)126 ret <4 x float> %tmp3127}128 129declare <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8>, <8 x i8>) nounwind readnone130declare <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16>, <4 x i16>) nounwind readnone131declare <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone132 133declare <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone134declare <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone135declare <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone136 137declare <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float>, <2 x float>) nounwind readnone138 139declare <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8>, <16 x i8>) nounwind readnone140declare <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16>, <8 x i16>) nounwind readnone141declare <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32>, <4 x i32>) nounwind readnone142 143declare <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone144declare <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone145declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone146 147declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone148 149define <8 x i8> @vmaxs8(ptr %A, ptr %B) nounwind {150;CHECK-LABEL: vmaxs8:151;CHECK: vmax.s8152 %tmp1 = load <8 x i8>, ptr %A153 %tmp2 = load <8 x i8>, ptr %B154 %tmp3 = call <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)155 ret <8 x i8> %tmp3156}157 158define <4 x i16> @vmaxs16(ptr %A, ptr %B) nounwind {159;CHECK-LABEL: vmaxs16:160;CHECK: vmax.s16161 %tmp1 = load <4 x i16>, ptr %A162 %tmp2 = load <4 x i16>, ptr %B163 %tmp3 = call <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)164 ret <4 x i16> %tmp3165}166 167define <2 x i32> @vmaxs32(ptr %A, ptr %B) nounwind {168;CHECK-LABEL: vmaxs32:169;CHECK: vmax.s32170 %tmp1 = load <2 x i32>, ptr %A171 %tmp2 = load <2 x i32>, ptr %B172 %tmp3 = call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)173 ret <2 x i32> %tmp3174}175 176define <8 x i8> @vmaxu8(ptr %A, ptr %B) nounwind {177;CHECK-LABEL: vmaxu8:178;CHECK: vmax.u8179 %tmp1 = load <8 x i8>, ptr %A180 %tmp2 = load <8 x i8>, ptr %B181 %tmp3 = call <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)182 ret <8 x i8> %tmp3183}184 185define <4 x i16> @vmaxu16(ptr %A, ptr %B) nounwind {186;CHECK-LABEL: vmaxu16:187;CHECK: vmax.u16188 %tmp1 = load <4 x i16>, ptr %A189 %tmp2 = load <4 x i16>, ptr %B190 %tmp3 = call <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)191 ret <4 x i16> %tmp3192}193 194define <2 x i32> @vmaxu32(ptr %A, ptr %B) nounwind {195;CHECK-LABEL: vmaxu32:196;CHECK: vmax.u32197 %tmp1 = load <2 x i32>, ptr %A198 %tmp2 = load <2 x i32>, ptr %B199 %tmp3 = call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)200 ret <2 x i32> %tmp3201}202 203define <2 x float> @vmaxf32(ptr %A, ptr %B) nounwind {204;CHECK-LABEL: vmaxf32:205;CHECK: vmax.f32206 %tmp1 = load <2 x float>, ptr %A207 %tmp2 = load <2 x float>, ptr %B208 %tmp3 = call <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)209 ret <2 x float> %tmp3210}211 212define <16 x i8> @vmaxQs8(ptr %A, ptr %B) nounwind {213;CHECK-LABEL: vmaxQs8:214;CHECK: vmax.s8215 %tmp1 = load <16 x i8>, ptr %A216 %tmp2 = load <16 x i8>, ptr %B217 %tmp3 = call <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)218 ret <16 x i8> %tmp3219}220 221define <8 x i16> @vmaxQs16(ptr %A, ptr %B) nounwind {222;CHECK-LABEL: vmaxQs16:223;CHECK: vmax.s16224 %tmp1 = load <8 x i16>, ptr %A225 %tmp2 = load <8 x i16>, ptr %B226 %tmp3 = call <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)227 ret <8 x i16> %tmp3228}229 230define <4 x i32> @vmaxQs32(ptr %A, ptr %B) nounwind {231;CHECK-LABEL: vmaxQs32:232;CHECK: vmax.s32233 %tmp1 = load <4 x i32>, ptr %A234 %tmp2 = load <4 x i32>, ptr %B235 %tmp3 = call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)236 ret <4 x i32> %tmp3237}238 239define <16 x i8> @vmaxQu8(ptr %A, ptr %B) nounwind {240;CHECK-LABEL: vmaxQu8:241;CHECK: vmax.u8242 %tmp1 = load <16 x i8>, ptr %A243 %tmp2 = load <16 x i8>, ptr %B244 %tmp3 = call <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)245 ret <16 x i8> %tmp3246}247 248define <8 x i16> @vmaxQu16(ptr %A, ptr %B) nounwind {249;CHECK-LABEL: vmaxQu16:250;CHECK: vmax.u16251 %tmp1 = load <8 x i16>, ptr %A252 %tmp2 = load <8 x i16>, ptr %B253 %tmp3 = call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)254 ret <8 x i16> %tmp3255}256 257define <4 x i32> @vmaxQu32(ptr %A, ptr %B) nounwind {258;CHECK-LABEL: vmaxQu32:259;CHECK: vmax.u32260 %tmp1 = load <4 x i32>, ptr %A261 %tmp2 = load <4 x i32>, ptr %B262 %tmp3 = call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)263 ret <4 x i32> %tmp3264}265 266define <4 x float> @vmaxQf32(ptr %A, ptr %B) nounwind {267;CHECK-LABEL: vmaxQf32:268;CHECK: vmax.f32269 %tmp1 = load <4 x float>, ptr %A270 %tmp2 = load <4 x float>, ptr %B271 %tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)272 ret <4 x float> %tmp3273}274 275declare <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone276declare <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone277declare <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone278 279declare <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone280declare <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone281declare <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone282 283declare <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float>, <2 x float>) nounwind readnone284 285declare <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone286declare <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone287declare <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone288 289declare <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone290declare <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone291declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone292 293declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone294 295declare float @llvm.maxnum.f32(float %a, float %b)296declare float @llvm.minnum.f32(float %a, float %b)297 298define float @maxnum(float %a, float %b) {299;CHECK-LABEL: maxnum:300;CHECK: vcmp.f32301;CHECK-NEXT: vmrs302;CHECK-NEXT: vmovgt.f32303 %r = call nnan float @llvm.maxnum.f32(float %a, float %b)304 ret float %r305}306 307define float @minnum(float %a, float %b) {308;CHECK-LABEL: minnum:309;CHECK: vcmp.f32310;CHECK-NEXT: vmrs311;CHECK-NEXT: vmovlt.f32312 %r = call nnan float @llvm.minnum.f32(float %a, float %b)313 ret float %r314}315