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1; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 | FileCheck %s2 3; vectors4 5define <4 x float> @vmaxnmq(ptr %A, ptr %B) nounwind {6; CHECK-LABEL: vmaxnmq:7; CHECK: vmaxnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}8 %tmp1 = load <4 x float>, ptr %A9 %tmp2 = load <4 x float>, ptr %B10 %tmp3 = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)11 ret <4 x float> %tmp312}13 14define <2 x float> @vmaxnmd(ptr %A, ptr %B) nounwind {15; CHECK-LABEL: vmaxnmd:16; CHECK: vmaxnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}17 %tmp1 = load <2 x float>, ptr %A18 %tmp2 = load <2 x float>, ptr %B19 %tmp3 = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)20 ret <2 x float> %tmp321}22 23define <4 x float> @vminnmq(ptr %A, ptr %B) nounwind {24; CHECK-LABEL: vminnmq:25; CHECK: vminnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}26 %tmp1 = load <4 x float>, ptr %A27 %tmp2 = load <4 x float>, ptr %B28 %tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)29 ret <4 x float> %tmp330}31 32define <2 x float> @vminnmd(ptr %A, ptr %B) nounwind {33; CHECK-LABEL: vminnmd:34; CHECK: vminnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}35 %tmp1 = load <2 x float>, ptr %A36 %tmp2 = load <2 x float>, ptr %B37 %tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)38 ret <2 x float> %tmp339}40 41; scalars42 43define float @fp-armv8_vminnm_o(float %a, float %b) {44; CHECK-LABEL: "fp-armv8_vminnm_o":45; CHECK-NOT: vminnm.f3246 %cmp = fcmp olt float %a, %b47 %cond = select nsz i1 %cmp, float %a, float %b48 ret float %cond49}50 51define double @fp-armv8_vminnm_ole(double %a, double %b) {52; CHECK-LABEL: "fp-armv8_vminnm_ole":53; CHECK-NOT: vminnm.f6454 %cmp = fcmp ole double %a, %b55 %cond = select nsz i1 %cmp, double %a, double %b56 ret double %cond57}58 59define float @fp-armv8_vminnm_o_rev(float %a, float %b) {60; CHECK-LABEL: "fp-armv8_vminnm_o_rev":61; CHECK-NOT: vminnm.f3262 %cmp = fcmp ogt float %a, %b63 %cond = select nsz i1 %cmp, float %b, float %a64 ret float %cond65}66 67define double @fp-armv8_vminnm_oge_rev(double %a, double %b) {68; CHECK-LABEL: "fp-armv8_vminnm_oge_rev":69; CHECK-NOT: vminnm.f6470 %cmp = fcmp oge double %a, %b71 %cond = select nsz i1 %cmp, double %b, double %a72 ret double %cond73}74 75define float @fp-armv8_vminnm_u(float %a, float %b) {76; CHECK-LABEL: "fp-armv8_vminnm_u":77; CHECK-NOT: vminnm.f3278 %cmp = fcmp ult float %a, %b79 %cond = select nsz i1 %cmp, float %a, float %b80 ret float %cond81}82 83define float @fp-armv8_vminnm_ule(float %a, float %b) {84; CHECK-LABEL: "fp-armv8_vminnm_ule":85; CHECK-NOT: vminnm.f3286 %cmp = fcmp ule float %a, %b87 %cond = select nsz i1 %cmp, float %a, float %b88 ret float %cond89}90 91define float @fp-armv8_vminnm_u_rev(float %a, float %b) {92; CHECK-LABEL: "fp-armv8_vminnm_u_rev":93; CHECK-NOT: vminnm.f3294 %cmp = fcmp ugt float %a, %b95 %cond = select nsz i1 %cmp, float %b, float %a96 ret float %cond97}98 99define double @fp-armv8_vminnm_uge_rev(double %a, double %b) {100; CHECK-LABEL: "fp-armv8_vminnm_uge_rev":101; CHECK-NOT: vminnm.f64102 %cmp = fcmp uge double %a, %b103 %cond = select nsz i1 %cmp, double %b, double %a104 ret double %cond105}106 107define float @fp-armv8_vmaxnm_o(float %a, float %b) {108; CHECK-LABEL: "fp-armv8_vmaxnm_o":109; CHECK-NOT: vmaxnm.f32110 %cmp = fcmp ogt float %a, %b111 %cond = select nsz i1 %cmp, float %a, float %b112 ret float %cond113}114 115define float @fp-armv8_vmaxnm_oge(float %a, float %b) {116; CHECK-LABEL: "fp-armv8_vmaxnm_oge":117; CHECK-NOT: vmaxnm.f32118 %cmp = fcmp oge float %a, %b119 %cond = select nsz i1 %cmp, float %a, float %b120 ret float %cond121}122 123define float @fp-armv8_vmaxnm_o_rev(float %a, float %b) {124; CHECK-LABEL: "fp-armv8_vmaxnm_o_rev":125; CHECK-NOT: vmaxnm.f32126 %cmp = fcmp olt float %a, %b127 %cond = select nsz i1 %cmp, float %b, float %a128 ret float %cond129}130 131define float @fp-armv8_vmaxnm_ole_rev(float %a, float %b) {132; CHECK-LABEL: "fp-armv8_vmaxnm_ole_rev":133; CHECK-NOT: vmaxnm.f32134 %cmp = fcmp ole float %a, %b135 %cond = select nsz i1 %cmp, float %b, float %a136 ret float %cond137}138 139define float @fp-armv8_vmaxnm_u(float %a, float %b) {140; CHECK-LABEL: "fp-armv8_vmaxnm_u":141; CHECK-NOT: vmaxnm.f32142 %cmp = fcmp ugt float %a, %b143 %cond = select nsz i1 %cmp, float %a, float %b144 ret float %cond145}146 147define float @fp-armv8_vmaxnm_uge(float %a, float %b) {148; CHECK-LABEL: "fp-armv8_vmaxnm_uge":149; CHECK-NOT: vmaxnm.f32150 %cmp = fcmp uge float %a, %b151 %cond = select nsz i1 %cmp, float %a, float %b152 ret float %cond153}154 155define float @fp-armv8_vmaxnm_u_rev(float %a, float %b) {156; CHECK-LABEL: "fp-armv8_vmaxnm_u_rev":157; CHECK-NOT: vmaxnm.f32158 %cmp = fcmp ult float %a, %b159 %cond = select nsz i1 %cmp, float %b, float %a160 ret float %cond161}162 163define double @fp-armv8_vmaxnm_ule_rev(double %a, double %b) {164; CHECK-LABEL: "fp-armv8_vmaxnm_ule_rev":165; CHECK-NOT: vmaxnm.f64166 %cmp = fcmp ule double %a, %b167 %cond = select nsz i1 %cmp, double %b, double %a168 ret double %cond169}170 171; known non-NaNs172 173define float @fp-armv8_vminnm_NNNo(float %a) {174; CHECK-LABEL: "fp-armv8_vminnm_NNNo":175; CHECK: vminnm.f32176; CHECK-NOT: vminnm.f32177 %cmp1 = fcmp olt float %a, 12.178 %cond1 = select nsz i1 %cmp1, float %a, float 12.179 %cmp2 = fcmp olt float 34., %cond1180 %cond2 = select i1 %cmp2, float 34., float %cond1181 ret float %cond2182}183 184define double @fp-armv8_vminnm_NNNole(double %a) {185; CHECK-LABEL: "fp-armv8_vminnm_NNNole":186; CHECK: vminnm.f64187; CHECK-NOT: vminnm.f64188 %cmp1 = fcmp ole double %a, 34.189 %cond1 = select nsz i1 %cmp1, double %a, double 34.190 %cmp2 = fcmp ole double 56., %cond1191 %cond2 = select i1 %cmp2, double 56., double %cond1192 ret double %cond2193}194 195define float @fp-armv8_vminnm_NNNo_rev(float %a) {196; CHECK-LABEL: "fp-armv8_vminnm_NNNo_rev":197; CHECK: vminnm.f32198; CHECK-NOT: vminnm.f32199 %cmp1 = fcmp ogt float %a, 56.200 %cond1 = select nsz i1 %cmp1, float 56., float %a201 %cmp2 = fcmp ogt float 78., %cond1202 %cond2 = select nsz i1 %cmp2, float %cond1, float 78.203 ret float %cond2204}205 206define double @fp-armv8_vminnm_NNNoge_rev(double %a) {207; CHECK-LABEL: "fp-armv8_vminnm_NNNoge_rev":208; CHECK: vminnm.f64209; CHECK-NOT: vminnm.f64210 %cmp1 = fcmp oge double %a, 78.211 %cond1 = select nsz i1 %cmp1, double 78., double %a212 %cmp2 = fcmp oge double 90., %cond1213 %cond2 = select nsz i1 %cmp2, double %cond1, double 90.214 ret double %cond2215}216 217define float @fp-armv8_vminnm_NNNu(float %b) {218; CHECK-LABEL: "fp-armv8_vminnm_NNNu":219; CHECK: vminnm.f32220; CHECK-NOT: vminnm.f32221 %cmp1 = fcmp ult float 12., %b222 %cond1 = select nsz i1 %cmp1, float 12., float %b223 %cmp2 = fcmp ult float %cond1, 34.224 %cond2 = select i1 %cmp2, float %cond1, float 34.225 ret float %cond2226}227 228define float @fp-armv8_vminnm_NNNule(float %b) {229; CHECK-LABEL: "fp-armv8_vminnm_NNNule":230; CHECK: vminnm.f32231; CHECK-NOT: vminnm.f32232 %cmp1 = fcmp ule float 34., %b233 %cond1 = select nsz i1 %cmp1, float 34., float %b234 %cmp2 = fcmp ule float %cond1, 56.235 %cond2 = select i1 %cmp2, float %cond1, float 56.236 ret float %cond2237}238 239define float @fp-armv8_vminnm_NNNu_rev(float %b) {240; CHECK-LABEL: "fp-armv8_vminnm_NNNu_rev":241; CHECK: vminnm.f32242; CHECK-NOT: vminnm.f32243 %cmp1 = fcmp ugt float 56., %b244 %cond1 = select nsz i1 %cmp1, float %b, float 56.245 %cmp2 = fcmp ugt float %cond1, 78.246 %cond2 = select nsz i1 %cmp2, float 78., float %cond1247 ret float %cond2248}249 250define double @fp-armv8_vminnm_NNNuge_rev(double %b) {251; CHECK-LABEL: "fp-armv8_vminnm_NNNuge_rev":252; CHECK: vminnm.f64253; CHECK-NOT: vminnm.f64254 %cmp1 = fcmp uge double 78., %b255 %cond1 = select nsz i1 %cmp1, double %b, double 78.256 %cmp2 = fcmp uge double %cond1, 90.257 %cond2 = select nsz i1 %cmp2, double 90., double %cond1258 ret double %cond2259}260 261define float @fp-armv8_vmaxnm_NNNo(float %a) {262; CHECK-LABEL: "fp-armv8_vmaxnm_NNNo":263; CHECK: vmaxnm.f32264; CHECK-NOT: vmaxnm.f32265 %cmp1 = fcmp ogt float %a, 12.266 %cond1 = select nsz i1 %cmp1, float %a, float 12.267 %cmp2 = fcmp ogt float 34., %cond1268 %cond2 = select i1 %cmp2, float 34., float %cond1269 ret float %cond2270}271 272define float @fp-armv8_vmaxnm_NNNoge(float %a) {273; CHECK-LABEL: "fp-armv8_vmaxnm_NNNoge":274; CHECK: vmaxnm.f32275; CHECK-NOT: vmaxnm.f32276 %cmp1 = fcmp oge float %a, 34.277 %cond1 = select nsz i1 %cmp1, float %a, float 34.278 %cmp2 = fcmp oge float 56., %cond1279 %cond2 = select i1 %cmp2, float 56., float %cond1280 ret float %cond2281}282 283define float @fp-armv8_vmaxnm_NNNo_rev(float %a) {284; CHECK-LABEL: "fp-armv8_vmaxnm_NNNo_rev":285; CHECK: vmaxnm.f32286; CHECK-NOT: vmaxnm.f32287 %cmp1 = fcmp olt float %a, 56.288 %cond1 = select nsz i1 %cmp1, float 56., float %a289 %cmp2 = fcmp olt float 78., %cond1290 %cond2 = select nsz i1 %cmp2, float %cond1, float 78.291 ret float %cond2292}293 294define float @fp-armv8_vmaxnm_NNNole_rev(float %a) {295; CHECK-LABEL: "fp-armv8_vmaxnm_NNNole_rev":296; CHECK: vmaxnm.f32297; CHECK-NOT: vmaxnm.f32298 %cmp1 = fcmp ole float %a, 78.299 %cond1 = select nsz i1 %cmp1, float 78., float %a300 %cmp2 = fcmp ole float 90., %cond1301 %cond2 = select nsz i1 %cmp2, float %cond1, float 90.302 ret float %cond2303}304 305define float @fp-armv8_vmaxnm_NNNu(float %b) {306; CHECK-LABEL: "fp-armv8_vmaxnm_NNNu":307; CHECK: vmaxnm.f32308; CHECK-NOT: vmaxnm.f32309 %cmp1 = fcmp ugt float 12., %b310 %cond1 = select nsz i1 %cmp1, float 12., float %b311 %cmp2 = fcmp ugt float %cond1, 34.312 %cond2 = select i1 %cmp2, float %cond1, float 34.313 ret float %cond2314}315 316define float @fp-armv8_vmaxnm_NNNuge(float %b) {317; CHECK-LABEL: "fp-armv8_vmaxnm_NNNuge":318; CHECK: vmaxnm.f32319; CHECK-NOT: vmaxnm.f32320 %cmp1 = fcmp uge float 34., %b321 %cond1 = select nsz i1 %cmp1, float 34., float %b322 %cmp2 = fcmp uge float %cond1, 56.323 %cond2 = select i1 %cmp2, float %cond1, float 56.324 ret float %cond2325}326 327define float @fp-armv8_vmaxnm_NNNu_rev(float %b) {328; CHECK-LABEL: "fp-armv8_vmaxnm_NNNu_rev":329; CHECK: vmaxnm.f32330; CHECK-NOT: vmaxnm.f32331 %cmp1 = fcmp ult float 56., %b332 %cond1 = select nsz i1 %cmp1, float %b, float 56.333 %cmp2 = fcmp ult float %cond1, 78.334 %cond2 = select nsz i1 %cmp2, float 78., float %cond1335 ret float %cond2336}337 338define double @fp-armv8_vmaxnm_NNNule_rev( double %b) {339; CHECK-LABEL: "fp-armv8_vmaxnm_NNNule_rev":340; CHECK: vmaxnm.f64341; CHECK-NOT: vmaxnm.f64342 %cmp1 = fcmp ule double 78., %b343 %cond1 = select nsz i1 %cmp1, double %b, double 78.344 %cmp2 = fcmp ule double %cond1, 90.345 %cond2 = select nsz i1 %cmp2, double 90., double %cond1346 ret double %cond2347}348 349define float @fp-armv8_vminmaxnm_0(float %a) {350; CHECK-LABEL: "fp-armv8_vminmaxnm_0":351; CHECK-NOT: vminnm.f32352; CHECK: vmaxnm.f32353 %cmp1 = fcmp ult float %a, 0.354 %cond1 = select nsz i1 %cmp1, float %a, float 0.355 %cmp2 = fcmp ogt float %cond1, 0.356 %cond2 = select nsz i1 %cmp2, float %cond1, float 0.357 ret float %cond2358}359 360define float @fp-armv8_vminmaxnm_neg0(float %a) {361; CHECK-LABEL: "fp-armv8_vminmaxnm_neg0":362; CHECK: vminnm.f32363; CHECK-NOT: vmaxnm.f32364 %cmp1 = fcmp olt float %a, -0.365 %cond1 = select nsz i1 %cmp1, float %a, float -0.366 %cmp2 = fcmp ugt float %cond1, -0.367 %cond2 = select i1 %cmp2, float %cond1, float -0.368 ret float %cond2369}370 371define float @fp-armv8_vminmaxnm_e_0(float %a) {372; CHECK-LABEL: "fp-armv8_vminmaxnm_e_0":373; CHECK-NOT: vminnm.f32374; CHECK: vmaxnm.f32375 %cmp1 = fcmp nsz ole float 0., %a376 %cond1 = select nsz i1 %cmp1, float 0., float %a377 %cmp2 = fcmp nsz uge float 0., %cond1378 %cond2 = select nsz i1 %cmp2, float 0., float %cond1379 ret float %cond2380}381 382define float @fp-armv8_vminmaxnm_e_neg0(float %a) {383; CHECK-LABEL: "fp-armv8_vminmaxnm_e_neg0":384; CHECK: vminnm.f32385; CHECK-NOT: vmaxnm.f32386 %cmp1 = fcmp nsz ule float -0., %a387 %cond1 = select nsz i1 %cmp1, float -0., float %a388 %cmp2 = fcmp nsz oge float -0., %cond1389 %cond2 = select i1 %cmp2, float -0., float %cond1390 ret float %cond2391}392 393declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone394declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone395declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone396declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) nounwind readnone397