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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple armv8-none-eabihf -mattr=+neon,+fp-armv8 -enable-no-nans-fp-math | FileCheck %s3 4; scalars5 6define float @fparmv8_vminnm_o(float %a, float %b) {7; CHECK-LABEL: fparmv8_vminnm_o:8; CHECK: @ %bb.0:9; CHECK-NEXT: vminnm.f32 s0, s0, s110; CHECK-NEXT: bx lr11 %cmp = fcmp fast olt float %a, %b12 %cond = select nsz i1 %cmp, float %a, float %b13 ret float %cond14}15 16define double @fparmv8_vminnm_ole(double %a, double %b) {17; CHECK-LABEL: fparmv8_vminnm_ole:18; CHECK: @ %bb.0:19; CHECK-NEXT: vminnm.f64 d0, d0, d120; CHECK-NEXT: bx lr21 %cmp = fcmp fast ole double %a, %b22 %cond = select nsz i1 %cmp, double %a, double %b23 ret double %cond24}25 26define float @fparmv8_vminnm_o_rev(float %a, float %b) {27; CHECK-LABEL: fparmv8_vminnm_o_rev:28; CHECK: @ %bb.0:29; CHECK-NEXT: vminnm.f32 s0, s0, s130; CHECK-NEXT: bx lr31 %cmp = fcmp fast ogt float %a, %b32 %cond = select nsz i1 %cmp, float %b, float %a33 ret float %cond34}35 36define double @fparmv8_vminnm_oge_rev(double %a, double %b) {37; CHECK-LABEL: fparmv8_vminnm_oge_rev:38; CHECK: @ %bb.0:39; CHECK-NEXT: vminnm.f64 d0, d0, d140; CHECK-NEXT: bx lr41 %cmp = fcmp fast oge double %a, %b42 %cond = select nsz i1 %cmp, double %b, double %a43 ret double %cond44}45 46define float @fparmv8_vminnm_u(float %a, float %b) {47; CHECK-LABEL: fparmv8_vminnm_u:48; CHECK: @ %bb.0:49; CHECK-NEXT: vminnm.f32 s0, s0, s150; CHECK-NEXT: bx lr51 %cmp = fcmp fast ult float %a, %b52 %cond = select nsz i1 %cmp, float %a, float %b53 ret float %cond54}55 56define float @fparmv8_vminnm_ule(float %a, float %b) {57; CHECK-LABEL: fparmv8_vminnm_ule:58; CHECK: @ %bb.0:59; CHECK-NEXT: vminnm.f32 s0, s0, s160; CHECK-NEXT: bx lr61 %cmp = fcmp fast ule float %a, %b62 %cond = select nsz i1 %cmp, float %a, float %b63 ret float %cond64}65 66define float @fparmv8_vminnm_u_rev(float %a, float %b) {67; CHECK-LABEL: fparmv8_vminnm_u_rev:68; CHECK: @ %bb.0:69; CHECK-NEXT: vminnm.f32 s0, s0, s170; CHECK-NEXT: bx lr71 %cmp = fcmp fast ugt float %a, %b72 %cond = select nsz i1 %cmp, float %b, float %a73 ret float %cond74}75 76define double @fparmv8_vminnm_uge_rev(double %a, double %b) {77; CHECK-LABEL: fparmv8_vminnm_uge_rev:78; CHECK: @ %bb.0:79; CHECK-NEXT: vminnm.f64 d0, d0, d180; CHECK-NEXT: bx lr81 %cmp = fcmp fast uge double %a, %b82 %cond = select nsz i1 %cmp, double %b, double %a83 ret double %cond84}85 86define float @fparmv8_vmaxnm_o(float %a, float %b) {87; CHECK-LABEL: fparmv8_vmaxnm_o:88; CHECK: @ %bb.0:89; CHECK-NEXT: vmaxnm.f32 s0, s0, s190; CHECK-NEXT: bx lr91 %cmp = fcmp fast ogt float %a, %b92 %cond = select nsz i1 %cmp, float %a, float %b93 ret float %cond94}95 96define float @fparmv8_vmaxnm_oge(float %a, float %b) {97; CHECK-LABEL: fparmv8_vmaxnm_oge:98; CHECK: @ %bb.0:99; CHECK-NEXT: vmaxnm.f32 s0, s0, s1100; CHECK-NEXT: bx lr101 %cmp = fcmp fast oge float %a, %b102 %cond = select nsz i1 %cmp, float %a, float %b103 ret float %cond104}105 106define float @fparmv8_vmaxnm_o_rev(float %a, float %b) {107; CHECK-LABEL: fparmv8_vmaxnm_o_rev:108; CHECK: @ %bb.0:109; CHECK-NEXT: vmaxnm.f32 s0, s0, s1110; CHECK-NEXT: bx lr111 %cmp = fcmp fast olt float %a, %b112 %cond = select nsz i1 %cmp, float %b, float %a113 ret float %cond114}115 116define float @fparmv8_vmaxnm_ole_rev(float %a, float %b) {117; CHECK-LABEL: fparmv8_vmaxnm_ole_rev:118; CHECK: @ %bb.0:119; CHECK-NEXT: vmaxnm.f32 s0, s0, s1120; CHECK-NEXT: bx lr121 %cmp = fcmp fast ole float %a, %b122 %cond = select nsz i1 %cmp, float %b, float %a123 ret float %cond124}125 126define float @fparmv8_vmaxnm_u(float %a, float %b) {127; CHECK-LABEL: fparmv8_vmaxnm_u:128; CHECK: @ %bb.0:129; CHECK-NEXT: vmaxnm.f32 s0, s0, s1130; CHECK-NEXT: bx lr131 %cmp = fcmp fast ugt float %a, %b132 %cond = select nsz i1 %cmp, float %a, float %b133 ret float %cond134}135 136define float @fparmv8_vmaxnm_uge(float %a, float %b) {137; CHECK-LABEL: fparmv8_vmaxnm_uge:138; CHECK: @ %bb.0:139; CHECK-NEXT: vmaxnm.f32 s0, s0, s1140; CHECK-NEXT: bx lr141 %cmp = fcmp fast uge float %a, %b142 %cond = select nsz i1 %cmp, float %a, float %b143 ret float %cond144}145 146define float @fparmv8_vmaxnm_u_rev(float %a, float %b) {147; CHECK-LABEL: fparmv8_vmaxnm_u_rev:148; CHECK: @ %bb.0:149; CHECK-NEXT: vmaxnm.f32 s0, s0, s1150; CHECK-NEXT: bx lr151 %cmp = fcmp fast ult float %a, %b152 %cond = select nsz i1 %cmp, float %b, float %a153 ret float %cond154}155 156define double @fparmv8_vmaxnm_ule_rev(double %a, double %b) {157; CHECK-LABEL: fparmv8_vmaxnm_ule_rev:158; CHECK: @ %bb.0:159; CHECK-NEXT: vmaxnm.f64 d0, d0, d1160; CHECK-NEXT: bx lr161 %cmp = fcmp fast ule double %a, %b162 %cond = select nsz i1 %cmp, double %b, double %a163 ret double %cond164}165 166; known non-NaNs167 168define float @fparmv8_vminnm_NNNo(float %a) {169; CHECK-LABEL: fparmv8_vminnm_NNNo:170; CHECK: @ %bb.0:171; CHECK-NEXT: vmov.f32 s2, #1.200000e+01172; CHECK-NEXT: vldr s4, .LCPI16_0173; CHECK-NEXT: vminnm.f32 s0, s0, s2174; CHECK-NEXT: vminnm.f32 s0, s0, s4175; CHECK-NEXT: bx lr176; CHECK-NEXT: .p2align 2177; CHECK-NEXT: @ %bb.1:178; CHECK-NEXT: .LCPI16_0:179; CHECK-NEXT: .long 0x42080000 @ float 34180 %cmp1 = fcmp fast olt float %a, 12.181 %cond1 = select nsz i1 %cmp1, float %a, float 12.182 %cmp2 = fcmp fast olt float 34., %cond1183 %cond2 = select nsz i1 %cmp2, float 34., float %cond1184 ret float %cond2185}186 187define double @fparmv8_vminnm_NNNole(double %a) {188; CHECK-LABEL: fparmv8_vminnm_NNNole:189; CHECK: @ %bb.0:190; CHECK-NEXT: vldr d16, .LCPI17_0191; CHECK-NEXT: vldr d17, .LCPI17_1192; CHECK-NEXT: vminnm.f64 d16, d0, d16193; CHECK-NEXT: vminnm.f64 d0, d16, d17194; CHECK-NEXT: bx lr195; CHECK-NEXT: .p2align 3196; CHECK-NEXT: @ %bb.1:197; CHECK-NEXT: .LCPI17_0:198; CHECK-NEXT: .long 0 @ double 34199; CHECK-NEXT: .long 1078001664200; CHECK-NEXT: .LCPI17_1:201; CHECK-NEXT: .long 0 @ double 56202; CHECK-NEXT: .long 1078722560203 %cmp1 = fcmp fast ole double %a, 34.204 %cond1 = select nsz i1 %cmp1, double %a, double 34.205 %cmp2 = fcmp fast ole double 56., %cond1206 %cond2 = select nsz i1 %cmp2, double 56., double %cond1207 ret double %cond2208}209 210define float @fparmv8_vminnm_NNNo_rev(float %a) {211; CHECK-LABEL: fparmv8_vminnm_NNNo_rev:212; CHECK: @ %bb.0:213; CHECK-NEXT: vldr s2, .LCPI18_0214; CHECK-NEXT: vldr s4, .LCPI18_1215; CHECK-NEXT: vminnm.f32 s0, s0, s2216; CHECK-NEXT: vminnm.f32 s0, s0, s4217; CHECK-NEXT: bx lr218; CHECK-NEXT: .p2align 2219; CHECK-NEXT: @ %bb.1:220; CHECK-NEXT: .LCPI18_0:221; CHECK-NEXT: .long 0x42600000 @ float 56222; CHECK-NEXT: .LCPI18_1:223; CHECK-NEXT: .long 0x429c0000 @ float 78224 %cmp1 = fcmp fast ogt float %a, 56.225 %cond1 = select nsz i1 %cmp1, float 56., float %a226 %cmp2 = fcmp fast ogt float 78., %cond1227 %cond2 = select nsz i1 %cmp2, float %cond1, float 78.228 ret float %cond2229}230 231define double @fparmv8_vminnm_NNNoge_rev(double %a) {232; CHECK-LABEL: fparmv8_vminnm_NNNoge_rev:233; CHECK: @ %bb.0:234; CHECK-NEXT: vldr d16, .LCPI19_0235; CHECK-NEXT: vldr d17, .LCPI19_1236; CHECK-NEXT: vminnm.f64 d16, d0, d16237; CHECK-NEXT: vminnm.f64 d0, d16, d17238; CHECK-NEXT: bx lr239; CHECK-NEXT: .p2align 3240; CHECK-NEXT: @ %bb.1:241; CHECK-NEXT: .LCPI19_0:242; CHECK-NEXT: .long 0 @ double 78243; CHECK-NEXT: .long 1079214080244; CHECK-NEXT: .LCPI19_1:245; CHECK-NEXT: .long 0 @ double 90246; CHECK-NEXT: .long 1079410688247 %cmp1 = fcmp fast oge double %a, 78.248 %cond1 = select nsz i1 %cmp1, double 78., double %a249 %cmp2 = fcmp fast oge double 90., %cond1250 %cond2 = select nsz i1 %cmp2, double %cond1, double 90.251 ret double %cond2252}253 254define float @fparmv8_vminnm_NNNu(float %b) {255; CHECK-LABEL: fparmv8_vminnm_NNNu:256; CHECK: @ %bb.0:257; CHECK-NEXT: vmov.f32 s2, #1.200000e+01258; CHECK-NEXT: vldr s4, .LCPI20_0259; CHECK-NEXT: vminnm.f32 s0, s0, s2260; CHECK-NEXT: vminnm.f32 s0, s0, s4261; CHECK-NEXT: bx lr262; CHECK-NEXT: .p2align 2263; CHECK-NEXT: @ %bb.1:264; CHECK-NEXT: .LCPI20_0:265; CHECK-NEXT: .long 0x42080000 @ float 34266 %cmp1 = fcmp fast ult float 12., %b267 %cond1 = select nsz i1 %cmp1, float 12., float %b268 %cmp2 = fcmp fast ult float %cond1, 34.269 %cond2 = select nsz i1 %cmp2, float %cond1, float 34.270 ret float %cond2271}272 273define float @fparmv8_vminnm_NNNule(float %b) {274; CHECK-LABEL: fparmv8_vminnm_NNNule:275; CHECK: @ %bb.0:276; CHECK-NEXT: vldr s2, .LCPI21_0277; CHECK-NEXT: vldr s4, .LCPI21_1278; CHECK-NEXT: vminnm.f32 s0, s0, s2279; CHECK-NEXT: vminnm.f32 s0, s0, s4280; CHECK-NEXT: bx lr281; CHECK-NEXT: .p2align 2282; CHECK-NEXT: @ %bb.1:283; CHECK-NEXT: .LCPI21_0:284; CHECK-NEXT: .long 0x42080000 @ float 34285; CHECK-NEXT: .LCPI21_1:286; CHECK-NEXT: .long 0x42600000 @ float 56287 %cmp1 = fcmp fast ule float 34., %b288 %cond1 = select nsz i1 %cmp1, float 34., float %b289 %cmp2 = fcmp fast ule float %cond1, 56.290 %cond2 = select nsz i1 %cmp2, float %cond1, float 56.291 ret float %cond2292}293 294define float @fparmv8_vminnm_NNNu_rev(float %b) {295; CHECK-LABEL: fparmv8_vminnm_NNNu_rev:296; CHECK: @ %bb.0:297; CHECK-NEXT: vldr s2, .LCPI22_0298; CHECK-NEXT: vldr s4, .LCPI22_1299; CHECK-NEXT: vminnm.f32 s0, s0, s2300; CHECK-NEXT: vminnm.f32 s0, s0, s4301; CHECK-NEXT: bx lr302; CHECK-NEXT: .p2align 2303; CHECK-NEXT: @ %bb.1:304; CHECK-NEXT: .LCPI22_0:305; CHECK-NEXT: .long 0x42600000 @ float 56306; CHECK-NEXT: .LCPI22_1:307; CHECK-NEXT: .long 0x429c0000 @ float 78308 %cmp1 = fcmp fast ugt float 56., %b309 %cond1 = select nsz i1 %cmp1, float %b, float 56.310 %cmp2 = fcmp fast ugt float %cond1, 78.311 %cond2 = select nsz i1 %cmp2, float 78., float %cond1312 ret float %cond2313}314 315define double @fparmv8_vminnm_NNNuge_rev(double %b) {316; CHECK-LABEL: fparmv8_vminnm_NNNuge_rev:317; CHECK: @ %bb.0:318; CHECK-NEXT: vldr d16, .LCPI23_0319; CHECK-NEXT: vldr d17, .LCPI23_1320; CHECK-NEXT: vminnm.f64 d16, d0, d16321; CHECK-NEXT: vminnm.f64 d0, d16, d17322; CHECK-NEXT: bx lr323; CHECK-NEXT: .p2align 3324; CHECK-NEXT: @ %bb.1:325; CHECK-NEXT: .LCPI23_0:326; CHECK-NEXT: .long 0 @ double 78327; CHECK-NEXT: .long 1079214080328; CHECK-NEXT: .LCPI23_1:329; CHECK-NEXT: .long 0 @ double 90330; CHECK-NEXT: .long 1079410688331 %cmp1 = fcmp fast uge double 78., %b332 %cond1 = select nsz i1 %cmp1, double %b, double 78.333 %cmp2 = fcmp fast uge double %cond1, 90.334 %cond2 = select nsz i1 %cmp2, double 90., double %cond1335 ret double %cond2336}337 338define float @fparmv8_vmaxnm_NNNo(float %a) {339; CHECK-LABEL: fparmv8_vmaxnm_NNNo:340; CHECK: @ %bb.0:341; CHECK-NEXT: vmov.f32 s2, #1.200000e+01342; CHECK-NEXT: vldr s4, .LCPI24_0343; CHECK-NEXT: vmaxnm.f32 s0, s0, s2344; CHECK-NEXT: vmaxnm.f32 s0, s0, s4345; CHECK-NEXT: bx lr346; CHECK-NEXT: .p2align 2347; CHECK-NEXT: @ %bb.1:348; CHECK-NEXT: .LCPI24_0:349; CHECK-NEXT: .long 0x42080000 @ float 34350 %cmp1 = fcmp fast ogt float %a, 12.351 %cond1 = select nsz i1 %cmp1, float %a, float 12.352 %cmp2 = fcmp fast ogt float 34., %cond1353 %cond2 = select nsz i1 %cmp2, float 34., float %cond1354 ret float %cond2355}356 357define float @fparmv8_vmaxnm_NNNoge(float %a) {358; CHECK-LABEL: fparmv8_vmaxnm_NNNoge:359; CHECK: @ %bb.0:360; CHECK-NEXT: vldr s2, .LCPI25_0361; CHECK-NEXT: vldr s4, .LCPI25_1362; CHECK-NEXT: vmaxnm.f32 s0, s0, s2363; CHECK-NEXT: vmaxnm.f32 s0, s0, s4364; CHECK-NEXT: bx lr365; CHECK-NEXT: .p2align 2366; CHECK-NEXT: @ %bb.1:367; CHECK-NEXT: .LCPI25_0:368; CHECK-NEXT: .long 0x42080000 @ float 34369; CHECK-NEXT: .LCPI25_1:370; CHECK-NEXT: .long 0x42600000 @ float 56371 %cmp1 = fcmp fast oge float %a, 34.372 %cond1 = select nsz i1 %cmp1, float %a, float 34.373 %cmp2 = fcmp fast oge float 56., %cond1374 %cond2 = select nsz i1 %cmp2, float 56., float %cond1375 ret float %cond2376}377 378define float @fparmv8_vmaxnm_NNNo_rev(float %a) {379; CHECK-LABEL: fparmv8_vmaxnm_NNNo_rev:380; CHECK: @ %bb.0:381; CHECK-NEXT: vldr s2, .LCPI26_0382; CHECK-NEXT: vldr s4, .LCPI26_1383; CHECK-NEXT: vmaxnm.f32 s0, s0, s2384; CHECK-NEXT: vmaxnm.f32 s0, s0, s4385; CHECK-NEXT: bx lr386; CHECK-NEXT: .p2align 2387; CHECK-NEXT: @ %bb.1:388; CHECK-NEXT: .LCPI26_0:389; CHECK-NEXT: .long 0x42600000 @ float 56390; CHECK-NEXT: .LCPI26_1:391; CHECK-NEXT: .long 0x429c0000 @ float 78392 %cmp1 = fcmp fast olt float %a, 56.393 %cond1 = select nsz i1 %cmp1, float 56., float %a394 %cmp2 = fcmp fast olt float 78., %cond1395 %cond2 = select nsz i1 %cmp2, float %cond1, float 78.396 ret float %cond2397}398 399define float @fparmv8_vmaxnm_NNNole_rev(float %a) {400; CHECK-LABEL: fparmv8_vmaxnm_NNNole_rev:401; CHECK: @ %bb.0:402; CHECK-NEXT: vldr s2, .LCPI27_0403; CHECK-NEXT: vldr s4, .LCPI27_1404; CHECK-NEXT: vmaxnm.f32 s0, s0, s2405; CHECK-NEXT: vmaxnm.f32 s0, s0, s4406; CHECK-NEXT: bx lr407; CHECK-NEXT: .p2align 2408; CHECK-NEXT: @ %bb.1:409; CHECK-NEXT: .LCPI27_0:410; CHECK-NEXT: .long 0x429c0000 @ float 78411; CHECK-NEXT: .LCPI27_1:412; CHECK-NEXT: .long 0x42b40000 @ float 90413 %cmp1 = fcmp fast ole float %a, 78.414 %cond1 = select nsz i1 %cmp1, float 78., float %a415 %cmp2 = fcmp fast ole float 90., %cond1416 %cond2 = select nsz i1 %cmp2, float %cond1, float 90.417 ret float %cond2418}419 420define float @fparmv8_vmaxnm_NNNu(float %b) {421; CHECK-LABEL: fparmv8_vmaxnm_NNNu:422; CHECK: @ %bb.0:423; CHECK-NEXT: vmov.f32 s2, #1.200000e+01424; CHECK-NEXT: vldr s4, .LCPI28_0425; CHECK-NEXT: vmaxnm.f32 s0, s0, s2426; CHECK-NEXT: vmaxnm.f32 s0, s0, s4427; CHECK-NEXT: bx lr428; CHECK-NEXT: .p2align 2429; CHECK-NEXT: @ %bb.1:430; CHECK-NEXT: .LCPI28_0:431; CHECK-NEXT: .long 0x42080000 @ float 34432 %cmp1 = fcmp fast ugt float 12., %b433 %cond1 = select nsz i1 %cmp1, float 12., float %b434 %cmp2 = fcmp fast ugt float %cond1, 34.435 %cond2 = select nsz i1 %cmp2, float %cond1, float 34.436 ret float %cond2437}438 439define float @fparmv8_vmaxnm_NNNuge(float %b) {440; CHECK-LABEL: fparmv8_vmaxnm_NNNuge:441; CHECK: @ %bb.0:442; CHECK-NEXT: vldr s2, .LCPI29_0443; CHECK-NEXT: vldr s4, .LCPI29_1444; CHECK-NEXT: vmaxnm.f32 s0, s0, s2445; CHECK-NEXT: vmaxnm.f32 s0, s0, s4446; CHECK-NEXT: bx lr447; CHECK-NEXT: .p2align 2448; CHECK-NEXT: @ %bb.1:449; CHECK-NEXT: .LCPI29_0:450; CHECK-NEXT: .long 0x42080000 @ float 34451; CHECK-NEXT: .LCPI29_1:452; CHECK-NEXT: .long 0x42600000 @ float 56453 %cmp1 = fcmp fast uge float 34., %b454 %cond1 = select nsz i1 %cmp1, float 34., float %b455 %cmp2 = fcmp fast uge float %cond1, 56.456 %cond2 = select nsz i1 %cmp2, float %cond1, float 56.457 ret float %cond2458}459 460define float @fparmv8_vmaxnm_NNNu_rev(float %b) {461; CHECK-LABEL: fparmv8_vmaxnm_NNNu_rev:462; CHECK: @ %bb.0:463; CHECK-NEXT: vldr s2, .LCPI30_0464; CHECK-NEXT: vldr s4, .LCPI30_1465; CHECK-NEXT: vmaxnm.f32 s0, s0, s2466; CHECK-NEXT: vmaxnm.f32 s0, s0, s4467; CHECK-NEXT: bx lr468; CHECK-NEXT: .p2align 2469; CHECK-NEXT: @ %bb.1:470; CHECK-NEXT: .LCPI30_0:471; CHECK-NEXT: .long 0x42600000 @ float 56472; CHECK-NEXT: .LCPI30_1:473; CHECK-NEXT: .long 0x429c0000 @ float 78474 %cmp1 = fcmp fast ult float 56., %b475 %cond1 = select nsz i1 %cmp1, float %b, float 56.476 %cmp2 = fcmp fast ult float %cond1, 78.477 %cond2 = select nsz i1 %cmp2, float 78., float %cond1478 ret float %cond2479}480 481define double @fparmv8_vmaxnm_NNNule_rev( double %b) {482; CHECK-LABEL: fparmv8_vmaxnm_NNNule_rev:483; CHECK: @ %bb.0:484; CHECK-NEXT: vldr d16, .LCPI31_0485; CHECK-NEXT: vldr d17, .LCPI31_1486; CHECK-NEXT: vmaxnm.f64 d16, d0, d16487; CHECK-NEXT: vmaxnm.f64 d0, d16, d17488; CHECK-NEXT: bx lr489; CHECK-NEXT: .p2align 3490; CHECK-NEXT: @ %bb.1:491; CHECK-NEXT: .LCPI31_0:492; CHECK-NEXT: .long 0 @ double 78493; CHECK-NEXT: .long 1079214080494; CHECK-NEXT: .LCPI31_1:495; CHECK-NEXT: .long 0 @ double 90496; CHECK-NEXT: .long 1079410688497 %cmp1 = fcmp fast ule double 78., %b498 %cond1 = select nsz i1 %cmp1, double %b, double 78.499 %cmp2 = fcmp fast ule double %cond1, 90.500 %cond2 = select nsz i1 %cmp2, double 90., double %cond1501 ret double %cond2502}503 504define float @fparmv8_vminmaxnm_0(float %a) {505; CHECK-LABEL: fparmv8_vminmaxnm_0:506; CHECK: @ %bb.0:507; CHECK-NEXT: vldr s2, .LCPI32_0508; CHECK-NEXT: vminnm.f32 s0, s0, s2509; CHECK-NEXT: vmaxnm.f32 s0, s0, s2510; CHECK-NEXT: bx lr511; CHECK-NEXT: .p2align 2512; CHECK-NEXT: @ %bb.1:513; CHECK-NEXT: .LCPI32_0:514; CHECK-NEXT: .long 0x00000000 @ float 0515 %cmp1 = fcmp fast olt float %a, 0.516 %cond1 = select nsz i1 %cmp1, float %a, float 0.517 %cmp2 = fcmp fast ogt float %cond1, 0.518 %cond2 = select nsz i1 %cmp2, float %cond1, float 0.519 ret float %cond2520}521 522define float @fparmv8_vminmaxnm_neg0(float %a) {523; CHECK-LABEL: fparmv8_vminmaxnm_neg0:524; CHECK: @ %bb.0:525; CHECK-NEXT: vldr s2, .LCPI33_0526; CHECK-NEXT: vminnm.f32 s0, s0, s2527; CHECK-NEXT: vmaxnm.f32 s0, s0, s2528; CHECK-NEXT: bx lr529; CHECK-NEXT: .p2align 2530; CHECK-NEXT: @ %bb.1:531; CHECK-NEXT: .LCPI33_0:532; CHECK-NEXT: .long 0x80000000 @ float -0533 %cmp1 = fcmp fast olt float %a, -0.534 %cond1 = select nsz i1 %cmp1, float %a, float -0.535 %cmp2 = fcmp fast ugt float %cond1, -0.536 %cond2 = select nsz i1 %cmp2, float %cond1, float -0.537 ret float %cond2538}539 540define float @fparmv8_vminmaxnm_e_0(float %a) {541; CHECK-LABEL: fparmv8_vminmaxnm_e_0:542; CHECK: @ %bb.0:543; CHECK-NEXT: vldr s2, .LCPI34_0544; CHECK-NEXT: vminnm.f32 s0, s0, s2545; CHECK-NEXT: vmaxnm.f32 s0, s0, s2546; CHECK-NEXT: bx lr547; CHECK-NEXT: .p2align 2548; CHECK-NEXT: @ %bb.1:549; CHECK-NEXT: .LCPI34_0:550; CHECK-NEXT: .long 0x00000000 @ float 0551 %cmp1 = fcmp fast ule float 0., %a552 %cond1 = select nsz i1 %cmp1, float 0., float %a553 %cmp2 = fcmp fast uge float 0., %cond1554 %cond2 = select nsz i1 %cmp2, float 0., float %cond1555 ret float %cond2556}557 558define float @fparmv8_vminmaxnm_e_neg0(float %a) {559; CHECK-LABEL: fparmv8_vminmaxnm_e_neg0:560; CHECK: @ %bb.0:561; CHECK-NEXT: vldr s2, .LCPI35_0562; CHECK-NEXT: vminnm.f32 s0, s0, s2563; CHECK-NEXT: vmaxnm.f32 s0, s0, s2564; CHECK-NEXT: bx lr565; CHECK-NEXT: .p2align 2566; CHECK-NEXT: @ %bb.1:567; CHECK-NEXT: .LCPI35_0:568; CHECK-NEXT: .long 0x80000000 @ float -0569 %cmp1 = fcmp fast ule float -0., %a570 %cond1 = select nsz i1 %cmp1, float -0., float %a571 %cmp2 = fcmp fast oge float -0., %cond1572 %cond2 = select nsz i1 %cmp2, float -0., float %cond1573 ret float %cond2574}575 576declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone577declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone578declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone579declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) nounwind readnone580