1312 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm-eabi -mattr=+neon,+fullfp16 %s -o - | FileCheck --check-prefixes=CHECK,CHECK-LE %s3; RUN: llc -mtriple=armeb-eabi -mattr=+neon,+fullfp16 %s -o - | FileCheck --check-prefixes=CHECK,CHECK-BE %s4 5define arm_aapcs_vfpcc <8 x i8> @v_movi8() nounwind {6; CHECK-LABEL: v_movi8:7; CHECK: @ %bb.0:8; CHECK-NEXT: vmov.i8 d0, #0x89; CHECK-NEXT: mov pc, lr10 ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >11}12 13define arm_aapcs_vfpcc <4 x i16> @v_movi16a() nounwind {14; CHECK-LABEL: v_movi16a:15; CHECK: @ %bb.0:16; CHECK-NEXT: vmov.i16 d0, #0x1017; CHECK-NEXT: mov pc, lr18 ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >19}20 21define arm_aapcs_vfpcc <4 x i16> @v_movi16b() nounwind {22; CHECK-LABEL: v_movi16b:23; CHECK: @ %bb.0:24; CHECK-NEXT: vmov.i16 d0, #0x100025; CHECK-NEXT: mov pc, lr26 ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >27}28 29define arm_aapcs_vfpcc <4 x i16> @v_mvni16a() nounwind {30; CHECK-LABEL: v_mvni16a:31; CHECK: @ %bb.0:32; CHECK-NEXT: vmvn.i16 d0, #0x1033; CHECK-NEXT: mov pc, lr34 ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >35}36 37define arm_aapcs_vfpcc <4 x i16> @v_mvni16b() nounwind {38; CHECK-LABEL: v_mvni16b:39; CHECK: @ %bb.0:40; CHECK-NEXT: vmvn.i16 d0, #0x100041; CHECK-NEXT: mov pc, lr42 ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >43}44 45define arm_aapcs_vfpcc <2 x i32> @v_movi32a() nounwind {46; CHECK-LABEL: v_movi32a:47; CHECK: @ %bb.0:48; CHECK-NEXT: vmov.i32 d0, #0x2049; CHECK-NEXT: mov pc, lr50 ret <2 x i32> < i32 32, i32 32 >51}52 53define arm_aapcs_vfpcc <2 x i32> @v_movi32b() nounwind {54; CHECK-LABEL: v_movi32b:55; CHECK: @ %bb.0:56; CHECK-NEXT: vmov.i32 d0, #0x200057; CHECK-NEXT: mov pc, lr58 ret <2 x i32> < i32 8192, i32 8192 >59}60 61define arm_aapcs_vfpcc <2 x i32> @v_movi32c() nounwind {62; CHECK-LABEL: v_movi32c:63; CHECK: @ %bb.0:64; CHECK-NEXT: vmov.i32 d0, #0x20000065; CHECK-NEXT: mov pc, lr66 ret <2 x i32> < i32 2097152, i32 2097152 >67}68 69define arm_aapcs_vfpcc <2 x i32> @v_movi32d() nounwind {70; CHECK-LABEL: v_movi32d:71; CHECK: @ %bb.0:72; CHECK-NEXT: vmov.i32 d0, #0x2000000073; CHECK-NEXT: mov pc, lr74 ret <2 x i32> < i32 536870912, i32 536870912 >75}76 77define arm_aapcs_vfpcc <2 x i32> @v_movi32e() nounwind {78; CHECK-LABEL: v_movi32e:79; CHECK: @ %bb.0:80; CHECK-NEXT: vmov.i32 d0, #0x20ff81; CHECK-NEXT: mov pc, lr82 ret <2 x i32> < i32 8447, i32 8447 >83}84 85define arm_aapcs_vfpcc <2 x i32> @v_movi32f() nounwind {86; CHECK-LABEL: v_movi32f:87; CHECK: @ %bb.0:88; CHECK-NEXT: vmov.i32 d0, #0x20ffff89; CHECK-NEXT: mov pc, lr90 ret <2 x i32> < i32 2162687, i32 2162687 >91}92 93define arm_aapcs_vfpcc <2 x i32> @v_mvni32a() nounwind {94; CHECK-LABEL: v_mvni32a:95; CHECK: @ %bb.0:96; CHECK-NEXT: vmvn.i32 d0, #0x2097; CHECK-NEXT: mov pc, lr98 ret <2 x i32> < i32 4294967263, i32 4294967263 >99}100 101define arm_aapcs_vfpcc <2 x i32> @v_mvni32b() nounwind {102; CHECK-LABEL: v_mvni32b:103; CHECK: @ %bb.0:104; CHECK-NEXT: vmvn.i32 d0, #0x2000105; CHECK-NEXT: mov pc, lr106 ret <2 x i32> < i32 4294959103, i32 4294959103 >107}108 109define arm_aapcs_vfpcc <2 x i32> @v_mvni32c() nounwind {110; CHECK-LABEL: v_mvni32c:111; CHECK: @ %bb.0:112; CHECK-NEXT: vmvn.i32 d0, #0x200000113; CHECK-NEXT: mov pc, lr114 ret <2 x i32> < i32 4292870143, i32 4292870143 >115}116 117define arm_aapcs_vfpcc <2 x i32> @v_mvni32d() nounwind {118; CHECK-LABEL: v_mvni32d:119; CHECK: @ %bb.0:120; CHECK-NEXT: vmvn.i32 d0, #0x20000000121; CHECK-NEXT: mov pc, lr122 ret <2 x i32> < i32 3758096383, i32 3758096383 >123}124 125define arm_aapcs_vfpcc <2 x i32> @v_mvni32e() nounwind {126; CHECK-LABEL: v_mvni32e:127; CHECK: @ %bb.0:128; CHECK-NEXT: vmvn.i32 d0, #0x20ff129; CHECK-NEXT: mov pc, lr130 ret <2 x i32> < i32 4294958848, i32 4294958848 >131}132 133define arm_aapcs_vfpcc <2 x i32> @v_mvni32f() nounwind {134; CHECK-LABEL: v_mvni32f:135; CHECK: @ %bb.0:136; CHECK-NEXT: vmvn.i32 d0, #0x20ffff137; CHECK-NEXT: mov pc, lr138 ret <2 x i32> < i32 4292804608, i32 4292804608 >139}140 141define arm_aapcs_vfpcc <1 x i64> @v_movi64() nounwind {142; CHECK-LE-LABEL: v_movi64:143; CHECK-LE: @ %bb.0:144; CHECK-LE-NEXT: vmov.i64 d0, #0xff0000ff0000ffff145; CHECK-LE-NEXT: mov pc, lr146;147; CHECK-BE-LABEL: v_movi64:148; CHECK-BE: @ %bb.0:149; CHECK-BE-NEXT: vmov.i64 d16, #0xffffff0000ff150; CHECK-BE-NEXT: vrev64.32 d0, d16151; CHECK-BE-NEXT: mov pc, lr152 ret <1 x i64> < i64 18374687574888349695 >153}154 155define arm_aapcs_vfpcc <16 x i8> @v_movQi8() nounwind {156; CHECK-LABEL: v_movQi8:157; CHECK: @ %bb.0:158; CHECK-NEXT: vmov.i8 q0, #0x8159; CHECK-NEXT: mov pc, lr160 ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >161}162 163define arm_aapcs_vfpcc <8 x i16> @v_movQi16a() nounwind {164; CHECK-LABEL: v_movQi16a:165; CHECK: @ %bb.0:166; CHECK-NEXT: vmov.i16 q0, #0x10167; CHECK-NEXT: mov pc, lr168 ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >169}170 171define arm_aapcs_vfpcc <8 x i16> @v_movQi16b() nounwind {172; CHECK-LABEL: v_movQi16b:173; CHECK: @ %bb.0:174; CHECK-NEXT: vmov.i16 q0, #0x1000175; CHECK-NEXT: mov pc, lr176 ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >177}178 179define arm_aapcs_vfpcc <4 x i32> @v_movQi32a() nounwind {180; CHECK-LABEL: v_movQi32a:181; CHECK: @ %bb.0:182; CHECK-NEXT: vmov.i32 q0, #0x20183; CHECK-NEXT: mov pc, lr184 ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >185}186 187define arm_aapcs_vfpcc <4 x i32> @v_movQi32b() nounwind {188; CHECK-LABEL: v_movQi32b:189; CHECK: @ %bb.0:190; CHECK-NEXT: vmov.i32 q0, #0x2000191; CHECK-NEXT: mov pc, lr192 ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >193}194 195define arm_aapcs_vfpcc <4 x i32> @v_movQi32c() nounwind {196; CHECK-LABEL: v_movQi32c:197; CHECK: @ %bb.0:198; CHECK-NEXT: vmov.i32 q0, #0x200000199; CHECK-NEXT: mov pc, lr200 ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >201}202 203define arm_aapcs_vfpcc <4 x i32> @v_movQi32d() nounwind {204; CHECK-LABEL: v_movQi32d:205; CHECK: @ %bb.0:206; CHECK-NEXT: vmov.i32 q0, #0x20000000207; CHECK-NEXT: mov pc, lr208 ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >209}210 211define arm_aapcs_vfpcc <4 x i32> @v_movQi32e() nounwind {212; CHECK-LABEL: v_movQi32e:213; CHECK: @ %bb.0:214; CHECK-NEXT: vmov.i32 q0, #0x20ff215; CHECK-NEXT: mov pc, lr216 ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >217}218 219define arm_aapcs_vfpcc <4 x i32> @v_movQi32f() nounwind {220; CHECK-LABEL: v_movQi32f:221; CHECK: @ %bb.0:222; CHECK-NEXT: vmov.i32 q0, #0x20ffff223; CHECK-NEXT: mov pc, lr224 ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >225}226 227define arm_aapcs_vfpcc <2 x i64> @v_movQi64() nounwind {228; CHECK-LABEL: v_movQi64:229; CHECK: @ %bb.0:230; CHECK-NEXT: vmov.i64 q0, #0xff0000ff0000ffff231; CHECK-NEXT: mov pc, lr232 ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >233}234 235; Check for correct assembler printing for immediate values.236%struct.int8x8_t = type { <8 x i8> }237define arm_aapcs_vfpcc void @vdupn128(ptr noalias nocapture sret(%struct.int8x8_t) %agg.result) nounwind {238; CHECK-LABEL: vdupn128:239; CHECK: @ %bb.0: @ %entry240; CHECK-NEXT: vmov.i8 d16, #0x80241; CHECK-NEXT: vstr d16, [r0]242; CHECK-NEXT: mov pc, lr243entry:244 %0 = getelementptr inbounds %struct.int8x8_t, ptr %agg.result, i32 0, i32 0 ; <ptr> [#uses=1]245 store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, ptr %0, align 8246 ret void247}248 249define arm_aapcs_vfpcc void @vdupnneg75(ptr noalias nocapture sret(%struct.int8x8_t) %agg.result) nounwind {250; CHECK-LABEL: vdupnneg75:251; CHECK: @ %bb.0: @ %entry252; CHECK-NEXT: vmov.i8 d16, #0xb5253; CHECK-NEXT: vstr d16, [r0]254; CHECK-NEXT: mov pc, lr255entry:256 %0 = getelementptr inbounds %struct.int8x8_t, ptr %agg.result, i32 0, i32 0 ; <ptr> [#uses=1]257 store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, ptr %0, align 8258 ret void259}260 261define arm_aapcs_vfpcc <8 x i16> @vmovls8(ptr %A) nounwind {262; CHECK-LE-LABEL: vmovls8:263; CHECK-LE: @ %bb.0:264; CHECK-LE-NEXT: vld1.8 {d16}, [r0:64]265; CHECK-LE-NEXT: vmovl.s8 q0, d16266; CHECK-LE-NEXT: mov pc, lr267;268; CHECK-BE-LABEL: vmovls8:269; CHECK-BE: @ %bb.0:270; CHECK-BE-NEXT: vld1.8 {d16}, [r0:64]271; CHECK-BE-NEXT: vmovl.s8 q8, d16272; CHECK-BE-NEXT: vrev64.16 q0, q8273; CHECK-BE-NEXT: mov pc, lr274 %tmp1 = load <8 x i8>, ptr %A275 %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>276 ret <8 x i16> %tmp2277}278 279define arm_aapcs_vfpcc <4 x i32> @vmovls16(ptr %A) nounwind {280; CHECK-LE-LABEL: vmovls16:281; CHECK-LE: @ %bb.0:282; CHECK-LE-NEXT: vld1.16 {d16}, [r0:64]283; CHECK-LE-NEXT: vmovl.s16 q0, d16284; CHECK-LE-NEXT: mov pc, lr285;286; CHECK-BE-LABEL: vmovls16:287; CHECK-BE: @ %bb.0:288; CHECK-BE-NEXT: vld1.16 {d16}, [r0:64]289; CHECK-BE-NEXT: vmovl.s16 q8, d16290; CHECK-BE-NEXT: vrev64.32 q0, q8291; CHECK-BE-NEXT: mov pc, lr292 %tmp1 = load <4 x i16>, ptr %A293 %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>294 ret <4 x i32> %tmp2295}296 297define arm_aapcs_vfpcc <2 x i64> @vmovls32(ptr %A) nounwind {298; CHECK-LABEL: vmovls32:299; CHECK: @ %bb.0:300; CHECK-NEXT: vld1.32 {d16}, [r0:64]301; CHECK-NEXT: vmovl.s32 q0, d16302; CHECK-NEXT: mov pc, lr303 %tmp1 = load <2 x i32>, ptr %A304 %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>305 ret <2 x i64> %tmp2306}307 308define arm_aapcs_vfpcc <8 x i16> @vmovlu8(ptr %A) nounwind {309; CHECK-LE-LABEL: vmovlu8:310; CHECK-LE: @ %bb.0:311; CHECK-LE-NEXT: vld1.8 {d16}, [r0:64]312; CHECK-LE-NEXT: vmovl.u8 q0, d16313; CHECK-LE-NEXT: mov pc, lr314;315; CHECK-BE-LABEL: vmovlu8:316; CHECK-BE: @ %bb.0:317; CHECK-BE-NEXT: vld1.8 {d16}, [r0:64]318; CHECK-BE-NEXT: vmovl.u8 q8, d16319; CHECK-BE-NEXT: vrev64.16 q0, q8320; CHECK-BE-NEXT: mov pc, lr321 %tmp1 = load <8 x i8>, ptr %A322 %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>323 ret <8 x i16> %tmp2324}325 326define arm_aapcs_vfpcc <4 x i32> @vmovlu16(ptr %A) nounwind {327; CHECK-LE-LABEL: vmovlu16:328; CHECK-LE: @ %bb.0:329; CHECK-LE-NEXT: vld1.16 {d16}, [r0:64]330; CHECK-LE-NEXT: vmovl.u16 q0, d16331; CHECK-LE-NEXT: mov pc, lr332;333; CHECK-BE-LABEL: vmovlu16:334; CHECK-BE: @ %bb.0:335; CHECK-BE-NEXT: vld1.16 {d16}, [r0:64]336; CHECK-BE-NEXT: vmovl.u16 q8, d16337; CHECK-BE-NEXT: vrev64.32 q0, q8338; CHECK-BE-NEXT: mov pc, lr339 %tmp1 = load <4 x i16>, ptr %A340 %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>341 ret <4 x i32> %tmp2342}343 344define arm_aapcs_vfpcc <2 x i64> @vmovlu32(ptr %A) nounwind {345; CHECK-LABEL: vmovlu32:346; CHECK: @ %bb.0:347; CHECK-NEXT: vld1.32 {d16}, [r0:64]348; CHECK-NEXT: vmovl.u32 q0, d16349; CHECK-NEXT: mov pc, lr350 %tmp1 = load <2 x i32>, ptr %A351 %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>352 ret <2 x i64> %tmp2353}354 355define arm_aapcs_vfpcc <8 x i8> @vmovni16(ptr %A) nounwind {356; CHECK-LE-LABEL: vmovni16:357; CHECK-LE: @ %bb.0:358; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]359; CHECK-LE-NEXT: vmovn.i16 d0, q8360; CHECK-LE-NEXT: mov pc, lr361;362; CHECK-BE-LABEL: vmovni16:363; CHECK-BE: @ %bb.0:364; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0]365; CHECK-BE-NEXT: vrev64.16 q8, q8366; CHECK-BE-NEXT: vmovn.i16 d16, q8367; CHECK-BE-NEXT: vrev64.8 d0, d16368; CHECK-BE-NEXT: mov pc, lr369 %tmp1 = load <8 x i16>, ptr %A370 %tmp2 = trunc <8 x i16> %tmp1 to <8 x i8>371 ret <8 x i8> %tmp2372}373 374define arm_aapcs_vfpcc <4 x i16> @vmovni32(ptr %A) nounwind {375; CHECK-LE-LABEL: vmovni32:376; CHECK-LE: @ %bb.0:377; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]378; CHECK-LE-NEXT: vmovn.i32 d0, q8379; CHECK-LE-NEXT: mov pc, lr380;381; CHECK-BE-LABEL: vmovni32:382; CHECK-BE: @ %bb.0:383; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0]384; CHECK-BE-NEXT: vrev64.32 q8, q8385; CHECK-BE-NEXT: vmovn.i32 d16, q8386; CHECK-BE-NEXT: vrev64.16 d0, d16387; CHECK-BE-NEXT: mov pc, lr388 %tmp1 = load <4 x i32>, ptr %A389 %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>390 ret <4 x i16> %tmp2391}392 393define arm_aapcs_vfpcc <2 x i32> @vmovni64(ptr %A) nounwind {394; CHECK-LE-LABEL: vmovni64:395; CHECK-LE: @ %bb.0:396; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]397; CHECK-LE-NEXT: vmovn.i64 d0, q8398; CHECK-LE-NEXT: mov pc, lr399;400; CHECK-BE-LABEL: vmovni64:401; CHECK-BE: @ %bb.0:402; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0]403; CHECK-BE-NEXT: vmovn.i64 d16, q8404; CHECK-BE-NEXT: vrev64.32 d0, d16405; CHECK-BE-NEXT: mov pc, lr406 %tmp1 = load <2 x i64>, ptr %A407 %tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>408 ret <2 x i32> %tmp2409}410 411define arm_aapcs_vfpcc <8 x i8> @vqmovns16(ptr %A) nounwind {412; CHECK-LE-LABEL: vqmovns16:413; CHECK-LE: @ %bb.0:414; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]415; CHECK-LE-NEXT: vqmovn.s16 d0, q8416; CHECK-LE-NEXT: mov pc, lr417;418; CHECK-BE-LABEL: vqmovns16:419; CHECK-BE: @ %bb.0:420; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0]421; CHECK-BE-NEXT: vrev64.16 q8, q8422; CHECK-BE-NEXT: vqmovn.s16 d16, q8423; CHECK-BE-NEXT: vrev64.8 d0, d16424; CHECK-BE-NEXT: mov pc, lr425 %tmp1 = load <8 x i16>, ptr %A426 %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)427 ret <8 x i8> %tmp2428}429 430define arm_aapcs_vfpcc <4 x i16> @vqmovns32(ptr %A) nounwind {431; CHECK-LE-LABEL: vqmovns32:432; CHECK-LE: @ %bb.0:433; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]434; CHECK-LE-NEXT: vqmovn.s32 d0, q8435; CHECK-LE-NEXT: mov pc, lr436;437; CHECK-BE-LABEL: vqmovns32:438; CHECK-BE: @ %bb.0:439; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0]440; CHECK-BE-NEXT: vrev64.32 q8, q8441; CHECK-BE-NEXT: vqmovn.s32 d16, q8442; CHECK-BE-NEXT: vrev64.16 d0, d16443; CHECK-BE-NEXT: mov pc, lr444 %tmp1 = load <4 x i32>, ptr %A445 %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)446 ret <4 x i16> %tmp2447}448 449define arm_aapcs_vfpcc <2 x i32> @vqmovns64(ptr %A) nounwind {450; CHECK-LE-LABEL: vqmovns64:451; CHECK-LE: @ %bb.0:452; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]453; CHECK-LE-NEXT: vqmovn.s64 d0, q8454; CHECK-LE-NEXT: mov pc, lr455;456; CHECK-BE-LABEL: vqmovns64:457; CHECK-BE: @ %bb.0:458; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0]459; CHECK-BE-NEXT: vqmovn.s64 d16, q8460; CHECK-BE-NEXT: vrev64.32 d0, d16461; CHECK-BE-NEXT: mov pc, lr462 %tmp1 = load <2 x i64>, ptr %A463 %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)464 ret <2 x i32> %tmp2465}466 467define arm_aapcs_vfpcc <8 x i8> @vqmovnu16(ptr %A) nounwind {468; CHECK-LE-LABEL: vqmovnu16:469; CHECK-LE: @ %bb.0:470; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]471; CHECK-LE-NEXT: vqmovn.u16 d0, q8472; CHECK-LE-NEXT: mov pc, lr473;474; CHECK-BE-LABEL: vqmovnu16:475; CHECK-BE: @ %bb.0:476; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0]477; CHECK-BE-NEXT: vrev64.16 q8, q8478; CHECK-BE-NEXT: vqmovn.u16 d16, q8479; CHECK-BE-NEXT: vrev64.8 d0, d16480; CHECK-BE-NEXT: mov pc, lr481 %tmp1 = load <8 x i16>, ptr %A482 %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)483 ret <8 x i8> %tmp2484}485 486define arm_aapcs_vfpcc <4 x i16> @vqmovnu32(ptr %A) nounwind {487; CHECK-LE-LABEL: vqmovnu32:488; CHECK-LE: @ %bb.0:489; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]490; CHECK-LE-NEXT: vqmovn.u32 d0, q8491; CHECK-LE-NEXT: mov pc, lr492;493; CHECK-BE-LABEL: vqmovnu32:494; CHECK-BE: @ %bb.0:495; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0]496; CHECK-BE-NEXT: vrev64.32 q8, q8497; CHECK-BE-NEXT: vqmovn.u32 d16, q8498; CHECK-BE-NEXT: vrev64.16 d0, d16499; CHECK-BE-NEXT: mov pc, lr500 %tmp1 = load <4 x i32>, ptr %A501 %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)502 ret <4 x i16> %tmp2503}504 505define arm_aapcs_vfpcc <2 x i32> @vqmovnu64(ptr %A) nounwind {506; CHECK-LE-LABEL: vqmovnu64:507; CHECK-LE: @ %bb.0:508; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]509; CHECK-LE-NEXT: vqmovn.u64 d0, q8510; CHECK-LE-NEXT: mov pc, lr511;512; CHECK-BE-LABEL: vqmovnu64:513; CHECK-BE: @ %bb.0:514; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0]515; CHECK-BE-NEXT: vqmovn.u64 d16, q8516; CHECK-BE-NEXT: vrev64.32 d0, d16517; CHECK-BE-NEXT: mov pc, lr518 %tmp1 = load <2 x i64>, ptr %A519 %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)520 ret <2 x i32> %tmp2521}522 523define arm_aapcs_vfpcc <8 x i8> @vqmovuns16(ptr %A) nounwind {524; CHECK-LE-LABEL: vqmovuns16:525; CHECK-LE: @ %bb.0:526; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]527; CHECK-LE-NEXT: vqmovun.s16 d0, q8528; CHECK-LE-NEXT: mov pc, lr529;530; CHECK-BE-LABEL: vqmovuns16:531; CHECK-BE: @ %bb.0:532; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0]533; CHECK-BE-NEXT: vrev64.16 q8, q8534; CHECK-BE-NEXT: vqmovun.s16 d16, q8535; CHECK-BE-NEXT: vrev64.8 d0, d16536; CHECK-BE-NEXT: mov pc, lr537 %tmp1 = load <8 x i16>, ptr %A538 %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)539 ret <8 x i8> %tmp2540}541 542define arm_aapcs_vfpcc <4 x i16> @vqmovuns32(ptr %A) nounwind {543; CHECK-LE-LABEL: vqmovuns32:544; CHECK-LE: @ %bb.0:545; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]546; CHECK-LE-NEXT: vqmovun.s32 d0, q8547; CHECK-LE-NEXT: mov pc, lr548;549; CHECK-BE-LABEL: vqmovuns32:550; CHECK-BE: @ %bb.0:551; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0]552; CHECK-BE-NEXT: vrev64.32 q8, q8553; CHECK-BE-NEXT: vqmovun.s32 d16, q8554; CHECK-BE-NEXT: vrev64.16 d0, d16555; CHECK-BE-NEXT: mov pc, lr556 %tmp1 = load <4 x i32>, ptr %A557 %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)558 ret <4 x i16> %tmp2559}560 561define arm_aapcs_vfpcc <2 x i32> @vqmovuns64(ptr %A) nounwind {562; CHECK-LE-LABEL: vqmovuns64:563; CHECK-LE: @ %bb.0:564; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0]565; CHECK-LE-NEXT: vqmovun.s64 d0, q8566; CHECK-LE-NEXT: mov pc, lr567;568; CHECK-BE-LABEL: vqmovuns64:569; CHECK-BE: @ %bb.0:570; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0]571; CHECK-BE-NEXT: vqmovun.s64 d16, q8572; CHECK-BE-NEXT: vrev64.32 d0, d16573; CHECK-BE-NEXT: mov pc, lr574 %tmp1 = load <2 x i64>, ptr %A575 %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)576 ret <2 x i32> %tmp2577}578 579declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) nounwind readnone580declare <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32>) nounwind readnone581declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) nounwind readnone582 583declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone584declare <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32>) nounwind readnone585declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone586 587declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone588declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone589declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone590 591; Truncating vector stores are not supported. The following should not crash.592; Radar 8598391.593define arm_aapcs_vfpcc void @noTruncStore(ptr %a, ptr %b) nounwind {594; CHECK-LE-LABEL: noTruncStore:595; CHECK-LE: @ %bb.0:596; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0:128]597; CHECK-LE-NEXT: vmovn.i32 d16, q8598; CHECK-LE-NEXT: vstr d16, [r1]599; CHECK-LE-NEXT: mov pc, lr600;601; CHECK-BE-LABEL: noTruncStore:602; CHECK-BE: @ %bb.0:603; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0:128]604; CHECK-BE-NEXT: vrev64.32 q8, q8605; CHECK-BE-NEXT: vmovn.i32 d16, q8606; CHECK-BE-NEXT: vrev64.16 d16, d16607; CHECK-BE-NEXT: vstr d16, [r1]608; CHECK-BE-NEXT: mov pc, lr609 %tmp1 = load <4 x i32>, ptr %a, align 16610 %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>611 store <4 x i16> %tmp2, ptr %b, align 8612 ret void613}614 615; Use vmov.f32 to materialize f32 immediate splats616; rdar://10437054617define arm_aapcs_vfpcc void @v_mov_v2f32(ptr nocapture %p) nounwind {618; CHECK-LABEL: v_mov_v2f32:619; CHECK: @ %bb.0: @ %entry620; CHECK-NEXT: vmov.f32 d16, #-1.600000e+01621; CHECK-NEXT: vstr d16, [r0]622; CHECK-NEXT: mov pc, lr623entry:624 store <2 x float> <float -1.600000e+01, float -1.600000e+01>, ptr %p, align 4625 ret void626}627 628define arm_aapcs_vfpcc void @v_mov_v4f32(ptr nocapture %p) nounwind {629; CHECK-LE-LABEL: v_mov_v4f32:630; CHECK-LE: @ %bb.0: @ %entry631; CHECK-LE-NEXT: vmov.f32 q8, #3.100000e+01632; CHECK-LE-NEXT: vst1.32 {d16, d17}, [r0]633; CHECK-LE-NEXT: mov pc, lr634;635; CHECK-BE-LABEL: v_mov_v4f32:636; CHECK-BE: @ %bb.0: @ %entry637; CHECK-BE-NEXT: vmov.f32 q8, #3.100000e+01638; CHECK-BE-NEXT: vstmia r0, {d16, d17}639; CHECK-BE-NEXT: mov pc, lr640entry:641 store <4 x float> <float 3.100000e+01, float 3.100000e+01, float 3.100000e+01, float 3.100000e+01>, ptr %p, align 4642 ret void643}644 645define arm_aapcs_vfpcc void @v_mov_v4f32_undef(ptr nocapture %p) nounwind {646; CHECK-LE-LABEL: v_mov_v4f32_undef:647; CHECK-LE: @ %bb.0: @ %entry648; CHECK-LE-NEXT: vmov.f32 q8, #1.000000e+00649; CHECK-LE-NEXT: vld1.64 {d18, d19}, [r0]650; CHECK-LE-NEXT: vadd.f32 q8, q9, q8651; CHECK-LE-NEXT: vst1.64 {d16, d17}, [r0]652; CHECK-LE-NEXT: mov pc, lr653;654; CHECK-BE-LABEL: v_mov_v4f32_undef:655; CHECK-BE: @ %bb.0: @ %entry656; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0]657; CHECK-BE-NEXT: vmov.f32 q9, #1.000000e+00658; CHECK-BE-NEXT: vrev64.32 q8, q8659; CHECK-BE-NEXT: vadd.f32 q8, q8, q9660; CHECK-BE-NEXT: vrev64.32 q8, q8661; CHECK-BE-NEXT: vst1.64 {d16, d17}, [r0]662; CHECK-BE-NEXT: mov pc, lr663entry:664 %a = load <4 x float> , ptr %p665 %b = fadd <4 x float> %a, <float undef, float 1.0, float 1.0, float 1.0>666 store <4 x float> %b, ptr %p667 ret void668}669 670; Vector any_extends must be selected as either vmovl.u or vmovl.s.671; rdar://10723651672define arm_aapcs_vfpcc void @any_extend(<4 x i1> %x, <4 x i32> %y) nounwind ssp {673; CHECK-LE-LABEL: any_extend:674; CHECK-LE: @ %bb.0: @ %entry675; CHECK-LE-NEXT: vmov.i16 d16, #0x1676; CHECK-LE-NEXT: vand d16, d0, d16677; CHECK-LE-NEXT: vmovl.u16 q8, d16678; CHECK-LE-NEXT: vsub.i32 q8, q8, q1679; CHECK-LE-NEXT: vmovn.i32 d16, q8680; CHECK-LE-NEXT: vst1.16 {d16}, [r0]681;682; CHECK-BE-LABEL: any_extend:683; CHECK-BE: @ %bb.0: @ %entry684; CHECK-BE-NEXT: vmov.i16 d16, #0x1685; CHECK-BE-NEXT: vrev64.16 d17, d0686; CHECK-BE-NEXT: vrev64.32 q9, q1687; CHECK-BE-NEXT: vand d16, d17, d16688; CHECK-BE-NEXT: vmovl.u16 q8, d16689; CHECK-BE-NEXT: vsub.i32 q8, q8, q9690; CHECK-BE-NEXT: vmovn.i32 d16, q8691; CHECK-BE-NEXT: vst1.16 {d16}, [r0]692entry:693 %and.i186 = zext <4 x i1> %x to <4 x i32>694 %add.i185 = sub <4 x i32> %and.i186, %y695 %sub.i = sub <4 x i32> %add.i185, zeroinitializer696 %add.i = add <4 x i32> %sub.i, zeroinitializer697 %vmovn.i = trunc <4 x i32> %add.i to <4 x i16>698 tail call void @llvm.arm.neon.vst1.p0.v4i16(ptr undef, <4 x i16> %vmovn.i, i32 2)699 unreachable700}701 702define arm_aapcs_vfpcc void @v_movi8_sti8(ptr %p) {703; CHECK-LABEL: v_movi8_sti8:704; CHECK: @ %bb.0:705; CHECK-NEXT: vmov.i8 d16, #0x1706; CHECK-NEXT: vst1.8 {d16}, [r0]707; CHECK-NEXT: mov pc, lr708 call void @llvm.arm.neon.vst1.p0.v8i8(ptr %p, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, i32 1)709 ret void710}711 712define arm_aapcs_vfpcc void @v_movi8_sti16(ptr %p) {713; CHECK-LABEL: v_movi8_sti16:714; CHECK: @ %bb.0:715; CHECK-NEXT: vmov.i8 d16, #0x1716; CHECK-NEXT: vst1.16 {d16}, [r0]717; CHECK-NEXT: mov pc, lr718 %val = bitcast <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <4 x i16>719 call void @llvm.arm.neon.vst1.p0.v4i16(ptr %p, <4 x i16> %val, i32 2)720 ret void721}722 723define arm_aapcs_vfpcc void @v_movi8_stf16(ptr %p) {724; CHECK-LABEL: v_movi8_stf16:725; CHECK: @ %bb.0:726; CHECK-NEXT: vmov.i8 d16, #0x1727; CHECK-NEXT: vst1.16 {d16}, [r0]728; CHECK-NEXT: mov pc, lr729 %val = bitcast <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <4 x half>730 call void @llvm.arm.neon.vst1.p0.v4f16(ptr %p, <4 x half> %val, i32 2)731 ret void732}733 734define arm_aapcs_vfpcc void @v_movi8_sti32(ptr %p) {735; CHECK-LABEL: v_movi8_sti32:736; CHECK: @ %bb.0:737; CHECK-NEXT: vmov.i8 d16, #0x1738; CHECK-NEXT: vst1.32 {d16}, [r0]739; CHECK-NEXT: mov pc, lr740 %val = bitcast <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <2 x i32>741 call void @llvm.arm.neon.vst1.p0.v2i32(ptr %p, <2 x i32> %val, i32 4)742 ret void743}744 745define arm_aapcs_vfpcc void @v_movi8_stf32(ptr %p) {746; CHECK-LABEL: v_movi8_stf32:747; CHECK: @ %bb.0:748; CHECK-NEXT: vmov.i8 d16, #0x1749; CHECK-NEXT: vst1.32 {d16}, [r0]750; CHECK-NEXT: mov pc, lr751 %val = bitcast <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <2 x float>752 call void @llvm.arm.neon.vst1.p0.v2f32(ptr %p, <2 x float> %val, i32 4)753 ret void754}755 756define arm_aapcs_vfpcc void @v_movi8_sti64(ptr %p) {757; CHECK-LABEL: v_movi8_sti64:758; CHECK: @ %bb.0:759; CHECK-NEXT: vmov.i8 d16, #0x1760; CHECK-NEXT: vst1.64 {d16}, [r0:64]761; CHECK-NEXT: mov pc, lr762 %val = bitcast <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <1 x i64>763 call void @llvm.arm.neon.vst1.p0.v1i64(ptr %p, <1 x i64> %val, i32 8)764 ret void765}766 767define arm_aapcs_vfpcc void @v_movi16_sti16(ptr %p) {768; CHECK-LABEL: v_movi16_sti16:769; CHECK: @ %bb.0:770; CHECK-NEXT: vmov.i16 d16, #0x1771; CHECK-NEXT: vst1.16 {d16}, [r0]772; CHECK-NEXT: mov pc, lr773 call void @llvm.arm.neon.vst1.p0.v4i16(ptr %p, <4 x i16> <i16 1, i16 1, i16 1, i16 1>, i32 2)774 ret void775}776 777define arm_aapcs_vfpcc void @v_movi16_stf16(ptr %p) {778; CHECK-LABEL: v_movi16_stf16:779; CHECK: @ %bb.0:780; CHECK-NEXT: vmov.i16 d16, #0x1781; CHECK-NEXT: vst1.16 {d16}, [r0]782; CHECK-NEXT: mov pc, lr783 %val = bitcast <4 x i16> <i16 1, i16 1, i16 1, i16 1> to <4 x half>784 call void @llvm.arm.neon.vst1.p0.v4f16(ptr %p, <4 x half> %val, i32 2)785 ret void786}787 788define arm_aapcs_vfpcc void @v_movi16_sti32(ptr %p) {789; CHECK-LABEL: v_movi16_sti32:790; CHECK: @ %bb.0:791; CHECK-NEXT: vmov.i16 d16, #0x1792; CHECK-NEXT: vst1.32 {d16}, [r0]793; CHECK-NEXT: mov pc, lr794 %val = bitcast <4 x i16> <i16 1, i16 1, i16 1, i16 1> to <2 x i32>795 call void @llvm.arm.neon.vst1.p0.v2i32(ptr %p, <2 x i32> %val, i32 4)796 ret void797}798 799define arm_aapcs_vfpcc void @v_movi16_stf32(ptr %p) {800; CHECK-LABEL: v_movi16_stf32:801; CHECK: @ %bb.0:802; CHECK-NEXT: vmov.i16 d16, #0x1803; CHECK-NEXT: vst1.32 {d16}, [r0]804; CHECK-NEXT: mov pc, lr805 %val = bitcast <4 x i16> <i16 1, i16 1, i16 1, i16 1> to <2 x float>806 call void @llvm.arm.neon.vst1.p0.v2f32(ptr %p, <2 x float> %val, i32 4)807 ret void808}809 810define arm_aapcs_vfpcc void @v_movi16_sti64(ptr %p) {811; CHECK-LABEL: v_movi16_sti64:812; CHECK: @ %bb.0:813; CHECK-NEXT: vmov.i16 d16, #0x1814; CHECK-NEXT: vst1.64 {d16}, [r0:64]815; CHECK-NEXT: mov pc, lr816 %val = bitcast <4 x i16> <i16 1, i16 1, i16 1, i16 1> to <1 x i64>817 call void @llvm.arm.neon.vst1.p0.v1i64(ptr %p, <1 x i64> %val, i32 8)818 ret void819}820 821define arm_aapcs_vfpcc void @v_movi32_sti32(ptr %p) {822; CHECK-LABEL: v_movi32_sti32:823; CHECK: @ %bb.0:824; CHECK-NEXT: vmov.i32 d16, #0x1825; CHECK-NEXT: vst1.32 {d16}, [r0]826; CHECK-NEXT: mov pc, lr827 call void @llvm.arm.neon.vst1.p0.v2i32(ptr %p, <2 x i32> <i32 1, i32 1>, i32 4)828 ret void829}830 831define arm_aapcs_vfpcc void @v_movi32_stf32(ptr %p) {832; CHECK-LABEL: v_movi32_stf32:833; CHECK: @ %bb.0:834; CHECK-NEXT: vmov.i32 d16, #0x1835; CHECK-NEXT: vst1.32 {d16}, [r0]836; CHECK-NEXT: mov pc, lr837 %val = bitcast <2 x i32> <i32 1, i32 1> to <2 x float>838 call void @llvm.arm.neon.vst1.p0.v2f32(ptr %p, <2 x float> %val, i32 4)839 ret void840}841 842define arm_aapcs_vfpcc void @v_movi32_sti64(ptr %p) {843; CHECK-LABEL: v_movi32_sti64:844; CHECK: @ %bb.0:845; CHECK-NEXT: vmov.i32 d16, #0x1846; CHECK-NEXT: vst1.64 {d16}, [r0:64]847; CHECK-NEXT: mov pc, lr848 %val = bitcast <2 x i32> <i32 1, i32 1> to <1 x i64>849 call void @llvm.arm.neon.vst1.p0.v1i64(ptr %p, <1 x i64> %val, i32 8)850 ret void851}852 853define arm_aapcs_vfpcc void @v_movf32_stf32(ptr %p) {854; CHECK-LABEL: v_movf32_stf32:855; CHECK: @ %bb.0:856; CHECK-NEXT: vmov.f32 d16, #1.000000e+00857; CHECK-NEXT: vst1.32 {d16}, [r0]858; CHECK-NEXT: mov pc, lr859 call void @llvm.arm.neon.vst1.p0.v2f32(ptr %p, <2 x float> <float 1.0, float 1.0>, i32 4)860 ret void861}862 863define arm_aapcs_vfpcc void@v_movf32_sti32(ptr %p) {864; FIXME: We should use vmov.f32 instead of mov then vdup865; CHECK-LABEL: v_movf32_sti32:866; CHECK: @ %bb.0:867; CHECK-NEXT: mov r1, #1065353216868; CHECK-NEXT: vdup.32 d16, r1869; CHECK-NEXT: vst1.32 {d16}, [r0]870; CHECK-NEXT: mov pc, lr871 %val = bitcast <2 x float> <float 1.0, float 1.0> to <2 x i32>872 call void @llvm.arm.neon.vst1.p0.v2i32(ptr %p, <2 x i32> %val, i32 4)873 ret void874}875 876define arm_aapcs_vfpcc void @v_movf32_sti64(ptr %p) {877; CHECK-LE-LABEL: v_movf32_sti64:878; CHECK-LE: @ %bb.0:879; CHECK-LE-NEXT: mov r1, #1065353216880; CHECK-LE-NEXT: vdup.32 d16, r1881; CHECK-LE-NEXT: vst1.64 {d16}, [r0:64]882; CHECK-LE-NEXT: mov pc, lr883;884; FIXME: vrev is not needed here885; CHECK-BE-LABEL: v_movf32_sti64:886; CHECK-BE: @ %bb.0:887; CHECK-BE-NEXT: mov r1, #1065353216888; CHECK-BE-NEXT: vdup.32 d16, r1889; CHECK-BE-NEXT: vrev64.32 d16, d16890; CHECK-BE-NEXT: vst1.64 {d16}, [r0:64]891; CHECK-BE-NEXT: mov pc, lr892 %val = bitcast <2 x float> <float 1.0, float 1.0> to <1 x i64>893 call void @llvm.arm.neon.vst1.p0.v1i64(ptr %p, <1 x i64> %val, i32 8)894 ret void895}896 897define arm_aapcs_vfpcc void @v_movi64_sti64(ptr %p) {898; CHECK-LE-LABEL: v_movi64_sti64:899; CHECK-LE: @ %bb.0:900; CHECK-LE-NEXT: vmov.i64 d16, #0xff901; CHECK-LE-NEXT: vst1.64 {d16}, [r0:64]902; CHECK-LE-NEXT: mov pc, lr903;904; CHECK-BE-LABEL: v_movi64_sti64:905; CHECK-BE: @ %bb.0:906; CHECK-BE-NEXT: vmov.i64 d16, #0xff00000000907; CHECK-BE-NEXT: vrev64.32 d16, d16908; CHECK-BE-NEXT: vst1.64 {d16}, [r0:64]909; CHECK-BE-NEXT: mov pc, lr910 call void @llvm.arm.neon.vst1.p0.v1i64(ptr %p, <1 x i64> <i64 255>, i32 8)911 ret void912}913 914define arm_aapcs_vfpcc void @v_movQi8_sti8(ptr %p) {915; CHECK-LABEL: v_movQi8_sti8:916; CHECK: @ %bb.0:917; CHECK-NEXT: vmov.i8 q8, #0x1918; CHECK-NEXT: vst1.8 {d16, d17}, [r0]919; CHECK-NEXT: mov pc, lr920 call void @llvm.arm.neon.vst1.p0.v16i8(ptr %p, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, i32 1)921 ret void922}923 924define arm_aapcs_vfpcc void @v_movQi8_sti16(ptr %p) {925; CHECK-LABEL: v_movQi8_sti16:926; CHECK: @ %bb.0:927; CHECK-NEXT: vmov.i8 q8, #0x1928; CHECK-NEXT: vst1.16 {d16, d17}, [r0]929; CHECK-NEXT: mov pc, lr930 %val = bitcast <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <8 x i16>931 call void @llvm.arm.neon.vst1.p0.v8i16(ptr %p, <8 x i16> %val, i32 2)932 ret void933}934 935define arm_aapcs_vfpcc void @v_movQi8_stf16(ptr %p) {936; CHECK-LABEL: v_movQi8_stf16:937; CHECK: @ %bb.0:938; CHECK-NEXT: vmov.i8 q8, #0x1939; CHECK-NEXT: vst1.16 {d16, d17}, [r0]940; CHECK-NEXT: mov pc, lr941 %val = bitcast <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <8 x half>942 call void @llvm.arm.neon.vst1.p0.v8f16(ptr %p, <8 x half> %val, i32 2)943 ret void944}945 946define arm_aapcs_vfpcc void @v_movQi8_sti32(ptr %p) {947; CHECK-LABEL: v_movQi8_sti32:948; CHECK: @ %bb.0:949; CHECK-NEXT: vmov.i8 q8, #0x1950; CHECK-NEXT: vst1.32 {d16, d17}, [r0]951; CHECK-NEXT: mov pc, lr952 %val = bitcast <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <4 x i32>953 call void @llvm.arm.neon.vst1.p0.v4i32(ptr %p, <4 x i32> %val, i32 4)954 ret void955}956 957define arm_aapcs_vfpcc void @v_movQi8_stf32(ptr %p) {958; CHECK-LABEL: v_movQi8_stf32:959; CHECK: @ %bb.0:960; CHECK-NEXT: vmov.i8 q8, #0x1961; CHECK-NEXT: vst1.32 {d16, d17}, [r0]962; CHECK-NEXT: mov pc, lr963 %val = bitcast <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <4 x float>964 call void @llvm.arm.neon.vst1.p0.v4f32(ptr %p, <4 x float> %val, i32 4)965 ret void966}967 968define arm_aapcs_vfpcc void @v_movQi8_sti64(ptr %p) {969; CHECK-LABEL: v_movQi8_sti64:970; CHECK: @ %bb.0:971; CHECK-NEXT: vmov.i8 q8, #0x1972; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64]973; CHECK-NEXT: mov pc, lr974 %val = bitcast <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <2 x i64>975 call void @llvm.arm.neon.vst1.p0.v2i64(ptr %p, <2 x i64> %val, i32 8)976 ret void977}978 979define arm_aapcs_vfpcc void @v_movQi16_sti16(ptr %p) {980; CHECK-LABEL: v_movQi16_sti16:981; CHECK: @ %bb.0:982; CHECK-NEXT: vmov.i16 q8, #0x1983; CHECK-NEXT: vst1.16 {d16, d17}, [r0]984; CHECK-NEXT: mov pc, lr985 call void @llvm.arm.neon.vst1.p0.v8i16(ptr %p, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, i32 2)986 ret void987}988 989define arm_aapcs_vfpcc void @v_movQi16_stf16(ptr %p) {990; CHECK-LABEL: v_movQi16_stf16:991; CHECK: @ %bb.0:992; CHECK-NEXT: vmov.i16 q8, #0x1993; CHECK-NEXT: vst1.16 {d16, d17}, [r0]994; CHECK-NEXT: mov pc, lr995 %val = bitcast <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> to <8 x half>996 call void @llvm.arm.neon.vst1.p0.v8f16(ptr %p, <8 x half> %val, i32 2)997 ret void998}999 1000define arm_aapcs_vfpcc void @v_movQi16_sti32(ptr %p) {1001; CHECK-LABEL: v_movQi16_sti32:1002; CHECK: @ %bb.0:1003; CHECK-NEXT: vmov.i16 q8, #0x11004; CHECK-NEXT: vst1.32 {d16, d17}, [r0]1005; CHECK-NEXT: mov pc, lr1006 %val = bitcast <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> to <4 x i32>1007 call void @llvm.arm.neon.vst1.p0.v4i32(ptr %p, <4 x i32> %val, i32 4)1008 ret void1009}1010 1011define arm_aapcs_vfpcc void @v_movQi16_stf32(ptr %p) {1012; CHECK-LABEL: v_movQi16_stf32:1013; CHECK: @ %bb.0:1014; CHECK-NEXT: vmov.i16 q8, #0x11015; CHECK-NEXT: vst1.32 {d16, d17}, [r0]1016; CHECK-NEXT: mov pc, lr1017 %val = bitcast <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> to <4 x float>1018 call void @llvm.arm.neon.vst1.p0.v4f32(ptr %p, <4 x float> %val, i32 4)1019 ret void1020}1021 1022define arm_aapcs_vfpcc void @v_movQi16_sti64(ptr %p) {1023; CHECK-LABEL: v_movQi16_sti64:1024; CHECK: @ %bb.0:1025; CHECK-NEXT: vmov.i16 q8, #0x11026; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64]1027; CHECK-NEXT: mov pc, lr1028 %val = bitcast <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> to <2 x i64>1029 call void @llvm.arm.neon.vst1.p0.v2i64(ptr %p, <2 x i64> %val, i32 8)1030 ret void1031}1032 1033define arm_aapcs_vfpcc void @v_movQi32_sti32(ptr %p) {1034; CHECK-LABEL: v_movQi32_sti32:1035; CHECK: @ %bb.0:1036; CHECK-NEXT: vmov.i32 q8, #0x11037; CHECK-NEXT: vst1.32 {d16, d17}, [r0]1038; CHECK-NEXT: mov pc, lr1039 call void @llvm.arm.neon.vst1.p0.v4i32(ptr %p, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, i32 4)1040 ret void1041}1042 1043define arm_aapcs_vfpcc void @v_movQi32_stf32(ptr %p) {1044; CHECK-LABEL: v_movQi32_stf32:1045; CHECK: @ %bb.0:1046; CHECK-NEXT: vmov.i32 q8, #0x11047; CHECK-NEXT: vst1.32 {d16, d17}, [r0]1048; CHECK-NEXT: mov pc, lr1049 %val = bitcast <4 x i32> <i32 1, i32 1, i32 1, i32 1> to <4 x float>1050 call void @llvm.arm.neon.vst1.p0.v4f32(ptr %p, <4 x float> %val, i32 4)1051 ret void1052}1053 1054define arm_aapcs_vfpcc void @v_movQi32_sti64(ptr %p) {1055; CHECK-LABEL: v_movQi32_sti64:1056; CHECK: @ %bb.0:1057; CHECK-NEXT: vmov.i32 q8, #0x11058; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64]1059; CHECK-NEXT: mov pc, lr1060 %val = bitcast <4 x i32> <i32 1, i32 1, i32 1, i32 1> to <2 x i64>1061 call void @llvm.arm.neon.vst1.p0.v2i64(ptr %p, <2 x i64> %val, i32 8)1062 ret void1063}1064 1065define arm_aapcs_vfpcc void @v_movQf32_stf32(ptr %p) {1066; CHECK-LABEL: v_movQf32_stf32:1067; CHECK: @ %bb.0:1068; CHECK-NEXT: vmov.f32 q8, #1.000000e+001069; CHECK-NEXT: vst1.32 {d16, d17}, [r0]1070; CHECK-NEXT: mov pc, lr1071 call void @llvm.arm.neon.vst1.p0.v4f32(ptr %p, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, i32 4)1072 ret void1073}1074 1075define arm_aapcs_vfpcc void @v_movQf32_sti32(ptr %p) {1076; FIXME: We should use vmov.f32 instead of mov then vdup1077; CHECK-LABEL: v_movQf32_sti32:1078; CHECK: @ %bb.0:1079; CHECK-NEXT: mov r1, #10653532161080; CHECK-NEXT: vdup.32 q8, r11081; CHECK-NEXT: vst1.32 {d16, d17}, [r0]1082; CHECK-NEXT: mov pc, lr1083 %val = bitcast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0> to <4 x i32>1084 call void @llvm.arm.neon.vst1.p0.v4i32(ptr %p, <4 x i32> %val, i32 4)1085 ret void1086}1087 1088define arm_aapcs_vfpcc void @v_movQf32_sti64(ptr %p) {1089; CHECK-LE-LABEL: v_movQf32_sti64:1090; CHECK-LE: @ %bb.0:1091; CHECK-LE-NEXT: mov r1, #10653532161092; CHECK-LE-NEXT: vdup.32 q8, r11093; CHECK-LE-NEXT: vst1.64 {d16, d17}, [r0:64]1094; CHECK-LE-NEXT: mov pc, lr1095;1096; FIXME: vrev is not needed here1097; CHECK-BE-LABEL: v_movQf32_sti64:1098; CHECK-BE: @ %bb.0:1099; CHECK-BE-NEXT: mov r1, #10653532161100; CHECK-BE-NEXT: vdup.32 q8, r11101; CHECK-BE-NEXT: vrev64.32 q8, q81102; CHECK-BE-NEXT: vst1.64 {d16, d17}, [r0:64]1103; CHECK-BE-NEXT: mov pc, lr1104 %val = bitcast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0> to <2 x i64>1105 call void @llvm.arm.neon.vst1.p0.v2i64(ptr %p, <2 x i64> %val, i32 8)1106 ret void1107}1108 1109define arm_aapcs_vfpcc void @v_movQi64_sti64(ptr %p) {1110; CHECK-LE-LABEL: v_movQi64_sti64:1111; CHECK-LE: @ %bb.0:1112; CHECK-LE-NEXT: vmov.i64 q8, #0xff1113; CHECK-LE-NEXT: vst1.64 {d16, d17}, [r0:64]1114; CHECK-LE-NEXT: mov pc, lr1115;1116; CHECK-BE-LABEL: v_movQi64_sti64:1117; CHECK-BE: @ %bb.0:1118; CHECK-BE-NEXT: vmov.i64 q8, #0xff000000001119; CHECK-BE-NEXT: vrev64.32 q8, q81120; CHECK-BE-NEXT: vst1.64 {d16, d17}, [r0:64]1121; CHECK-BE-NEXT: mov pc, lr1122 call void @llvm.arm.neon.vst1.p0.v2i64(ptr %p, <2 x i64> <i64 255, i64 255>, i32 8)1123 ret void1124}1125 1126define arm_aapcs_vfpcc void @v_mvni16_sti16(ptr %p) {1127; CHECK-LABEL: v_mvni16_sti16:1128; CHECK: @ %bb.0:1129; CHECK-NEXT: vmvn.i16 d16, #0xfe1130; CHECK-NEXT: vst1.16 {d16}, [r0]1131; CHECK-NEXT: mov pc, lr1132 call void @llvm.arm.neon.vst1.p0.v4i16(ptr %p, <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281>, i32 2)1133 ret void1134}1135 1136define arm_aapcs_vfpcc void @v_mvni16_stf16(ptr %p) {1137; CHECK-LABEL: v_mvni16_stf16:1138; CHECK: @ %bb.0:1139; CHECK-NEXT: vmvn.i16 d16, #0xfe1140; CHECK-NEXT: vst1.16 {d16}, [r0]1141; CHECK-NEXT: mov pc, lr1142 %val = bitcast <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281> to <4 x half>1143 call void @llvm.arm.neon.vst1.p0.v4f16(ptr %p, <4 x half> %val, i32 2)1144 ret void1145}1146 1147define arm_aapcs_vfpcc void @v_mvni16_sti32(ptr %p) {1148; CHECK-LABEL: v_mvni16_sti32:1149; CHECK: @ %bb.0:1150; CHECK-NEXT: vmvn.i16 d16, #0xfe1151; CHECK-NEXT: vst1.32 {d16}, [r0]1152; CHECK-NEXT: mov pc, lr1153 %val = bitcast <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281> to <2 x i32>1154 call void @llvm.arm.neon.vst1.p0.v2i32(ptr %p, <2 x i32> %val, i32 4)1155 ret void1156}1157 1158define arm_aapcs_vfpcc void @v_mvni16_stf32(ptr %p) {1159; CHECK-LABEL: v_mvni16_stf32:1160; CHECK: @ %bb.0:1161; CHECK-NEXT: vmvn.i16 d16, #0xfe1162; CHECK-NEXT: vst1.32 {d16}, [r0]1163; CHECK-NEXT: mov pc, lr1164 %val = bitcast <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281> to <2 x float>1165 call void @llvm.arm.neon.vst1.p0.v2f32(ptr %p, <2 x float> %val, i32 4)1166 ret void1167}1168 1169define arm_aapcs_vfpcc void @v_mvni16_sti64(ptr %p) {1170; CHECK-LABEL: v_mvni16_sti64:1171; CHECK: @ %bb.0:1172; CHECK-NEXT: vmvn.i16 d16, #0xfe1173; CHECK-NEXT: vst1.64 {d16}, [r0:64]1174; CHECK-NEXT: mov pc, lr1175 %val = bitcast <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281> to <1 x i64>1176 call void @llvm.arm.neon.vst1.p0.v1i64(ptr %p, <1 x i64> %val, i32 8)1177 ret void1178}1179 1180define arm_aapcs_vfpcc void @v_mvni32_sti32(ptr %p) {1181; CHECK-LABEL: v_mvni32_sti32:1182; CHECK: @ %bb.0:1183; CHECK-NEXT: vmvn.i32 d16, #0xfe1184; CHECK-NEXT: vst1.32 {d16}, [r0]1185; CHECK-NEXT: mov pc, lr1186 call void @llvm.arm.neon.vst1.p0.v2i32(ptr %p, <2 x i32> <i32 4294967041, i32 4294967041>, i32 4)1187 ret void1188}1189 1190define arm_aapcs_vfpcc void @v_mvni32_stf32(ptr %p) {1191; CHECK-LABEL: v_mvni32_stf32:1192; CHECK: @ %bb.0:1193; CHECK-NEXT: vmvn.i32 d16, #0xfe1194; CHECK-NEXT: vst1.32 {d16}, [r0]1195; CHECK-NEXT: mov pc, lr1196 %val = bitcast <2 x i32> <i32 4294967041, i32 4294967041> to <2 x float>1197 call void @llvm.arm.neon.vst1.p0.v2f32(ptr %p, <2 x float> %val, i32 4)1198 ret void1199}1200 1201define arm_aapcs_vfpcc void @v_mvni32_sti64(ptr %p) {1202; CHECK-LABEL: v_mvni32_sti64:1203; CHECK: @ %bb.0:1204; CHECK-NEXT: vmvn.i32 d16, #0xfe1205; CHECK-NEXT: vst1.64 {d16}, [r0:64]1206; CHECK-NEXT: mov pc, lr1207 %val = bitcast <2 x i32> <i32 4294967041, i32 4294967041> to <1 x i64>1208 call void @llvm.arm.neon.vst1.p0.v1i64(ptr %p, <1 x i64> %val, i32 8)1209 ret void1210}1211 1212 1213define arm_aapcs_vfpcc void @v_mvnQi16_sti16(ptr %p) {1214; CHECK-LABEL: v_mvnQi16_sti16:1215; CHECK: @ %bb.0:1216; CHECK-NEXT: vmvn.i16 q8, #0xfe1217; CHECK-NEXT: vst1.16 {d16, d17}, [r0]1218; CHECK-NEXT: mov pc, lr1219 call void @llvm.arm.neon.vst1.p0.v8i16(ptr %p, <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281>, i32 2)1220 ret void1221}1222 1223define arm_aapcs_vfpcc void @v_mvnQi16_stf16(ptr %p) {1224; CHECK-LABEL: v_mvnQi16_stf16:1225; CHECK: @ %bb.0:1226; CHECK-NEXT: vmvn.i16 q8, #0xfe1227; CHECK-NEXT: vst1.16 {d16, d17}, [r0]1228; CHECK-NEXT: mov pc, lr1229 %val = bitcast <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281> to <8 x half>1230 call void @llvm.arm.neon.vst1.p0.v8f16(ptr %p, <8 x half> %val, i32 2)1231 ret void1232}1233 1234define arm_aapcs_vfpcc void @v_mvnQi16_sti32(ptr %p) {1235; CHECK-LABEL: v_mvnQi16_sti32:1236; CHECK: @ %bb.0:1237; CHECK-NEXT: vmvn.i16 q8, #0xfe1238; CHECK-NEXT: vst1.32 {d16, d17}, [r0]1239; CHECK-NEXT: mov pc, lr1240 %val = bitcast <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281> to <4 x i32>1241 call void @llvm.arm.neon.vst1.p0.v4i32(ptr %p, <4 x i32> %val, i32 4)1242 ret void1243}1244 1245define arm_aapcs_vfpcc void @v_mvnQi16_stf32(ptr %p) {1246; CHECK-LABEL: v_mvnQi16_stf32:1247; CHECK: @ %bb.0:1248; CHECK-NEXT: vmvn.i16 q8, #0xfe1249; CHECK-NEXT: vst1.32 {d16, d17}, [r0]1250; CHECK-NEXT: mov pc, lr1251 %val = bitcast <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281> to <4 x float>1252 call void @llvm.arm.neon.vst1.p0.v4f32(ptr %p, <4 x float> %val, i32 4)1253 ret void1254}1255 1256define arm_aapcs_vfpcc void @v_mvnQi16_sti64(ptr %p) {1257; CHECK-LABEL: v_mvnQi16_sti64:1258; CHECK: @ %bb.0:1259; CHECK-NEXT: vmvn.i16 q8, #0xfe1260; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64]1261; CHECK-NEXT: mov pc, lr1262 %val = bitcast <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281> to <2 x i64>1263 call void @llvm.arm.neon.vst1.p0.v2i64(ptr %p, <2 x i64> %val, i32 8)1264 ret void1265}1266 1267define arm_aapcs_vfpcc void @v_mvnQi32_sti32(ptr %p) {1268; CHECK-LABEL: v_mvnQi32_sti32:1269; CHECK: @ %bb.0:1270; CHECK-NEXT: vmvn.i32 q8, #0xfe1271; CHECK-NEXT: vst1.32 {d16, d17}, [r0]1272; CHECK-NEXT: mov pc, lr1273 call void @llvm.arm.neon.vst1.p0.v4i32(ptr %p, <4 x i32> <i32 4294967041, i32 4294967041, i32 4294967041, i32 4294967041>, i32 4)1274 ret void1275}1276 1277define arm_aapcs_vfpcc void @v_mvnQi32_stf32(ptr %p) {1278; CHECK-LABEL: v_mvnQi32_stf32:1279; CHECK: @ %bb.0:1280; CHECK-NEXT: vmvn.i32 q8, #0xfe1281; CHECK-NEXT: vst1.32 {d16, d17}, [r0]1282; CHECK-NEXT: mov pc, lr1283 %val = bitcast <4 x i32> <i32 4294967041, i32 4294967041, i32 4294967041, i32 4294967041> to <4 x float>1284 call void @llvm.arm.neon.vst1.p0.v4f32(ptr %p, <4 x float> %val, i32 4)1285 ret void1286}1287 1288define arm_aapcs_vfpcc void @v_mvnQi32_sti64(ptr %p) {1289; CHECK-LABEL: v_mvnQi32_sti64:1290; CHECK: @ %bb.0:1291; CHECK-NEXT: vmvn.i32 q8, #0xfe1292; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64]1293; CHECK-NEXT: mov pc, lr1294 %val = bitcast <4 x i32> <i32 4294967041, i32 4294967041, i32 4294967041, i32 4294967041> to <2 x i64>1295 call void @llvm.arm.neon.vst1.p0.v2i64(ptr %p, <2 x i64> %val, i32 8)1296 ret void1297}1298 1299declare void @llvm.arm.neon.vst1.p0.v8i8(ptr, <8 x i8>, i32) nounwind1300declare void @llvm.arm.neon.vst1.p0.v4i16(ptr, <4 x i16>, i32) nounwind1301declare void @llvm.arm.neon.vst1.p0.v4f16(ptr, <4 x half>, i32) nounwind1302declare void @llvm.arm.neon.vst1.p0.v2i32(ptr, <2 x i32>, i32) nounwind1303declare void @llvm.arm.neon.vst1.p0.v2f32(ptr, <2 x float>, i32) nounwind1304declare void @llvm.arm.neon.vst1.p0.v1i64(ptr, <1 x i64>, i32) nounwind1305 1306declare void @llvm.arm.neon.vst1.p0.v16i8(ptr, <16 x i8>, i32) nounwind1307declare void @llvm.arm.neon.vst1.p0.v8i16(ptr, <8 x i16>, i32) nounwind1308declare void @llvm.arm.neon.vst1.p0.v8f16(ptr, <8 x half>, i32) nounwind1309declare void @llvm.arm.neon.vst1.p0.v4i32(ptr, <4 x i32>, i32) nounwind1310declare void @llvm.arm.neon.vst1.p0.v4f32(ptr, <4 x float>, i32) nounwind1311declare void @llvm.arm.neon.vst1.p0.v2i64(ptr, <2 x i64>, i32) nounwind1312