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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=armv7a-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s3 4define <8 x i8> @vmuli8(<8 x i8> %A, <8 x i8> %B) nounwind {5; CHECK-LABEL: vmuli8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vmul.i8 d0, d0, d18; CHECK-NEXT: bx lr9 %tmp3 = mul <8 x i8> %A, %B10 ret <8 x i8> %tmp311}12 13define <4 x i16> @vmuli16(<4 x i16> %A, <4 x i16> %B) nounwind {14; CHECK-LABEL: vmuli16:15; CHECK: @ %bb.0:16; CHECK-NEXT: vmul.i16 d0, d0, d117; CHECK-NEXT: bx lr18 %tmp3 = mul <4 x i16> %A, %B19 ret <4 x i16> %tmp320}21 22define <2 x i32> @vmuli32(<2 x i32> %A, <2 x i32> %B) nounwind {23; CHECK-LABEL: vmuli32:24; CHECK: @ %bb.0:25; CHECK-NEXT: vmul.i32 d0, d0, d126; CHECK-NEXT: bx lr27 %tmp3 = mul <2 x i32> %A, %B28 ret <2 x i32> %tmp329}30 31define <2 x float> @vmulf32(<2 x float> %A, <2 x float> %B) nounwind {32; CHECK-LABEL: vmulf32:33; CHECK: @ %bb.0:34; CHECK-NEXT: vmul.f32 d0, d0, d135; CHECK-NEXT: bx lr36 %tmp3 = fmul <2 x float> %A, %B37 ret <2 x float> %tmp338}39 40define <8 x i8> @vmulp8(<8 x i8> %A, <8 x i8> %B) nounwind {41; CHECK-LABEL: vmulp8:42; CHECK: @ %bb.0:43; CHECK-NEXT: vmul.p8 d0, d0, d144; CHECK-NEXT: bx lr45 %tmp3 = call <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8> %A, <8 x i8> %B)46 ret <8 x i8> %tmp347}48 49define <16 x i8> @vmulQi8(<16 x i8> %A, <16 x i8> %B) nounwind {50; CHECK-LABEL: vmulQi8:51; CHECK: @ %bb.0:52; CHECK-NEXT: vmul.i8 q0, q0, q153; CHECK-NEXT: bx lr54 %tmp3 = mul <16 x i8> %A, %B55 ret <16 x i8> %tmp356}57 58define <8 x i16> @vmulQi16(<8 x i16> %A, <8 x i16> %B) nounwind {59; CHECK-LABEL: vmulQi16:60; CHECK: @ %bb.0:61; CHECK-NEXT: vmul.i16 q0, q0, q162; CHECK-NEXT: bx lr63 %tmp3 = mul <8 x i16> %A, %B64 ret <8 x i16> %tmp365}66 67define <4 x i32> @vmulQi32(<4 x i32> %A, <4 x i32> %B) nounwind {68; CHECK-LABEL: vmulQi32:69; CHECK: @ %bb.0:70; CHECK-NEXT: vmul.i32 q0, q0, q171; CHECK-NEXT: bx lr72 %tmp3 = mul <4 x i32> %A, %B73 ret <4 x i32> %tmp374}75 76define <4 x float> @vmulQf32(<4 x float> %A, <4 x float> %B) nounwind {77; CHECK-LABEL: vmulQf32:78; CHECK: @ %bb.0:79; CHECK-NEXT: vmul.f32 q0, q0, q180; CHECK-NEXT: bx lr81 %tmp3 = fmul <4 x float> %A, %B82 ret <4 x float> %tmp383}84 85define <16 x i8> @vmulQp8(<16 x i8> %A, <16 x i8> %B) nounwind {86; CHECK-LABEL: vmulQp8:87; CHECK: @ %bb.0:88; CHECK-NEXT: vmul.p8 q0, q0, q189; CHECK-NEXT: bx lr90 %tmp3 = call <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8> %A, <16 x i8> %B)91 ret <16 x i8> %tmp392}93 94declare <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone95declare <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone96 97define arm_aapcs_vfpcc <2 x float> @test_vmul_lanef32(<2 x float> %arg0_float32x2_t, <2 x float> %arg1_float32x2_t) nounwind readnone {98; CHECK-LABEL: test_vmul_lanef32:99; CHECK: @ %bb.0: @ %entry100; CHECK-NEXT: vmul.f32 d0, d0, d1[0]101; CHECK-NEXT: bx lr102entry:103 %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <2 x i32> zeroinitializer ; <<2 x float>> [#uses=1]104 %1 = fmul <2 x float> %0, %arg0_float32x2_t ; <<2 x float>> [#uses=1]105 ret <2 x float> %1106}107 108define arm_aapcs_vfpcc <4 x i16> @test_vmul_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {109; CHECK-LABEL: test_vmul_lanes16:110; CHECK: @ %bb.0: @ %entry111; CHECK-NEXT: vmul.i16 d0, d0, d1[1]112; CHECK-NEXT: bx lr113entry:114 %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses$115 %1 = mul <4 x i16> %0, %arg0_int16x4_t ; <<4 x i16>> [#uses=1]116 ret <4 x i16> %1117}118 119define arm_aapcs_vfpcc <2 x i32> @test_vmul_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {120; CHECK-LABEL: test_vmul_lanes32:121; CHECK: @ %bb.0: @ %entry122; CHECK-NEXT: vmul.i32 d0, d0, d1[1]123; CHECK-NEXT: bx lr124entry:125 %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]126 %1 = mul <2 x i32> %0, %arg0_int32x2_t ; <<2 x i32>> [#uses=1]127 ret <2 x i32> %1128}129 130define arm_aapcs_vfpcc <4 x float> @test_vmulQ_lanef32(<4 x float> %arg0_float32x4_t, <2 x float> %arg1_float32x2_t) nounwind readnone {131; CHECK-LABEL: test_vmulQ_lanef32:132; CHECK: @ %bb.0: @ %entry133; CHECK-NEXT: vmul.f32 q0, q0, d2[1]134; CHECK-NEXT: bx lr135entry:136 %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>$137 %1 = fmul <4 x float> %0, %arg0_float32x4_t ; <<4 x float>> [#uses=1]138 ret <4 x float> %1139}140 141define arm_aapcs_vfpcc <8 x i16> @test_vmulQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {142; CHECK-LABEL: test_vmulQ_lanes16:143; CHECK: @ %bb.0: @ %entry144; CHECK-NEXT: vmul.i16 q0, q0, d2[1]145; CHECK-NEXT: bx lr146entry:147 %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>148 %1 = mul <8 x i16> %0, %arg0_int16x8_t ; <<8 x i16>> [#uses=1]149 ret <8 x i16> %1150}151 152define arm_aapcs_vfpcc <4 x i32> @test_vmulQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {153; CHECK-LABEL: test_vmulQ_lanes32:154; CHECK: @ %bb.0: @ %entry155; CHECK-NEXT: vmul.i32 q0, q0, d2[1]156; CHECK-NEXT: bx lr157entry:158 %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses$159 %1 = mul <4 x i32> %0, %arg0_int32x4_t ; <<4 x i32>> [#uses=1]160 ret <4 x i32> %1161}162 163define <8 x i16> @vmulls8(<8 x i8> %A, <8 x i8> %B) nounwind {164; CHECK-LABEL: vmulls8:165; CHECK: @ %bb.0:166; CHECK-NEXT: vmull.s8 q0, d0, d1167; CHECK-NEXT: bx lr168 %tmp3 = sext <8 x i8> %A to <8 x i16>169 %tmp4 = sext <8 x i8> %B to <8 x i16>170 %tmp5 = mul <8 x i16> %tmp3, %tmp4171 ret <8 x i16> %tmp5172}173 174define <8 x i16> @vmulls8_int(<8 x i8> %A, <8 x i8> %B) nounwind {175; CHECK-LABEL: vmulls8_int:176; CHECK: @ %bb.0:177; CHECK-NEXT: vmull.s8 q0, d0, d1178; CHECK-NEXT: bx lr179 %tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %A, <8 x i8> %B)180 ret <8 x i16> %tmp3181}182 183define <4 x i32> @vmulls16(<4 x i16> %A, <4 x i16> %B) nounwind {184; CHECK-LABEL: vmulls16:185; CHECK: @ %bb.0:186; CHECK-NEXT: vmull.s16 q0, d0, d1187; CHECK-NEXT: bx lr188 %tmp3 = sext <4 x i16> %A to <4 x i32>189 %tmp4 = sext <4 x i16> %B to <4 x i32>190 %tmp5 = mul <4 x i32> %tmp3, %tmp4191 ret <4 x i32> %tmp5192}193 194define <4 x i32> @vmulls16_int(<4 x i16> %A, <4 x i16> %B) nounwind {195; CHECK-LABEL: vmulls16_int:196; CHECK: @ %bb.0:197; CHECK-NEXT: vmull.s16 q0, d0, d1198; CHECK-NEXT: bx lr199 %tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %A, <4 x i16> %B)200 ret <4 x i32> %tmp3201}202 203define <2 x i64> @vmulls32(<2 x i32> %A, <2 x i32> %B) nounwind {204; CHECK-LABEL: vmulls32:205; CHECK: @ %bb.0:206; CHECK-NEXT: vmull.s32 q0, d0, d1207; CHECK-NEXT: bx lr208 %tmp3 = sext <2 x i32> %A to <2 x i64>209 %tmp4 = sext <2 x i32> %B to <2 x i64>210 %tmp5 = mul <2 x i64> %tmp3, %tmp4211 ret <2 x i64> %tmp5212}213 214define <2 x i64> @vmulls32_int(<2 x i32> %A, <2 x i32> %B) nounwind {215; CHECK-LABEL: vmulls32_int:216; CHECK: @ %bb.0:217; CHECK-NEXT: vmull.s32 q0, d0, d1218; CHECK-NEXT: bx lr219 %tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %A, <2 x i32> %B)220 ret <2 x i64> %tmp3221}222 223define <8 x i16> @vmullu8(<8 x i8> %A, <8 x i8> %B) nounwind {224; CHECK-LABEL: vmullu8:225; CHECK: @ %bb.0:226; CHECK-NEXT: vmull.u8 q0, d0, d1227; CHECK-NEXT: bx lr228 %tmp3 = zext <8 x i8> %A to <8 x i16>229 %tmp4 = zext <8 x i8> %B to <8 x i16>230 %tmp5 = mul <8 x i16> %tmp3, %tmp4231 ret <8 x i16> %tmp5232}233 234define <8 x i16> @vmullu8_int(<8 x i8> %A, <8 x i8> %B) nounwind {235; CHECK-LABEL: vmullu8_int:236; CHECK: @ %bb.0:237; CHECK-NEXT: vmull.u8 q0, d0, d1238; CHECK-NEXT: bx lr239 %tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %A, <8 x i8> %B)240 ret <8 x i16> %tmp3241}242 243define <4 x i32> @vmullu16(<4 x i16> %A, <4 x i16> %B) nounwind {244; CHECK-LABEL: vmullu16:245; CHECK: @ %bb.0:246; CHECK-NEXT: vmull.u16 q0, d0, d1247; CHECK-NEXT: bx lr248 %tmp3 = zext <4 x i16> %A to <4 x i32>249 %tmp4 = zext <4 x i16> %B to <4 x i32>250 %tmp5 = mul <4 x i32> %tmp3, %tmp4251 ret <4 x i32> %tmp5252}253 254define <4 x i32> @vmullu16_int(<4 x i16> %A, <4 x i16> %B) nounwind {255; CHECK-LABEL: vmullu16_int:256; CHECK: @ %bb.0:257; CHECK-NEXT: vmull.u16 q0, d0, d1258; CHECK-NEXT: bx lr259 %tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %A, <4 x i16> %B)260 ret <4 x i32> %tmp3261}262 263define <2 x i64> @vmullu32(<2 x i32> %A, <2 x i32> %B) nounwind {264; CHECK-LABEL: vmullu32:265; CHECK: @ %bb.0:266; CHECK-NEXT: vmull.u32 q0, d0, d1267; CHECK-NEXT: bx lr268 %tmp3 = zext <2 x i32> %A to <2 x i64>269 %tmp4 = zext <2 x i32> %B to <2 x i64>270 %tmp5 = mul <2 x i64> %tmp3, %tmp4271 ret <2 x i64> %tmp5272}273 274define <2 x i64> @vmullu32_int(<2 x i32> %A, <2 x i32> %B) nounwind {275; CHECK-LABEL: vmullu32_int:276; CHECK: @ %bb.0:277; CHECK-NEXT: vmull.u32 q0, d0, d1278; CHECK-NEXT: bx lr279 %tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %A, <2 x i32> %B)280 ret <2 x i64> %tmp3281}282 283define <8 x i16> @vmulla8(<8 x i8> %A, <8 x i8> %B) nounwind {284; CHECK-LABEL: vmulla8:285; CHECK: @ %bb.0:286; CHECK-NEXT: vmull.u8 q0, d0, d1287; CHECK-NEXT: vbic.i16 q0, #0xff00288; CHECK-NEXT: bx lr289 %tmp3 = zext <8 x i8> %A to <8 x i16>290 %tmp4 = zext <8 x i8> %B to <8 x i16>291 %tmp5 = mul <8 x i16> %tmp3, %tmp4292 %and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>293 ret <8 x i16> %and294}295 296define <4 x i32> @vmulla16(<4 x i16> %A, <4 x i16> %B) nounwind {297; CHECK-LABEL: vmulla16:298; CHECK: @ %bb.0:299; CHECK-NEXT: vmull.u16 q8, d0, d1300; CHECK-NEXT: vmov.i32 q9, #0xffff301; CHECK-NEXT: vand q0, q8, q9302; CHECK-NEXT: bx lr303 %tmp3 = zext <4 x i16> %A to <4 x i32>304 %tmp4 = zext <4 x i16> %B to <4 x i32>305 %tmp5 = mul <4 x i32> %tmp3, %tmp4306 %and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535>307 ret <4 x i32> %and308}309 310define <2 x i64> @vmulla32(<2 x i32> %A, <2 x i32> %B) nounwind {311; CHECK-LABEL: vmulla32:312; CHECK: @ %bb.0:313; CHECK-NEXT: vmull.u32 q8, d0, d1314; CHECK-NEXT: vmov.i64 q9, #0xffffffff315; CHECK-NEXT: vand q0, q8, q9316; CHECK-NEXT: bx lr317 %tmp3 = zext <2 x i32> %A to <2 x i64>318 %tmp4 = zext <2 x i32> %B to <2 x i64>319 %tmp5 = mul <2 x i64> %tmp3, %tmp4320 %and = and <2 x i64> %tmp5, <i64 4294967295, i64 4294967295>321 ret <2 x i64> %and322}323 324define <8 x i16> @vmullp8(<8 x i8> %A, <8 x i8> %B) nounwind {325; CHECK-LABEL: vmullp8:326; CHECK: @ %bb.0:327; CHECK-NEXT: vmull.p8 q0, d0, d1328; CHECK-NEXT: bx lr329 %tmp3 = call <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8> %A, <8 x i8> %B)330 ret <8 x i16> %tmp3331}332 333define arm_aapcs_vfpcc <4 x i32> @test_vmull_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {334; CHECK-LABEL: test_vmull_lanes16:335; CHECK: @ %bb.0: @ %entry336; CHECK-NEXT: vmull.s16 q0, d0, d1[1]337; CHECK-NEXT: bx lr338entry:339 %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]340 %1 = sext <4 x i16> %arg0_int16x4_t to <4 x i32>341 %2 = sext <4 x i16> %0 to <4 x i32>342 %3 = mul <4 x i32> %1, %2343 ret <4 x i32> %3344}345 346define arm_aapcs_vfpcc <4 x i32> @test_vmull_lanes16_int(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {347; CHECK-LABEL: test_vmull_lanes16_int:348; CHECK: @ %bb.0: @ %entry349; CHECK-NEXT: vmull.s16 q0, d0, d1[1]350; CHECK-NEXT: bx lr351entry:352 %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]353 %1 = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]354 ret <4 x i32> %1355}356 357define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {358; CHECK-LABEL: test_vmull_lanes32:359; CHECK: @ %bb.0: @ %entry360; CHECK-NEXT: vmull.s32 q0, d0, d1[1]361; CHECK-NEXT: bx lr362entry:363 %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]364 %1 = sext <2 x i32> %arg0_int32x2_t to <2 x i64>365 %2 = sext <2 x i32> %0 to <2 x i64>366 %3 = mul <2 x i64> %1, %2367 ret <2 x i64> %3368}369 370define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanes32_int(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {371; CHECK-LABEL: test_vmull_lanes32_int:372; CHECK: @ %bb.0: @ %entry373; CHECK-NEXT: vmull.s32 q0, d0, d1[1]374; CHECK-NEXT: bx lr375entry:376 %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]377 %1 = tail call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]378 ret <2 x i64> %1379}380 381define arm_aapcs_vfpcc <4 x i32> @test_vmull_laneu16(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone {382; CHECK-LABEL: test_vmull_laneu16:383; CHECK: @ %bb.0: @ %entry384; CHECK-NEXT: vmull.u16 q0, d0, d1[1]385; CHECK-NEXT: bx lr386entry:387 %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]388 %1 = zext <4 x i16> %arg0_uint16x4_t to <4 x i32>389 %2 = zext <4 x i16> %0 to <4 x i32>390 %3 = mul <4 x i32> %1, %2391 ret <4 x i32> %3392}393 394define arm_aapcs_vfpcc <4 x i32> @test_vmull_laneu16_int(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone {395; CHECK-LABEL: test_vmull_laneu16_int:396; CHECK: @ %bb.0: @ %entry397; CHECK-NEXT: vmull.u16 q0, d0, d1[1]398; CHECK-NEXT: bx lr399entry:400 %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]401 %1 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %arg0_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]402 ret <4 x i32> %1403}404 405define arm_aapcs_vfpcc <2 x i64> @test_vmull_laneu32(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone {406; CHECK-LABEL: test_vmull_laneu32:407; CHECK: @ %bb.0: @ %entry408; CHECK-NEXT: vmull.u32 q0, d0, d1[1]409; CHECK-NEXT: bx lr410entry:411 %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]412 %1 = zext <2 x i32> %arg0_uint32x2_t to <2 x i64>413 %2 = zext <2 x i32> %0 to <2 x i64>414 %3 = mul <2 x i64> %1, %2415 ret <2 x i64> %3416}417 418define arm_aapcs_vfpcc <2 x i64> @test_vmull_laneu32_int(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone {419; CHECK-LABEL: test_vmull_laneu32_int:420; CHECK: @ %bb.0: @ %entry421; CHECK-NEXT: vmull.u32 q0, d0, d1[1]422; CHECK-NEXT: bx lr423entry:424 %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]425 %1 = tail call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %arg0_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]426 ret <2 x i64> %1427}428 429define arm_aapcs_vfpcc <4 x i32> @test_vmull_lanea16(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone {430; CHECK-LABEL: test_vmull_lanea16:431; CHECK: @ %bb.0: @ %entry432; CHECK-NEXT: vmull.u16 q8, d0, d1[1]433; CHECK-NEXT: vmov.i32 q9, #0xffff434; CHECK-NEXT: vand q0, q8, q9435; CHECK-NEXT: bx lr436entry:437 %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]438 %1 = zext <4 x i16> %arg0_uint16x4_t to <4 x i32>439 %2 = zext <4 x i16> %0 to <4 x i32>440 %3 = mul <4 x i32> %1, %2441 %and = and <4 x i32> %3, <i32 65535, i32 65535, i32 65535, i32 65535>442 ret <4 x i32> %and443}444 445define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanea32(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone {446; CHECK-LABEL: test_vmull_lanea32:447; CHECK: @ %bb.0: @ %entry448; CHECK-NEXT: vmull.u32 q8, d0, d1[1]449; CHECK-NEXT: vmov.i64 q9, #0xffffffff450; CHECK-NEXT: vand q0, q8, q9451; CHECK-NEXT: bx lr452entry:453 %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]454 %1 = zext <2 x i32> %arg0_uint32x2_t to <2 x i64>455 %2 = zext <2 x i32> %0 to <2 x i64>456 %3 = mul <2 x i64> %1, %2457 %and = and <2 x i64> %3, <i64 4294967295, i64 4294967295>458 ret <2 x i64> %and459}460 461declare <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone462declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone463declare <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone464 465declare <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone466declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone467declare <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone468 469declare <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8>, <8 x i8>) nounwind readnone470 471 472; Radar 8687140473; VMULL needs to recognize BUILD_VECTORs with sign/zero-extended elements.474 475define <8 x i16> @vmull_extvec_s8(<8 x i8> %arg) nounwind {476; CHECK-LABEL: vmull_extvec_s8:477; CHECK: @ %bb.0:478; CHECK-NEXT: vmov.i8 d16, #0xf4479; CHECK-NEXT: vmull.s8 q0, d0, d16480; CHECK-NEXT: bx lr481 %tmp3 = sext <8 x i8> %arg to <8 x i16>482 %tmp4 = mul <8 x i16> %tmp3, <i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12>483 ret <8 x i16> %tmp4484}485 486define <8 x i16> @vmull_extvec_u8(<8 x i8> %arg) nounwind {487; CHECK-LABEL: vmull_extvec_u8:488; CHECK: @ %bb.0:489; CHECK-NEXT: vmov.i8 d16, #0xc490; CHECK-NEXT: vmull.u8 q0, d0, d16491; CHECK-NEXT: bx lr492 %tmp3 = zext <8 x i8> %arg to <8 x i16>493 %tmp4 = mul <8 x i16> %tmp3, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>494 ret <8 x i16> %tmp4495}496 497define <8 x i16> @vmull_noextvec_s8(<8 x i8> %arg) nounwind {498; Do not use VMULL if the BUILD_VECTOR element values are too big.499; CHECK-LABEL: vmull_noextvec_s8:500; CHECK: @ %bb.0:501; CHECK-NEXT: vmovl.s8 q8, d0502; CHECK-NEXT: adr r0, .LCPI44_0503; CHECK-NEXT: vld1.64 {d18, d19}, [r0:128]504; CHECK-NEXT: vmul.i16 q0, q8, q9505; CHECK-NEXT: bx lr506; CHECK-NEXT: .p2align 4507; CHECK-NEXT: @ %bb.1:508; CHECK-NEXT: .LCPI44_0:509; CHECK-NEXT: .short 64537 @ 0xfc19510; CHECK-NEXT: .short 64537 @ 0xfc19511; CHECK-NEXT: .short 64537 @ 0xfc19512; CHECK-NEXT: .short 64537 @ 0xfc19513; CHECK-NEXT: .short 64537 @ 0xfc19514; CHECK-NEXT: .short 64537 @ 0xfc19515; CHECK-NEXT: .short 64537 @ 0xfc19516; CHECK-NEXT: .short 64537 @ 0xfc19517 %tmp3 = sext <8 x i8> %arg to <8 x i16>518 %tmp4 = mul <8 x i16> %tmp3, <i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999>519 ret <8 x i16> %tmp4520}521 522define <8 x i16> @vmull_noextvec_u8(<8 x i8> %arg) nounwind {523; Do not use VMULL if the BUILD_VECTOR element values are too big.524; CHECK-LABEL: vmull_noextvec_u8:525; CHECK: @ %bb.0:526; CHECK-NEXT: vmovl.u8 q8, d0527; CHECK-NEXT: adr r0, .LCPI45_0528; CHECK-NEXT: vld1.64 {d18, d19}, [r0:128]529; CHECK-NEXT: vmul.i16 q0, q8, q9530; CHECK-NEXT: bx lr531; CHECK-NEXT: .p2align 4532; CHECK-NEXT: @ %bb.1:533; CHECK-NEXT: .LCPI45_0:534; CHECK-NEXT: .short 999 @ 0x3e7535; CHECK-NEXT: .short 999 @ 0x3e7536; CHECK-NEXT: .short 999 @ 0x3e7537; CHECK-NEXT: .short 999 @ 0x3e7538; CHECK-NEXT: .short 999 @ 0x3e7539; CHECK-NEXT: .short 999 @ 0x3e7540; CHECK-NEXT: .short 999 @ 0x3e7541; CHECK-NEXT: .short 999 @ 0x3e7542 %tmp3 = zext <8 x i8> %arg to <8 x i16>543 %tmp4 = mul <8 x i16> %tmp3, <i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999>544 ret <8 x i16> %tmp4545}546 547define <4 x i32> @vmull_extvec_s16(<4 x i16> %arg) nounwind {548; CHECK-LABEL: vmull_extvec_s16:549; CHECK: @ %bb.0:550; CHECK-NEXT: vmvn.i16 d16, #0xb551; CHECK-NEXT: vmull.s16 q0, d0, d16552; CHECK-NEXT: bx lr553 %tmp3 = sext <4 x i16> %arg to <4 x i32>554 %tmp4 = mul <4 x i32> %tmp3, <i32 -12, i32 -12, i32 -12, i32 -12>555 ret <4 x i32> %tmp4556}557 558define <4 x i32> @vmull_extvec_u16(<4 x i16> %arg) nounwind {559; CHECK-LABEL: vmull_extvec_u16:560; CHECK: @ %bb.0:561; CHECK-NEXT: vldr d16, .LCPI47_0562; CHECK-NEXT: vmull.u16 q0, d0, d16563; CHECK-NEXT: bx lr564; CHECK-NEXT: .p2align 3565; CHECK-NEXT: @ %bb.1:566; CHECK-NEXT: .LCPI47_0:567; CHECK-NEXT: .short 1234 @ 0x4d2568; CHECK-NEXT: .short 1234 @ 0x4d2569; CHECK-NEXT: .short 1234 @ 0x4d2570; CHECK-NEXT: .short 1234 @ 0x4d2571 %tmp3 = zext <4 x i16> %arg to <4 x i32>572 %tmp4 = mul <4 x i32> %tmp3, <i32 1234, i32 1234, i32 1234, i32 1234>573 ret <4 x i32> %tmp4574}575 576define <2 x i64> @vmull_extvec_s32(<2 x i32> %arg) nounwind {577; CHECK-LABEL: vmull_extvec_s32:578; CHECK: @ %bb.0:579; CHECK-NEXT: vldr d16, .LCPI48_0580; CHECK-NEXT: vmull.s32 q0, d0, d16581; CHECK-NEXT: bx lr582; CHECK-NEXT: .p2align 3583; CHECK-NEXT: @ %bb.1:584; CHECK-NEXT: .LCPI48_0:585; CHECK-NEXT: .long 4294966062 @ 0xfffffb2e586; CHECK-NEXT: .long 4294966062 @ 0xfffffb2e587 %tmp3 = sext <2 x i32> %arg to <2 x i64>588 %tmp4 = mul <2 x i64> %tmp3, <i64 -1234, i64 -1234>589 ret <2 x i64> %tmp4590}591 592define <2 x i64> @vmull_extvec_u32(<2 x i32> %arg) nounwind {593; CHECK-LABEL: vmull_extvec_u32:594; CHECK: @ %bb.0:595; CHECK-NEXT: vldr d16, .LCPI49_0596; CHECK-NEXT: vmull.u32 q0, d0, d16597; CHECK-NEXT: bx lr598; CHECK-NEXT: .p2align 3599; CHECK-NEXT: @ %bb.1:600; CHECK-NEXT: .LCPI49_0:601; CHECK-NEXT: .long 1234 @ 0x4d2602; CHECK-NEXT: .long 1234 @ 0x4d2603 %tmp3 = zext <2 x i32> %arg to <2 x i64>604 %tmp4 = mul <2 x i64> %tmp3, <i64 1234, i64 1234>605 ret <2 x i64> %tmp4606}607 608; rdar://9197392609define void @distribute(ptr %dst, ptr %src, i32 %mul) nounwind {610; CHECK-LABEL: distribute:611; CHECK: @ %bb.0: @ %entry612; CHECK-NEXT: vld1.8 {d16, d17}, [r1]613; CHECK-NEXT: vdup.8 d18, r2614; CHECK-NEXT: vmull.u8 q10, d17, d18615; CHECK-NEXT: vmlal.u8 q10, d16, d18616; CHECK-NEXT: vst1.16 {d20, d21}, [r0]617; CHECK-NEXT: bx lr618entry:619 %0 = trunc i32 %mul to i8620 %1 = insertelement <8 x i8> undef, i8 %0, i32 0621 %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer622 %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr %src, i32 1)623 %4 = bitcast <16 x i8> %3 to <2 x double>624 %5 = extractelement <2 x double> %4, i32 1625 %6 = bitcast double %5 to <8 x i8>626 %7 = zext <8 x i8> %6 to <8 x i16>627 %8 = zext <8 x i8> %2 to <8 x i16>628 %9 = extractelement <2 x double> %4, i32 0629 %10 = bitcast double %9 to <8 x i8>630 %11 = zext <8 x i8> %10 to <8 x i16>631 %12 = add <8 x i16> %7, %11632 %13 = mul <8 x i16> %12, %8633 tail call void @llvm.arm.neon.vst1.p0.v8i16(ptr %dst, <8 x i16> %13, i32 2)634 ret void635}636 637declare <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr, i32) nounwind readonly638 639declare void @llvm.arm.neon.vst1.p0.v8i16(ptr, <8 x i16>, i32) nounwind640 641; Take advantage of the Cortex-A8 multiplier accumulator forward.642 643%struct.uint8x8_t = type { <8 x i8> }644 645define void @distribute2(ptr nocapture %dst, ptr %src, i32 %mul) nounwind {646; CHECK-LABEL: distribute2:647; CHECK: @ %bb.0: @ %entry648; CHECK-NEXT: vld1.8 {d16, d17}, [r1]649; CHECK-NEXT: vadd.i8 d16, d17, d16650; CHECK-NEXT: vdup.8 d17, r2651; CHECK-NEXT: vmul.i8 d16, d16, d17652; CHECK-NEXT: vstr d16, [r0]653; CHECK-NEXT: bx lr654entry:655 %0 = trunc i32 %mul to i8656 %1 = insertelement <8 x i8> undef, i8 %0, i32 0657 %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer658 %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr %src, i32 1)659 %4 = bitcast <16 x i8> %3 to <2 x double>660 %5 = extractelement <2 x double> %4, i32 1661 %6 = bitcast double %5 to <8 x i8>662 %7 = extractelement <2 x double> %4, i32 0663 %8 = bitcast double %7 to <8 x i8>664 %9 = add <8 x i8> %6, %8665 %10 = mul <8 x i8> %9, %2666 store <8 x i8> %10, ptr %dst, align 8667 ret void668}669 670define void @distribute2_commutative(ptr nocapture %dst, ptr %src, i32 %mul) nounwind {671; CHECK-LABEL: distribute2_commutative:672; CHECK: @ %bb.0: @ %entry673; CHECK-NEXT: vld1.8 {d16, d17}, [r1]674; CHECK-NEXT: vadd.i8 d16, d17, d16675; CHECK-NEXT: vdup.8 d17, r2676; CHECK-NEXT: vmul.i8 d16, d17, d16677; CHECK-NEXT: vstr d16, [r0]678; CHECK-NEXT: bx lr679entry:680 %0 = trunc i32 %mul to i8681 %1 = insertelement <8 x i8> undef, i8 %0, i32 0682 %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer683 %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr %src, i32 1)684 %4 = bitcast <16 x i8> %3 to <2 x double>685 %5 = extractelement <2 x double> %4, i32 1686 %6 = bitcast double %5 to <8 x i8>687 %7 = extractelement <2 x double> %4, i32 0688 %8 = bitcast double %7 to <8 x i8>689 %9 = add <8 x i8> %6, %8690 %10 = mul <8 x i8> %2, %9691 store <8 x i8> %10, ptr %dst, align 8692 ret void693}694 695define <8 x i8> @no_distribute(<8 x i8> %a, <8 x i8> %b) nounwind {696; CHECK-LABEL: no_distribute:697; CHECK: @ %bb.0: @ %entry698; CHECK-NEXT: vadd.i8 d16, d0, d1699; CHECK-NEXT: vmul.i8 d0, d16, d16700; CHECK-NEXT: bx lr701entry:702 %0 = add <8 x i8> %a, %b703 %1 = mul <8x i8> %0, %0704 ret <8 x i8> %1705}706 707; If one operand has a zero-extend and the other a sign-extend, vmull708; cannot be used.709define i16 @vmullWithInconsistentExtensions(<8 x i8> %vec) {710; CHECK-LABEL: vmullWithInconsistentExtensions:711; CHECK: @ %bb.0:712; CHECK-NEXT: vmovl.s8 q8, d0713; CHECK-NEXT: vmov.i16 q9, #0xff714; CHECK-NEXT: vmul.i16 q8, q8, q9715; CHECK-NEXT: vmov.u16 r0, d16[0]716; CHECK-NEXT: bx lr717 %1 = sext <8 x i8> %vec to <8 x i16>718 %2 = mul <8 x i16> %1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>719 %3 = extractelement <8 x i16> %2, i32 0720 ret i16 %3721}722 723; A constant build_vector created for a vmull with half-width elements must724; not introduce illegal types. <rdar://problem/11324364>725define void @vmull_buildvector() nounwind optsize ssp align 2 {726; CHECK-LABEL: vmull_buildvector:727; CHECK: @ %bb.0: @ %entry728entry:729 br i1 undef, label %for.end179, label %for.body.lr.ph730 731for.body.lr.ph: ; preds = %entry732 br label %for.body733 734for.cond.loopexit: ; preds = %for.body33, %for.body735 br i1 undef, label %for.end179, label %for.body736 737for.body: ; preds = %for.cond.loopexit, %for.body.lr.ph738 br i1 undef, label %for.cond.loopexit, label %for.body33.lr.ph739 740for.body33.lr.ph: ; preds = %for.body741 %.sub = select i1 undef, i32 0, i32 undef742 br label %for.body33743 744for.body33: ; preds = %for.body33, %for.body33.lr.ph745 %add45 = add i32 undef, undef746 %vld155 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0(ptr undef, i32 1)747 %0 = load ptr, ptr undef, align 4748 %shuffle.i250 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer749 %1 = bitcast <1 x i64> %shuffle.i250 to <8 x i8>750 %vmovl.i249 = zext <8 x i8> %1 to <8 x i16>751 %shuffle.i246 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer752 %shuffle.i240 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> <i32 1>753 %2 = bitcast <1 x i64> %shuffle.i240 to <8 x i8>754 %3 = bitcast <16 x i8> undef to <2 x i64>755 %vmovl.i237 = zext <8 x i8> undef to <8 x i16>756 %shuffle.i234 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer757 %shuffle.i226 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer758 %vmovl.i225 = zext <8 x i8> undef to <8 x i16>759 %mul.i223 = mul <8 x i16> %vmovl.i249, %vmovl.i249760 %vshl_n = shl <8 x i16> %mul.i223, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>761 %vqsub2.i216 = tail call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>, <8 x i16> %vshl_n) nounwind762 %mul.i209 = mul <8 x i16> undef, <i16 80, i16 80, i16 80, i16 80, i16 80, i16 80, i16 80, i16 80>763 %vshr_n130 = lshr <8 x i16> undef, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>764 %vshr_n134 = lshr <8 x i16> %mul.i209, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>765 %sub.i205 = sub <8 x i16> <i16 80, i16 80, i16 80, i16 80, i16 80, i16 80, i16 80, i16 80>, %vshr_n130766 %sub.i203 = sub <8 x i16> <i16 80, i16 80, i16 80, i16 80, i16 80, i16 80, i16 80, i16 80>, %vshr_n134767 %add.i200 = add <8 x i16> %sub.i205, <i16 96, i16 96, i16 96, i16 96, i16 96, i16 96, i16 96, i16 96>768 %add.i198 = add <8 x i16> %add.i200, %sub.i203769 %mul.i194 = mul <8 x i16> %add.i198, %vmovl.i237770 %mul.i191 = mul <8 x i16> %vshr_n130, undef771 %add.i192 = add <8 x i16> %mul.i191, %mul.i194772 %mul.i187 = mul <8 x i16> %vshr_n134, undef773 %add.i188 = add <8 x i16> %mul.i187, %add.i192774 %mul.i185 = mul <8 x i16> undef, undef775 %add.i186 = add <8 x i16> %mul.i185, undef776 %vrshr_n160 = tail call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %add.i188, <8 x i16> <i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8>)777 %vrshr_n163 = tail call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %add.i186, <8 x i16> <i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8>)778 %mul.i184 = mul <8 x i16> undef, %vrshr_n160779 %mul.i181 = mul <8 x i16> undef, %vmovl.i225780 %add.i182 = add <8 x i16> %mul.i181, %mul.i184781 %vrshr_n170 = tail call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %add.i182, <8 x i16> <i16 -7, i16 -7, i16 -7, i16 -7, i16 -7, i16 -7, i16 -7, i16 -7>)782 %vqmovn1.i180 = tail call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %vrshr_n170) nounwind783 %4 = bitcast <8 x i8> %vqmovn1.i180 to <1 x i64>784 %shuffle.i = shufflevector <1 x i64> %4, <1 x i64> undef, <2 x i32> <i32 0, i32 1>785 %5 = bitcast <2 x i64> %shuffle.i to <16 x i8>786 store <16 x i8> %5, ptr undef, align 16787 %add177 = add nsw i32 undef, 16788 br i1 undef, label %for.body33, label %for.cond.loopexit789 790for.end179: ; preds = %for.cond.loopexit, %entry791 ret void792}793 794declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone795declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>) nounwind readnone796declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone797 798; vmull lowering would create a zext(v4i8 load()) instead of a zextload(v4i8),799; creating an illegal type during legalization and causing an assert.800; PR15970801define void @no_illegal_types_vmull_sext(<4 x i32> %a) {802; CHECK-LABEL: no_illegal_types_vmull_sext:803; CHECK: @ %bb.0: @ %entry804entry:805 %wide.load283.i = load <4 x i8>, ptr undef, align 1806 %0 = sext <4 x i8> %wide.load283.i to <4 x i32>807 %1 = sub nsw <4 x i32> %0, %a808 %2 = mul nsw <4 x i32> %1, %1809 %predphi290.v.i = select <4 x i1> undef, <4 x i32> undef, <4 x i32> %2810 store <4 x i32> %predphi290.v.i, ptr undef, align 4811 ret void812}813define void @no_illegal_types_vmull_zext(<4 x i32> %a) {814; CHECK-LABEL: no_illegal_types_vmull_zext:815; CHECK: @ %bb.0: @ %entry816entry:817 %wide.load283.i = load <4 x i8>, ptr undef, align 1818 %0 = zext <4 x i8> %wide.load283.i to <4 x i32>819 %1 = sub nsw <4 x i32> %0, %a820 %2 = mul nsw <4 x i32> %1, %1821 %predphi290.v.i = select <4 x i1> undef, <4 x i32> undef, <4 x i32> %2822 store <4 x i32> %predphi290.v.i, ptr undef, align 4823 ret void824}825 826define void @fmul_splat(ptr %A, ptr nocapture %dst, float %tmp) nounwind {827; Look for a scalar float rather than a splat, then a vector*scalar multiply.828; CHECK-LABEL: fmul_splat:829; CHECK: @ %bb.0:830; CHECK-NEXT: vld1.32 {d16, d17}, [r0]831; CHECK-NEXT: @ kill: def $s0 killed $s0 def $d0832; CHECK-NEXT: vmul.f32 q8, q8, d0[0]833; CHECK-NEXT: vst1.32 {d16, d17}, [r1]834; CHECK-NEXT: bx lr835 %tmp5 = load <4 x float>, ptr %A, align 4836 %tmp6 = insertelement <4 x float> undef, float %tmp, i32 0837 %tmp7 = insertelement <4 x float> %tmp6, float %tmp, i32 1838 %tmp8 = insertelement <4 x float> %tmp7, float %tmp, i32 2839 %tmp9 = insertelement <4 x float> %tmp8, float %tmp, i32 3840 %tmp10 = fmul <4 x float> %tmp9, %tmp5841 store <4 x float> %tmp10, ptr %dst, align 4842 ret void843}844 845define void @fmul_splat_load(ptr %A, ptr nocapture %dst, ptr nocapture readonly %src) nounwind {846; Look for doing a normal scalar FP load rather than an to-all-lanes load,847; then a vector*scalar multiply.848; FIXME: Temporarily broken due to splat representation changes.849; CHECK-LABEL: fmul_splat_load:850; CHECK: @ %bb.0:851; CHECK-NEXT: vld1.32 {d16, d17}, [r0]852; CHECK-NEXT: vld1.32 {d18[], d19[]}, [r2:32]853; CHECK-NEXT: vmul.f32 q8, q9, q8854; CHECK-NEXT: vst1.32 {d16, d17}, [r1]855; CHECK-NEXT: bx lr856 %tmp = load float, ptr %src, align 4857 %tmp5 = load <4 x float>, ptr %A, align 4858 %tmp6 = insertelement <4 x float> undef, float %tmp, i32 0859 %tmp7 = insertelement <4 x float> %tmp6, float %tmp, i32 1860 %tmp8 = insertelement <4 x float> %tmp7, float %tmp, i32 2861 %tmp9 = insertelement <4 x float> %tmp8, float %tmp, i32 3862 %tmp10 = fmul <4 x float> %tmp9, %tmp5863 store <4 x float> %tmp10, ptr %dst, align 4864 ret void865}866