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1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3define <8 x i8> @vnegs8(ptr %A) nounwind {4;CHECK-LABEL: vnegs8:5;CHECK: vneg.s86 %tmp1 = load <8 x i8>, ptr %A7 %tmp2 = sub <8 x i8> zeroinitializer, %tmp18 ret <8 x i8> %tmp29}10 11define <4 x i16> @vnegs16(ptr %A) nounwind {12;CHECK-LABEL: vnegs16:13;CHECK: vneg.s1614 %tmp1 = load <4 x i16>, ptr %A15 %tmp2 = sub <4 x i16> zeroinitializer, %tmp116 ret <4 x i16> %tmp217}18 19define <2 x i32> @vnegs32(ptr %A) nounwind {20;CHECK-LABEL: vnegs32:21;CHECK: vneg.s3222 %tmp1 = load <2 x i32>, ptr %A23 %tmp2 = sub <2 x i32> zeroinitializer, %tmp124 ret <2 x i32> %tmp225}26 27define <2 x float> @vnegf32(ptr %A) nounwind {28;CHECK-LABEL: vnegf32:29;CHECK: vneg.f3230 %tmp1 = load <2 x float>, ptr %A31 %tmp2 = fsub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp132 ret <2 x float> %tmp233}34 35define <16 x i8> @vnegQs8(ptr %A) nounwind {36;CHECK-LABEL: vnegQs8:37;CHECK: vneg.s838 %tmp1 = load <16 x i8>, ptr %A39 %tmp2 = sub <16 x i8> zeroinitializer, %tmp140 ret <16 x i8> %tmp241}42 43define <8 x i16> @vnegQs16(ptr %A) nounwind {44;CHECK-LABEL: vnegQs16:45;CHECK: vneg.s1646 %tmp1 = load <8 x i16>, ptr %A47 %tmp2 = sub <8 x i16> zeroinitializer, %tmp148 ret <8 x i16> %tmp249}50 51define <4 x i32> @vnegQs32(ptr %A) nounwind {52;CHECK-LABEL: vnegQs32:53;CHECK: vneg.s3254 %tmp1 = load <4 x i32>, ptr %A55 %tmp2 = sub <4 x i32> zeroinitializer, %tmp156 ret <4 x i32> %tmp257}58 59define <4 x float> @vnegQf32(ptr %A) nounwind {60;CHECK-LABEL: vnegQf32:61;CHECK: vneg.f3262 %tmp1 = load <4 x float>, ptr %A63 %tmp2 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp164 ret <4 x float> %tmp265}66 67define <8 x i8> @vqnegs8(ptr %A) nounwind {68;CHECK-LABEL: vqnegs8:69;CHECK: vqneg.s870 %tmp1 = load <8 x i8>, ptr %A71 %tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1)72 ret <8 x i8> %tmp273}74 75define <4 x i16> @vqnegs16(ptr %A) nounwind {76;CHECK-LABEL: vqnegs16:77;CHECK: vqneg.s1678 %tmp1 = load <4 x i16>, ptr %A79 %tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)80 ret <4 x i16> %tmp281}82 83define <2 x i32> @vqnegs32(ptr %A) nounwind {84;CHECK-LABEL: vqnegs32:85;CHECK: vqneg.s3286 %tmp1 = load <2 x i32>, ptr %A87 %tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1)88 ret <2 x i32> %tmp289}90 91define <16 x i8> @vqnegQs8(ptr %A) nounwind {92;CHECK-LABEL: vqnegQs8:93;CHECK: vqneg.s894 %tmp1 = load <16 x i8>, ptr %A95 %tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1)96 ret <16 x i8> %tmp297}98 99define <8 x i16> @vqnegQs16(ptr %A) nounwind {100;CHECK-LABEL: vqnegQs16:101;CHECK: vqneg.s16102 %tmp1 = load <8 x i16>, ptr %A103 %tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)104 ret <8 x i16> %tmp2105}106 107define <4 x i32> @vqnegQs32(ptr %A) nounwind {108;CHECK-LABEL: vqnegQs32:109;CHECK: vqneg.s32110 %tmp1 = load <4 x i32>, ptr %A111 %tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1)112 ret <4 x i32> %tmp2113}114 115declare <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8>) nounwind readnone116declare <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16>) nounwind readnone117declare <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32>) nounwind readnone118 119declare <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8>) nounwind readnone120declare <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16>) nounwind readnone121declare <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32>) nounwind readnone122