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1; RUN: llc -mattr=+neon < %s | FileCheck %s2target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"3target triple = "thumbv7-elf"4 5define <4 x i16> @vqdmulhs16(ptr %A, ptr %B) nounwind {6;CHECK-LABEL: vqdmulhs16:7;CHECK: vqdmulh.s168 %tmp1 = load <4 x i16>, ptr %A9 %tmp2 = load <4 x i16>, ptr %B10 %tmp3 = call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)11 ret <4 x i16> %tmp312}13 14define <2 x i32> @vqdmulhs32(ptr %A, ptr %B) nounwind {15;CHECK-LABEL: vqdmulhs32:16;CHECK: vqdmulh.s3217 %tmp1 = load <2 x i32>, ptr %A18 %tmp2 = load <2 x i32>, ptr %B19 %tmp3 = call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)20 ret <2 x i32> %tmp321}22 23define <8 x i16> @vqdmulhQs16(ptr %A, ptr %B) nounwind {24;CHECK-LABEL: vqdmulhQs16:25;CHECK: vqdmulh.s1626 %tmp1 = load <8 x i16>, ptr %A27 %tmp2 = load <8 x i16>, ptr %B28 %tmp3 = call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)29 ret <8 x i16> %tmp330}31 32define <4 x i32> @vqdmulhQs32(ptr %A, ptr %B) nounwind {33;CHECK-LABEL: vqdmulhQs32:34;CHECK: vqdmulh.s3235 %tmp1 = load <4 x i32>, ptr %A36 %tmp2 = load <4 x i32>, ptr %B37 %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)38 ret <4 x i32> %tmp339}40 41define arm_aapcs_vfpcc <8 x i16> @test_vqdmulhQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {42entry:43; CHECK: test_vqdmulhQ_lanes1644; CHECK: vqdmulh.s16 q0, q0, d2[1]45 %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> ; <<8 x i16>> [#uses=1]46 %1 = tail call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %arg0_int16x8_t, <8 x i16> %0) ; <<8 x i16>> [#uses=1]47 ret <8 x i16> %148}49 50define arm_aapcs_vfpcc <4 x i32> @test_vqdmulhQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {51entry:52; CHECK: test_vqdmulhQ_lanes3253; CHECK: vqdmulh.s32 q0, q0, d2[1]54 %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses=1]55 %1 = tail call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i32> %0) ; <<4 x i32>> [#uses=1]56 ret <4 x i32> %157}58 59define arm_aapcs_vfpcc <4 x i16> @test_vqdmulh_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {60entry:61; CHECK: test_vqdmulh_lanes1662; CHECK: vqdmulh.s16 d0, d0, d1[1]63 %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]64 %1 = tail call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i16>> [#uses=1]65 ret <4 x i16> %166}67 68define arm_aapcs_vfpcc <2 x i32> @test_vqdmulh_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {69entry:70; CHECK: test_vqdmulh_lanes3271; CHECK: vqdmulh.s32 d0, d0, d1[1]72 %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]73 %1 = tail call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i32>> [#uses=1]74 ret <2 x i32> %175}76 77declare <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone78declare <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone79 80declare <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone81declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone82 83define <4 x i16> @vqrdmulhs16(ptr %A, ptr %B) nounwind {84;CHECK-LABEL: vqrdmulhs16:85;CHECK: vqrdmulh.s1686 %tmp1 = load <4 x i16>, ptr %A87 %tmp2 = load <4 x i16>, ptr %B88 %tmp3 = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)89 ret <4 x i16> %tmp390}91 92define <2 x i32> @vqrdmulhs32(ptr %A, ptr %B) nounwind {93;CHECK-LABEL: vqrdmulhs32:94;CHECK: vqrdmulh.s3295 %tmp1 = load <2 x i32>, ptr %A96 %tmp2 = load <2 x i32>, ptr %B97 %tmp3 = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)98 ret <2 x i32> %tmp399}100 101define <8 x i16> @vqrdmulhQs16(ptr %A, ptr %B) nounwind {102;CHECK-LABEL: vqrdmulhQs16:103;CHECK: vqrdmulh.s16104 %tmp1 = load <8 x i16>, ptr %A105 %tmp2 = load <8 x i16>, ptr %B106 %tmp3 = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)107 ret <8 x i16> %tmp3108}109 110define <4 x i32> @vqrdmulhQs32(ptr %A, ptr %B) nounwind {111;CHECK-LABEL: vqrdmulhQs32:112;CHECK: vqrdmulh.s32113 %tmp1 = load <4 x i32>, ptr %A114 %tmp2 = load <4 x i32>, ptr %B115 %tmp3 = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)116 ret <4 x i32> %tmp3117}118 119define arm_aapcs_vfpcc <8 x i16> @test_vqRdmulhQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {120entry:121; CHECK: test_vqRdmulhQ_lanes16122; CHECK: vqrdmulh.s16 q0, q0, d2[1]123 %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> ; <<8 x i16>> [#uses=1]124 %1 = tail call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %arg0_int16x8_t, <8 x i16> %0) ; <<8 x i16>> [#uses=1]125 ret <8 x i16> %1126}127 128define arm_aapcs_vfpcc <4 x i32> @test_vqRdmulhQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {129entry:130; CHECK: test_vqRdmulhQ_lanes32131; CHECK: vqrdmulh.s32 q0, q0, d2[1]132 %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses=1]133 %1 = tail call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i32> %0) ; <<4 x i32>> [#uses=1]134 ret <4 x i32> %1135}136 137define arm_aapcs_vfpcc <4 x i16> @test_vqRdmulh_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {138entry:139; CHECK: test_vqRdmulh_lanes16140; CHECK: vqrdmulh.s16 d0, d0, d1[1]141 %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]142 %1 = tail call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i16>> [#uses=1]143 ret <4 x i16> %1144}145 146define arm_aapcs_vfpcc <2 x i32> @test_vqRdmulh_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {147entry:148; CHECK: test_vqRdmulh_lanes32149; CHECK: vqrdmulh.s32 d0, d0, d1[1]150 %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]151 %1 = tail call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i32>> [#uses=1]152 ret <2 x i32> %1153}154 155declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone156declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone157 158declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone159declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone160 161define <4 x i32> @vqdmulls16(ptr %A, ptr %B) nounwind {162;CHECK-LABEL: vqdmulls16:163;CHECK: vqdmull.s16164 %tmp1 = load <4 x i16>, ptr %A165 %tmp2 = load <4 x i16>, ptr %B166 %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)167 ret <4 x i32> %tmp3168}169 170define <2 x i64> @vqdmulls32(ptr %A, ptr %B) nounwind {171;CHECK-LABEL: vqdmulls32:172;CHECK: vqdmull.s32173 %tmp1 = load <2 x i32>, ptr %A174 %tmp2 = load <2 x i32>, ptr %B175 %tmp3 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)176 ret <2 x i64> %tmp3177}178 179define arm_aapcs_vfpcc <4 x i32> @test_vqdmull_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {180entry:181; CHECK: test_vqdmull_lanes16182; CHECK: vqdmull.s16 q0, d0, d1[1]183 %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]184 %1 = tail call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]185 ret <4 x i32> %1186}187 188define arm_aapcs_vfpcc <2 x i64> @test_vqdmull_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {189entry:190; CHECK: test_vqdmull_lanes32191; CHECK: vqdmull.s32 q0, d0, d1[1]192 %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]193 %1 = tail call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]194 ret <2 x i64> %1195}196 197declare <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone198declare <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone199 200define <4 x i32> @vqdmlals16_natural(ptr %A, ptr %B, ptr %C) nounwind {201;CHECK-LABEL: vqdmlals16_natural:202;CHECK: vqdmlal.s16203 %tmp1 = load <4 x i32>, ptr %A204 %tmp2 = load <4 x i16>, ptr %B205 %tmp3 = load <4 x i16>, ptr %C206 %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp2, <4 x i16> %tmp3)207 %tmp5 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp4)208 ret <4 x i32> %tmp5209}210 211define <2 x i64> @vqdmlals32_natural(ptr %A, ptr %B, ptr %C) nounwind {212;CHECK-LABEL: vqdmlals32_natural:213;CHECK: vqdmlal.s32214 %tmp1 = load <2 x i64>, ptr %A215 %tmp2 = load <2 x i32>, ptr %B216 %tmp3 = load <2 x i32>, ptr %C217 %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp2, <2 x i32> %tmp3)218 %tmp5 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp4)219 ret <2 x i64> %tmp5220}221 222define arm_aapcs_vfpcc <4 x i32> @test_vqdmlal_lanes16_natural(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone {223entry:224; CHECK-LABEL: test_vqdmlal_lanes16_natural:225; CHECK: vqdmlal.s16 q0, d2, d3[1]226 %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]227 %1 = tail call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %arg1_int16x4_t, <4 x i16> %0)228 %2 = tail call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i32> %1)229 ret <4 x i32> %2230}231 232define arm_aapcs_vfpcc <2 x i64> @test_vqdmlal_lanes32_natural(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone {233entry:234; CHECK-LABEL: test_vqdmlal_lanes32_natural:235; CHECK: vqdmlal.s32 q0, d2, d3[1]236 %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]237 %1 = tail call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %arg1_int32x2_t, <2 x i32> %0)238 %2 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i64> %1)239 ret <2 x i64> %2240}241 242declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>) nounwind readnone243declare <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64>, <2 x i64>) nounwind readnone244 245define <4 x i32> @vqdmlsls16_natural(ptr %A, ptr %B, ptr %C) nounwind {246;CHECK-LABEL: vqdmlsls16_natural:247;CHECK: vqdmlsl.s16248 %tmp1 = load <4 x i32>, ptr %A249 %tmp2 = load <4 x i16>, ptr %B250 %tmp3 = load <4 x i16>, ptr %C251 %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp2, <4 x i16> %tmp3)252 %tmp5 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp4)253 ret <4 x i32> %tmp5254}255 256define <2 x i64> @vqdmlsls32_natural(ptr %A, ptr %B, ptr %C) nounwind {257;CHECK-LABEL: vqdmlsls32_natural:258;CHECK: vqdmlsl.s32259 %tmp1 = load <2 x i64>, ptr %A260 %tmp2 = load <2 x i32>, ptr %B261 %tmp3 = load <2 x i32>, ptr %C262 %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp2, <2 x i32> %tmp3)263 %tmp5 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp4)264 ret <2 x i64> %tmp5265}266 267define arm_aapcs_vfpcc <4 x i32> @test_vqdmlsl_lanes16_natural(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone {268entry:269; CHECK-LABEL: test_vqdmlsl_lanes16_natural:270; CHECK: vqdmlsl.s16 q0, d2, d3[1]271 %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]272 %1 = tail call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %arg1_int16x4_t, <4 x i16> %0)273 %2 = tail call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i32> %1)274 ret <4 x i32> %2275}276 277define arm_aapcs_vfpcc <2 x i64> @test_vqdmlsl_lanes32_natural(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone {278entry:279; CHECK-LABEL: test_vqdmlsl_lanes32_natural:280; CHECK: vqdmlsl.s32 q0, d2, d3[1]281 %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]282 %1 = tail call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %arg1_int32x2_t, <2 x i32> %0)283 %2 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i64> %1)284 ret <2 x i64> %2285}286 287declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>) nounwind readnone288declare <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64>, <2 x i64>) nounwind readnone289