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1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3define <8 x i8> @vqshls8(ptr %A, ptr %B) nounwind {4;CHECK-LABEL: vqshls8:5;CHECK: vqshl.s86 %tmp1 = load <8 x i8>, ptr %A7 %tmp2 = load <8 x i8>, ptr %B8 %tmp3 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)9 ret <8 x i8> %tmp310}11 12define <4 x i16> @vqshls16(ptr %A, ptr %B) nounwind {13;CHECK-LABEL: vqshls16:14;CHECK: vqshl.s1615 %tmp1 = load <4 x i16>, ptr %A16 %tmp2 = load <4 x i16>, ptr %B17 %tmp3 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)18 ret <4 x i16> %tmp319}20 21define <2 x i32> @vqshls32(ptr %A, ptr %B) nounwind {22;CHECK-LABEL: vqshls32:23;CHECK: vqshl.s3224 %tmp1 = load <2 x i32>, ptr %A25 %tmp2 = load <2 x i32>, ptr %B26 %tmp3 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)27 ret <2 x i32> %tmp328}29 30define <1 x i64> @vqshls64(ptr %A, ptr %B) nounwind {31;CHECK-LABEL: vqshls64:32;CHECK: vqshl.s6433 %tmp1 = load <1 x i64>, ptr %A34 %tmp2 = load <1 x i64>, ptr %B35 %tmp3 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)36 ret <1 x i64> %tmp337}38 39define <8 x i8> @vqshlu8(ptr %A, ptr %B) nounwind {40;CHECK-LABEL: vqshlu8:41;CHECK: vqshl.u842 %tmp1 = load <8 x i8>, ptr %A43 %tmp2 = load <8 x i8>, ptr %B44 %tmp3 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)45 ret <8 x i8> %tmp346}47 48define <4 x i16> @vqshlu16(ptr %A, ptr %B) nounwind {49;CHECK-LABEL: vqshlu16:50;CHECK: vqshl.u1651 %tmp1 = load <4 x i16>, ptr %A52 %tmp2 = load <4 x i16>, ptr %B53 %tmp3 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)54 ret <4 x i16> %tmp355}56 57define <2 x i32> @vqshlu32(ptr %A, ptr %B) nounwind {58;CHECK-LABEL: vqshlu32:59;CHECK: vqshl.u3260 %tmp1 = load <2 x i32>, ptr %A61 %tmp2 = load <2 x i32>, ptr %B62 %tmp3 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)63 ret <2 x i32> %tmp364}65 66define <1 x i64> @vqshlu64(ptr %A, ptr %B) nounwind {67;CHECK-LABEL: vqshlu64:68;CHECK: vqshl.u6469 %tmp1 = load <1 x i64>, ptr %A70 %tmp2 = load <1 x i64>, ptr %B71 %tmp3 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)72 ret <1 x i64> %tmp373}74 75define <16 x i8> @vqshlQs8(ptr %A, ptr %B) nounwind {76;CHECK-LABEL: vqshlQs8:77;CHECK: vqshl.s878 %tmp1 = load <16 x i8>, ptr %A79 %tmp2 = load <16 x i8>, ptr %B80 %tmp3 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)81 ret <16 x i8> %tmp382}83 84define <8 x i16> @vqshlQs16(ptr %A, ptr %B) nounwind {85;CHECK-LABEL: vqshlQs16:86;CHECK: vqshl.s1687 %tmp1 = load <8 x i16>, ptr %A88 %tmp2 = load <8 x i16>, ptr %B89 %tmp3 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)90 ret <8 x i16> %tmp391}92 93define <4 x i32> @vqshlQs32(ptr %A, ptr %B) nounwind {94;CHECK-LABEL: vqshlQs32:95;CHECK: vqshl.s3296 %tmp1 = load <4 x i32>, ptr %A97 %tmp2 = load <4 x i32>, ptr %B98 %tmp3 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)99 ret <4 x i32> %tmp3100}101 102define <2 x i64> @vqshlQs64(ptr %A, ptr %B) nounwind {103;CHECK-LABEL: vqshlQs64:104;CHECK: vqshl.s64105 %tmp1 = load <2 x i64>, ptr %A106 %tmp2 = load <2 x i64>, ptr %B107 %tmp3 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)108 ret <2 x i64> %tmp3109}110 111define <16 x i8> @vqshlQu8(ptr %A, ptr %B) nounwind {112;CHECK-LABEL: vqshlQu8:113;CHECK: vqshl.u8114 %tmp1 = load <16 x i8>, ptr %A115 %tmp2 = load <16 x i8>, ptr %B116 %tmp3 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)117 ret <16 x i8> %tmp3118}119 120define <8 x i16> @vqshlQu16(ptr %A, ptr %B) nounwind {121;CHECK-LABEL: vqshlQu16:122;CHECK: vqshl.u16123 %tmp1 = load <8 x i16>, ptr %A124 %tmp2 = load <8 x i16>, ptr %B125 %tmp3 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)126 ret <8 x i16> %tmp3127}128 129define <4 x i32> @vqshlQu32(ptr %A, ptr %B) nounwind {130;CHECK-LABEL: vqshlQu32:131;CHECK: vqshl.u32132 %tmp1 = load <4 x i32>, ptr %A133 %tmp2 = load <4 x i32>, ptr %B134 %tmp3 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)135 ret <4 x i32> %tmp3136}137 138define <2 x i64> @vqshlQu64(ptr %A, ptr %B) nounwind {139;CHECK-LABEL: vqshlQu64:140;CHECK: vqshl.u64141 %tmp1 = load <2 x i64>, ptr %A142 %tmp2 = load <2 x i64>, ptr %B143 %tmp3 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)144 ret <2 x i64> %tmp3145}146 147define <8 x i8> @vqshls_n8(ptr %A) nounwind {148;CHECK-LABEL: vqshls_n8:149;CHECK: vqshl.s8{{.*#7}}150 %tmp1 = load <8 x i8>, ptr %A151 %tmp2 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)152 ret <8 x i8> %tmp2153}154 155define <4 x i16> @vqshls_n16(ptr %A) nounwind {156;CHECK-LABEL: vqshls_n16:157;CHECK: vqshl.s16{{.*#15}}158 %tmp1 = load <4 x i16>, ptr %A159 %tmp2 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)160 ret <4 x i16> %tmp2161}162 163define <2 x i32> @vqshls_n32(ptr %A) nounwind {164;CHECK-LABEL: vqshls_n32:165;CHECK: vqshl.s32{{.*#31}}166 %tmp1 = load <2 x i32>, ptr %A167 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)168 ret <2 x i32> %tmp2169}170 171define <1 x i64> @vqshls_n64(ptr %A) nounwind {172;CHECK-LABEL: vqshls_n64:173;CHECK: vqshl.s64{{.*#63}}174 %tmp1 = load <1 x i64>, ptr %A175 %tmp2 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)176 ret <1 x i64> %tmp2177}178 179define <8 x i8> @vqshlu_n8(ptr %A) nounwind {180;CHECK-LABEL: vqshlu_n8:181;CHECK: vqshl.u8{{.*#7}}182 %tmp1 = load <8 x i8>, ptr %A183 %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)184 ret <8 x i8> %tmp2185}186 187define <4 x i16> @vqshlu_n16(ptr %A) nounwind {188;CHECK-LABEL: vqshlu_n16:189;CHECK: vqshl.u16{{.*#15}}190 %tmp1 = load <4 x i16>, ptr %A191 %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)192 ret <4 x i16> %tmp2193}194 195define <2 x i32> @vqshlu_n32(ptr %A) nounwind {196;CHECK-LABEL: vqshlu_n32:197;CHECK: vqshl.u32{{.*#31}}198 %tmp1 = load <2 x i32>, ptr %A199 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)200 ret <2 x i32> %tmp2201}202 203define <1 x i64> @vqshlu_n64(ptr %A) nounwind {204;CHECK-LABEL: vqshlu_n64:205;CHECK: vqshl.u64{{.*#63}}206 %tmp1 = load <1 x i64>, ptr %A207 %tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)208 ret <1 x i64> %tmp2209}210 211define <8 x i8> @vqshlsu_n8(ptr %A) nounwind {212;CHECK-LABEL: vqshlsu_n8:213;CHECK: vqshlu.s8214 %tmp1 = load <8 x i8>, ptr %A215 %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)216 ret <8 x i8> %tmp2217}218 219define <4 x i16> @vqshlsu_n16(ptr %A) nounwind {220;CHECK-LABEL: vqshlsu_n16:221;CHECK: vqshlu.s16222 %tmp1 = load <4 x i16>, ptr %A223 %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)224 ret <4 x i16> %tmp2225}226 227define <2 x i32> @vqshlsu_n32(ptr %A) nounwind {228;CHECK-LABEL: vqshlsu_n32:229;CHECK: vqshlu.s32230 %tmp1 = load <2 x i32>, ptr %A231 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)232 ret <2 x i32> %tmp2233}234 235define <1 x i64> @vqshlsu_n64(ptr %A) nounwind {236;CHECK-LABEL: vqshlsu_n64:237;CHECK: vqshlu.s64238 %tmp1 = load <1 x i64>, ptr %A239 %tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)240 ret <1 x i64> %tmp2241}242 243define <16 x i8> @vqshlQs_n8(ptr %A) nounwind {244;CHECK-LABEL: vqshlQs_n8:245;CHECK: vqshl.s8{{.*#7}}246 %tmp1 = load <16 x i8>, ptr %A247 %tmp2 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)248 ret <16 x i8> %tmp2249}250 251define <8 x i16> @vqshlQs_n16(ptr %A) nounwind {252;CHECK-LABEL: vqshlQs_n16:253;CHECK: vqshl.s16{{.*#15}}254 %tmp1 = load <8 x i16>, ptr %A255 %tmp2 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)256 ret <8 x i16> %tmp2257}258 259define <4 x i32> @vqshlQs_n32(ptr %A) nounwind {260;CHECK-LABEL: vqshlQs_n32:261;CHECK: vqshl.s32{{.*#31}}262 %tmp1 = load <4 x i32>, ptr %A263 %tmp2 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)264 ret <4 x i32> %tmp2265}266 267define <2 x i64> @vqshlQs_n64(ptr %A) nounwind {268;CHECK-LABEL: vqshlQs_n64:269;CHECK: vqshl.s64{{.*#63}}270 %tmp1 = load <2 x i64>, ptr %A271 %tmp2 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)272 ret <2 x i64> %tmp2273}274 275define <16 x i8> @vqshlQu_n8(ptr %A) nounwind {276;CHECK-LABEL: vqshlQu_n8:277;CHECK: vqshl.u8{{.*#7}}278 %tmp1 = load <16 x i8>, ptr %A279 %tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)280 ret <16 x i8> %tmp2281}282 283define <8 x i16> @vqshlQu_n16(ptr %A) nounwind {284;CHECK-LABEL: vqshlQu_n16:285;CHECK: vqshl.u16{{.*#15}}286 %tmp1 = load <8 x i16>, ptr %A287 %tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)288 ret <8 x i16> %tmp2289}290 291define <4 x i32> @vqshlQu_n32(ptr %A) nounwind {292;CHECK-LABEL: vqshlQu_n32:293;CHECK: vqshl.u32{{.*#31}}294 %tmp1 = load <4 x i32>, ptr %A295 %tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)296 ret <4 x i32> %tmp2297}298 299define <2 x i64> @vqshlQu_n64(ptr %A) nounwind {300;CHECK-LABEL: vqshlQu_n64:301;CHECK: vqshl.u64{{.*#63}}302 %tmp1 = load <2 x i64>, ptr %A303 %tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)304 ret <2 x i64> %tmp2305}306 307define <16 x i8> @vqshlQsu_n8(ptr %A) nounwind {308;CHECK-LABEL: vqshlQsu_n8:309;CHECK: vqshlu.s8310 %tmp1 = load <16 x i8>, ptr %A311 %tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)312 ret <16 x i8> %tmp2313}314 315define <8 x i16> @vqshlQsu_n16(ptr %A) nounwind {316;CHECK-LABEL: vqshlQsu_n16:317;CHECK: vqshlu.s16318 %tmp1 = load <8 x i16>, ptr %A319 %tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)320 ret <8 x i16> %tmp2321}322 323define <4 x i32> @vqshlQsu_n32(ptr %A) nounwind {324;CHECK-LABEL: vqshlQsu_n32:325;CHECK: vqshlu.s32326 %tmp1 = load <4 x i32>, ptr %A327 %tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)328 ret <4 x i32> %tmp2329}330 331define <2 x i64> @vqshlQsu_n64(ptr %A) nounwind {332;CHECK-LABEL: vqshlQsu_n64:333;CHECK: vqshlu.s64334 %tmp1 = load <2 x i64>, ptr %A335 %tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)336 ret <2 x i64> %tmp2337}338 339declare <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone340declare <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone341declare <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone342declare <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone343 344declare <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone345declare <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone346declare <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone347declare <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone348 349declare <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone350declare <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone351declare <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone352declare <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone353 354declare <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone355declare <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone356declare <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone357declare <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone358 359declare <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone360declare <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone361declare <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone362declare <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone363 364declare <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone365declare <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone366declare <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone367declare <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone368 369define <8 x i8> @vqrshls8(ptr %A, ptr %B) nounwind {370;CHECK-LABEL: vqrshls8:371;CHECK: vqrshl.s8372 %tmp1 = load <8 x i8>, ptr %A373 %tmp2 = load <8 x i8>, ptr %B374 %tmp3 = call <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)375 ret <8 x i8> %tmp3376}377 378define <4 x i16> @vqrshls16(ptr %A, ptr %B) nounwind {379;CHECK-LABEL: vqrshls16:380;CHECK: vqrshl.s16381 %tmp1 = load <4 x i16>, ptr %A382 %tmp2 = load <4 x i16>, ptr %B383 %tmp3 = call <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)384 ret <4 x i16> %tmp3385}386 387define <2 x i32> @vqrshls32(ptr %A, ptr %B) nounwind {388;CHECK-LABEL: vqrshls32:389;CHECK: vqrshl.s32390 %tmp1 = load <2 x i32>, ptr %A391 %tmp2 = load <2 x i32>, ptr %B392 %tmp3 = call <2 x i32> @llvm.arm.neon.vqrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)393 ret <2 x i32> %tmp3394}395 396define <1 x i64> @vqrshls64(ptr %A, ptr %B) nounwind {397;CHECK-LABEL: vqrshls64:398;CHECK: vqrshl.s64399 %tmp1 = load <1 x i64>, ptr %A400 %tmp2 = load <1 x i64>, ptr %B401 %tmp3 = call <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)402 ret <1 x i64> %tmp3403}404 405define <8 x i8> @vqrshlu8(ptr %A, ptr %B) nounwind {406;CHECK-LABEL: vqrshlu8:407;CHECK: vqrshl.u8408 %tmp1 = load <8 x i8>, ptr %A409 %tmp2 = load <8 x i8>, ptr %B410 %tmp3 = call <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)411 ret <8 x i8> %tmp3412}413 414define <4 x i16> @vqrshlu16(ptr %A, ptr %B) nounwind {415;CHECK-LABEL: vqrshlu16:416;CHECK: vqrshl.u16417 %tmp1 = load <4 x i16>, ptr %A418 %tmp2 = load <4 x i16>, ptr %B419 %tmp3 = call <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)420 ret <4 x i16> %tmp3421}422 423define <2 x i32> @vqrshlu32(ptr %A, ptr %B) nounwind {424;CHECK-LABEL: vqrshlu32:425;CHECK: vqrshl.u32426 %tmp1 = load <2 x i32>, ptr %A427 %tmp2 = load <2 x i32>, ptr %B428 %tmp3 = call <2 x i32> @llvm.arm.neon.vqrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)429 ret <2 x i32> %tmp3430}431 432define <1 x i64> @vqrshlu64(ptr %A, ptr %B) nounwind {433;CHECK-LABEL: vqrshlu64:434;CHECK: vqrshl.u64435 %tmp1 = load <1 x i64>, ptr %A436 %tmp2 = load <1 x i64>, ptr %B437 %tmp3 = call <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)438 ret <1 x i64> %tmp3439}440 441define <16 x i8> @vqrshlQs8(ptr %A, ptr %B) nounwind {442;CHECK-LABEL: vqrshlQs8:443;CHECK: vqrshl.s8444 %tmp1 = load <16 x i8>, ptr %A445 %tmp2 = load <16 x i8>, ptr %B446 %tmp3 = call <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)447 ret <16 x i8> %tmp3448}449 450define <8 x i16> @vqrshlQs16(ptr %A, ptr %B) nounwind {451;CHECK-LABEL: vqrshlQs16:452;CHECK: vqrshl.s16453 %tmp1 = load <8 x i16>, ptr %A454 %tmp2 = load <8 x i16>, ptr %B455 %tmp3 = call <8 x i16> @llvm.arm.neon.vqrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)456 ret <8 x i16> %tmp3457}458 459define <4 x i32> @vqrshlQs32(ptr %A, ptr %B) nounwind {460;CHECK-LABEL: vqrshlQs32:461;CHECK: vqrshl.s32462 %tmp1 = load <4 x i32>, ptr %A463 %tmp2 = load <4 x i32>, ptr %B464 %tmp3 = call <4 x i32> @llvm.arm.neon.vqrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)465 ret <4 x i32> %tmp3466}467 468define <2 x i64> @vqrshlQs64(ptr %A, ptr %B) nounwind {469;CHECK-LABEL: vqrshlQs64:470;CHECK: vqrshl.s64471 %tmp1 = load <2 x i64>, ptr %A472 %tmp2 = load <2 x i64>, ptr %B473 %tmp3 = call <2 x i64> @llvm.arm.neon.vqrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)474 ret <2 x i64> %tmp3475}476 477define <16 x i8> @vqrshlQu8(ptr %A, ptr %B) nounwind {478;CHECK-LABEL: vqrshlQu8:479;CHECK: vqrshl.u8480 %tmp1 = load <16 x i8>, ptr %A481 %tmp2 = load <16 x i8>, ptr %B482 %tmp3 = call <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)483 ret <16 x i8> %tmp3484}485 486define <8 x i16> @vqrshlQu16(ptr %A, ptr %B) nounwind {487;CHECK-LABEL: vqrshlQu16:488;CHECK: vqrshl.u16489 %tmp1 = load <8 x i16>, ptr %A490 %tmp2 = load <8 x i16>, ptr %B491 %tmp3 = call <8 x i16> @llvm.arm.neon.vqrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)492 ret <8 x i16> %tmp3493}494 495define <4 x i32> @vqrshlQu32(ptr %A, ptr %B) nounwind {496;CHECK-LABEL: vqrshlQu32:497;CHECK: vqrshl.u32498 %tmp1 = load <4 x i32>, ptr %A499 %tmp2 = load <4 x i32>, ptr %B500 %tmp3 = call <4 x i32> @llvm.arm.neon.vqrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)501 ret <4 x i32> %tmp3502}503 504define <2 x i64> @vqrshlQu64(ptr %A, ptr %B) nounwind {505;CHECK-LABEL: vqrshlQu64:506;CHECK: vqrshl.u64507 %tmp1 = load <2 x i64>, ptr %A508 %tmp2 = load <2 x i64>, ptr %B509 %tmp3 = call <2 x i64> @llvm.arm.neon.vqrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)510 ret <2 x i64> %tmp3511}512 513declare <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone514declare <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone515declare <2 x i32> @llvm.arm.neon.vqrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone516declare <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone517 518declare <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone519declare <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone520declare <2 x i32> @llvm.arm.neon.vqrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone521declare <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone522 523declare <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone524declare <8 x i16> @llvm.arm.neon.vqrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone525declare <4 x i32> @llvm.arm.neon.vqrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone526declare <2 x i64> @llvm.arm.neon.vqrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone527 528declare <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone529declare <8 x i16> @llvm.arm.neon.vqrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone530declare <4 x i32> @llvm.arm.neon.vqrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone531declare <2 x i64> @llvm.arm.neon.vqrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone532