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1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3define <8 x i8> @vqshrns8(ptr %A) nounwind {4;CHECK-LABEL: vqshrns8:5;CHECK: vqshrn.s166 %tmp1 = load <8 x i16>, ptr %A7 %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)8 ret <8 x i8> %tmp29}10 11define <4 x i16> @vqshrns16(ptr %A) nounwind {12;CHECK-LABEL: vqshrns16:13;CHECK: vqshrn.s3214 %tmp1 = load <4 x i32>, ptr %A15 %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)16 ret <4 x i16> %tmp217}18 19define <2 x i32> @vqshrns32(ptr %A) nounwind {20;CHECK-LABEL: vqshrns32:21;CHECK: vqshrn.s6422 %tmp1 = load <2 x i64>, ptr %A23 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)24 ret <2 x i32> %tmp225}26 27define <8 x i8> @vqshrnu8(ptr %A) nounwind {28;CHECK-LABEL: vqshrnu8:29;CHECK: vqshrn.u1630 %tmp1 = load <8 x i16>, ptr %A31 %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)32 ret <8 x i8> %tmp233}34 35define <4 x i16> @vqshrnu16(ptr %A) nounwind {36;CHECK-LABEL: vqshrnu16:37;CHECK: vqshrn.u3238 %tmp1 = load <4 x i32>, ptr %A39 %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)40 ret <4 x i16> %tmp241}42 43define <2 x i32> @vqshrnu32(ptr %A) nounwind {44;CHECK-LABEL: vqshrnu32:45;CHECK: vqshrn.u6446 %tmp1 = load <2 x i64>, ptr %A47 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)48 ret <2 x i32> %tmp249}50 51define <8 x i8> @vqshruns8(ptr %A) nounwind {52;CHECK-LABEL: vqshruns8:53;CHECK: vqshrun.s1654 %tmp1 = load <8 x i16>, ptr %A55 %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)56 ret <8 x i8> %tmp257}58 59define <4 x i16> @vqshruns16(ptr %A) nounwind {60;CHECK-LABEL: vqshruns16:61;CHECK: vqshrun.s3262 %tmp1 = load <4 x i32>, ptr %A63 %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)64 ret <4 x i16> %tmp265}66 67define <2 x i32> @vqshruns32(ptr %A) nounwind {68;CHECK-LABEL: vqshruns32:69;CHECK: vqshrun.s6470 %tmp1 = load <2 x i64>, ptr %A71 %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)72 ret <2 x i32> %tmp273}74 75declare <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone76declare <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone77declare <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone78 79declare <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone80declare <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone81declare <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone82 83declare <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone84declare <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone85declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone86 87define <8 x i8> @vqrshrns8(ptr %A) nounwind {88;CHECK-LABEL: vqrshrns8:89;CHECK: vqrshrn.s1690 %tmp1 = load <8 x i16>, ptr %A91 %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)92 ret <8 x i8> %tmp293}94 95define <4 x i16> @vqrshrns16(ptr %A) nounwind {96;CHECK-LABEL: vqrshrns16:97;CHECK: vqrshrn.s3298 %tmp1 = load <4 x i32>, ptr %A99 %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)100 ret <4 x i16> %tmp2101}102 103define <2 x i32> @vqrshrns32(ptr %A) nounwind {104;CHECK-LABEL: vqrshrns32:105;CHECK: vqrshrn.s64106 %tmp1 = load <2 x i64>, ptr %A107 %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)108 ret <2 x i32> %tmp2109}110 111define <8 x i8> @vqrshrnu8(ptr %A) nounwind {112;CHECK-LABEL: vqrshrnu8:113;CHECK: vqrshrn.u16114 %tmp1 = load <8 x i16>, ptr %A115 %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)116 ret <8 x i8> %tmp2117}118 119define <4 x i16> @vqrshrnu16(ptr %A) nounwind {120;CHECK-LABEL: vqrshrnu16:121;CHECK: vqrshrn.u32122 %tmp1 = load <4 x i32>, ptr %A123 %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)124 ret <4 x i16> %tmp2125}126 127define <2 x i32> @vqrshrnu32(ptr %A) nounwind {128;CHECK-LABEL: vqrshrnu32:129;CHECK: vqrshrn.u64130 %tmp1 = load <2 x i64>, ptr %A131 %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)132 ret <2 x i32> %tmp2133}134 135define <8 x i8> @vqrshruns8(ptr %A) nounwind {136;CHECK-LABEL: vqrshruns8:137;CHECK: vqrshrun.s16138 %tmp1 = load <8 x i16>, ptr %A139 %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)140 ret <8 x i8> %tmp2141}142 143define <4 x i16> @vqrshruns16(ptr %A) nounwind {144;CHECK-LABEL: vqrshruns16:145;CHECK: vqrshrun.s32146 %tmp1 = load <4 x i32>, ptr %A147 %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)148 ret <4 x i16> %tmp2149}150 151define <2 x i32> @vqrshruns32(ptr %A) nounwind {152;CHECK-LABEL: vqrshruns32:153;CHECK: vqrshrun.s64154 %tmp1 = load <2 x i64>, ptr %A155 %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)156 ret <2 x i32> %tmp2157}158 159declare <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone160declare <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone161declare <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone162 163declare <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone164declare <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone165declare <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone166 167declare <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone168declare <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone169declare <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone170