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1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3define <8 x i8> @vqsubs8(ptr %A, ptr %B) nounwind {4;CHECK-LABEL: vqsubs8:5;CHECK: vqsub.s86 %tmp1 = load <8 x i8>, ptr %A7 %tmp2 = load <8 x i8>, ptr %B8 %tmp3 = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)9 ret <8 x i8> %tmp310}11 12define <4 x i16> @vqsubs16(ptr %A, ptr %B) nounwind {13;CHECK-LABEL: vqsubs16:14;CHECK: vqsub.s1615 %tmp1 = load <4 x i16>, ptr %A16 %tmp2 = load <4 x i16>, ptr %B17 %tmp3 = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)18 ret <4 x i16> %tmp319}20 21define <2 x i32> @vqsubs32(ptr %A, ptr %B) nounwind {22;CHECK-LABEL: vqsubs32:23;CHECK: vqsub.s3224 %tmp1 = load <2 x i32>, ptr %A25 %tmp2 = load <2 x i32>, ptr %B26 %tmp3 = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)27 ret <2 x i32> %tmp328}29 30define <1 x i64> @vqsubs64(ptr %A, ptr %B) nounwind {31;CHECK-LABEL: vqsubs64:32;CHECK: vqsub.s6433 %tmp1 = load <1 x i64>, ptr %A34 %tmp2 = load <1 x i64>, ptr %B35 %tmp3 = call <1 x i64> @llvm.ssub.sat.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)36 ret <1 x i64> %tmp337}38 39define <8 x i8> @vqsubu8(ptr %A, ptr %B) nounwind {40;CHECK-LABEL: vqsubu8:41;CHECK: vqsub.u842 %tmp1 = load <8 x i8>, ptr %A43 %tmp2 = load <8 x i8>, ptr %B44 %tmp3 = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)45 ret <8 x i8> %tmp346}47 48define <4 x i16> @vqsubu16(ptr %A, ptr %B) nounwind {49;CHECK-LABEL: vqsubu16:50;CHECK: vqsub.u1651 %tmp1 = load <4 x i16>, ptr %A52 %tmp2 = load <4 x i16>, ptr %B53 %tmp3 = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)54 ret <4 x i16> %tmp355}56 57define <2 x i32> @vqsubu32(ptr %A, ptr %B) nounwind {58;CHECK-LABEL: vqsubu32:59;CHECK: vqsub.u3260 %tmp1 = load <2 x i32>, ptr %A61 %tmp2 = load <2 x i32>, ptr %B62 %tmp3 = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)63 ret <2 x i32> %tmp364}65 66define <1 x i64> @vqsubu64(ptr %A, ptr %B) nounwind {67;CHECK-LABEL: vqsubu64:68;CHECK: vqsub.u6469 %tmp1 = load <1 x i64>, ptr %A70 %tmp2 = load <1 x i64>, ptr %B71 %tmp3 = call <1 x i64> @llvm.usub.sat.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)72 ret <1 x i64> %tmp373}74 75define <16 x i8> @vqsubQs8(ptr %A, ptr %B) nounwind {76;CHECK-LABEL: vqsubQs8:77;CHECK: vqsub.s878 %tmp1 = load <16 x i8>, ptr %A79 %tmp2 = load <16 x i8>, ptr %B80 %tmp3 = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)81 ret <16 x i8> %tmp382}83 84define <8 x i16> @vqsubQs16(ptr %A, ptr %B) nounwind {85;CHECK-LABEL: vqsubQs16:86;CHECK: vqsub.s1687 %tmp1 = load <8 x i16>, ptr %A88 %tmp2 = load <8 x i16>, ptr %B89 %tmp3 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)90 ret <8 x i16> %tmp391}92 93define <4 x i32> @vqsubQs32(ptr %A, ptr %B) nounwind {94;CHECK-LABEL: vqsubQs32:95;CHECK: vqsub.s3296 %tmp1 = load <4 x i32>, ptr %A97 %tmp2 = load <4 x i32>, ptr %B98 %tmp3 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)99 ret <4 x i32> %tmp3100}101 102define <2 x i64> @vqsubQs64(ptr %A, ptr %B) nounwind {103;CHECK-LABEL: vqsubQs64:104;CHECK: vqsub.s64105 %tmp1 = load <2 x i64>, ptr %A106 %tmp2 = load <2 x i64>, ptr %B107 %tmp3 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)108 ret <2 x i64> %tmp3109}110 111define <16 x i8> @vqsubQu8(ptr %A, ptr %B) nounwind {112;CHECK-LABEL: vqsubQu8:113;CHECK: vqsub.u8114 %tmp1 = load <16 x i8>, ptr %A115 %tmp2 = load <16 x i8>, ptr %B116 %tmp3 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)117 ret <16 x i8> %tmp3118}119 120define <8 x i16> @vqsubQu16(ptr %A, ptr %B) nounwind {121;CHECK-LABEL: vqsubQu16:122;CHECK: vqsub.u16123 %tmp1 = load <8 x i16>, ptr %A124 %tmp2 = load <8 x i16>, ptr %B125 %tmp3 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)126 ret <8 x i16> %tmp3127}128 129define <4 x i32> @vqsubQu32(ptr %A, ptr %B) nounwind {130;CHECK-LABEL: vqsubQu32:131;CHECK: vqsub.u32132 %tmp1 = load <4 x i32>, ptr %A133 %tmp2 = load <4 x i32>, ptr %B134 %tmp3 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)135 ret <4 x i32> %tmp3136}137 138define <2 x i64> @vqsubQu64(ptr %A, ptr %B) nounwind {139;CHECK-LABEL: vqsubQu64:140;CHECK: vqsub.u64141 %tmp1 = load <2 x i64>, ptr %A142 %tmp2 = load <2 x i64>, ptr %B143 %tmp3 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)144 ret <2 x i64> %tmp3145}146 147declare <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8>, <8 x i8>) nounwind readnone148declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>) nounwind readnone149declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>) nounwind readnone150declare <1 x i64> @llvm.ssub.sat.v1i64(<1 x i64>, <1 x i64>) nounwind readnone151 152declare <8 x i8> @llvm.usub.sat.v8i8(<8 x i8>, <8 x i8>) nounwind readnone153declare <4 x i16> @llvm.usub.sat.v4i16(<4 x i16>, <4 x i16>) nounwind readnone154declare <2 x i32> @llvm.usub.sat.v2i32(<2 x i32>, <2 x i32>) nounwind readnone155declare <1 x i64> @llvm.usub.sat.v1i64(<1 x i64>, <1 x i64>) nounwind readnone156 157declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>) nounwind readnone158declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) nounwind readnone159declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>) nounwind readnone160declare <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64>, <2 x i64>) nounwind readnone161 162declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>) nounwind readnone163declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>) nounwind readnone164declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) nounwind readnone165declare <2 x i64> @llvm.usub.sat.v2i64(<2 x i64>, <2 x i64>) nounwind readnone166