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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm-eabi -mattr=+neon,+fullfp16 %s -o - | FileCheck %s3 4define <8 x i8> @test_vrev64D8(ptr %A) nounwind {5; CHECK-LABEL: test_vrev64D8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vldr d16, [r0]8; CHECK-NEXT: vrev64.8 d16, d169; CHECK-NEXT: vmov r0, r1, d1610; CHECK-NEXT: mov pc, lr11 %tmp1 = load <8 x i8>, ptr %A12 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>13 ret <8 x i8> %tmp214}15 16define <4 x i16> @test_vrev64D16(ptr %A) nounwind {17; CHECK-LABEL: test_vrev64D16:18; CHECK: @ %bb.0:19; CHECK-NEXT: vldr d16, [r0]20; CHECK-NEXT: vrev64.16 d16, d1621; CHECK-NEXT: vmov r0, r1, d1622; CHECK-NEXT: mov pc, lr23 %tmp1 = load <4 x i16>, ptr %A24 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>25 ret <4 x i16> %tmp226}27 28define <4 x half> @test_vrev64Df16(ptr %A) nounwind {29; CHECK-LABEL: test_vrev64Df16:30; CHECK: @ %bb.0:31; CHECK-NEXT: vldr d16, [r0]32; CHECK-NEXT: vrev64.16 d16, d1633; CHECK-NEXT: vmov r0, r1, d1634; CHECK-NEXT: mov pc, lr35 %tmp1 = load <4 x half>, ptr %A36 %tmp2 = shufflevector <4 x half> %tmp1, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>37 ret <4 x half> %tmp238}39 40define <2 x i32> @test_vrev64D32(ptr %A) nounwind {41; CHECK-LABEL: test_vrev64D32:42; CHECK: @ %bb.0:43; CHECK-NEXT: vldr d16, [r0]44; CHECK-NEXT: vrev64.32 d16, d1645; CHECK-NEXT: vmov r0, r1, d1646; CHECK-NEXT: mov pc, lr47 %tmp1 = load <2 x i32>, ptr %A48 %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>49 ret <2 x i32> %tmp250}51 52define <2 x float> @test_vrev64Df(ptr %A) nounwind {53; CHECK-LABEL: test_vrev64Df:54; CHECK: @ %bb.0:55; CHECK-NEXT: vldr d16, [r0]56; CHECK-NEXT: vrev64.32 d16, d1657; CHECK-NEXT: vmov r0, r1, d1658; CHECK-NEXT: mov pc, lr59 %tmp1 = load <2 x float>, ptr %A60 %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>61 ret <2 x float> %tmp262}63 64define <16 x i8> @test_vrev64Q8(ptr %A) nounwind {65; CHECK-LABEL: test_vrev64Q8:66; CHECK: @ %bb.0:67; CHECK-NEXT: vld1.64 {d16, d17}, [r0]68; CHECK-NEXT: vrev64.8 q8, q869; CHECK-NEXT: vmov r0, r1, d1670; CHECK-NEXT: vmov r2, r3, d1771; CHECK-NEXT: mov pc, lr72 %tmp1 = load <16 x i8>, ptr %A73 %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>74 ret <16 x i8> %tmp275}76 77define <8 x i16> @test_vrev64Q16(ptr %A) nounwind {78; CHECK-LABEL: test_vrev64Q16:79; CHECK: @ %bb.0:80; CHECK-NEXT: vld1.64 {d16, d17}, [r0]81; CHECK-NEXT: vrev64.16 q8, q882; CHECK-NEXT: vmov r0, r1, d1683; CHECK-NEXT: vmov r2, r3, d1784; CHECK-NEXT: mov pc, lr85 %tmp1 = load <8 x i16>, ptr %A86 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>87 ret <8 x i16> %tmp288}89 90define <8 x half> @test_vrev64Qf16(ptr %A) nounwind {91; CHECK-LABEL: test_vrev64Qf16:92; CHECK: @ %bb.0:93; CHECK-NEXT: vld1.64 {d16, d17}, [r0]94; CHECK-NEXT: vrev64.16 q8, q895; CHECK-NEXT: vmov r0, r1, d1696; CHECK-NEXT: vmov r2, r3, d1797; CHECK-NEXT: mov pc, lr98 %tmp1 = load <8 x half>, ptr %A99 %tmp2 = shufflevector <8 x half> %tmp1, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>100 ret <8 x half> %tmp2101}102 103define <4 x i32> @test_vrev64Q32(ptr %A) nounwind {104; CHECK-LABEL: test_vrev64Q32:105; CHECK: @ %bb.0:106; CHECK-NEXT: vld1.64 {d16, d17}, [r0]107; CHECK-NEXT: vrev64.32 q8, q8108; CHECK-NEXT: vmov r0, r1, d16109; CHECK-NEXT: vmov r2, r3, d17110; CHECK-NEXT: mov pc, lr111 %tmp1 = load <4 x i32>, ptr %A112 %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>113 ret <4 x i32> %tmp2114}115 116define <4 x float> @test_vrev64Qf(ptr %A) nounwind {117; CHECK-LABEL: test_vrev64Qf:118; CHECK: @ %bb.0:119; CHECK-NEXT: vld1.64 {d16, d17}, [r0]120; CHECK-NEXT: vrev64.32 q8, q8121; CHECK-NEXT: vmov r0, r1, d16122; CHECK-NEXT: vmov r2, r3, d17123; CHECK-NEXT: mov pc, lr124 %tmp1 = load <4 x float>, ptr %A125 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>126 ret <4 x float> %tmp2127}128 129define <8 x i8> @test_vrev32D8(ptr %A) nounwind {130; CHECK-LABEL: test_vrev32D8:131; CHECK: @ %bb.0:132; CHECK-NEXT: vldr d16, [r0]133; CHECK-NEXT: vrev32.8 d16, d16134; CHECK-NEXT: vmov r0, r1, d16135; CHECK-NEXT: mov pc, lr136 %tmp1 = load <8 x i8>, ptr %A137 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>138 ret <8 x i8> %tmp2139}140 141define <4 x i16> @test_vrev32D16(ptr %A) nounwind {142; CHECK-LABEL: test_vrev32D16:143; CHECK: @ %bb.0:144; CHECK-NEXT: vldr d16, [r0]145; CHECK-NEXT: vrev32.16 d16, d16146; CHECK-NEXT: vmov r0, r1, d16147; CHECK-NEXT: mov pc, lr148 %tmp1 = load <4 x i16>, ptr %A149 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>150 ret <4 x i16> %tmp2151}152 153define <4 x half> @test_vrev32Df16(ptr %A) nounwind {154; CHECK-LABEL: test_vrev32Df16:155; CHECK: @ %bb.0:156; CHECK-NEXT: vldr d16, [r0]157; CHECK-NEXT: vrev32.16 d16, d16158; CHECK-NEXT: vmov r0, r1, d16159; CHECK-NEXT: mov pc, lr160 %tmp1 = load <4 x half>, ptr %A161 %tmp2 = shufflevector <4 x half> %tmp1, <4 x half> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>162 ret <4 x half> %tmp2163}164 165define <16 x i8> @test_vrev32Q8(ptr %A) nounwind {166; CHECK-LABEL: test_vrev32Q8:167; CHECK: @ %bb.0:168; CHECK-NEXT: vld1.64 {d16, d17}, [r0]169; CHECK-NEXT: vrev32.8 q8, q8170; CHECK-NEXT: vmov r0, r1, d16171; CHECK-NEXT: vmov r2, r3, d17172; CHECK-NEXT: mov pc, lr173 %tmp1 = load <16 x i8>, ptr %A174 %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>175 ret <16 x i8> %tmp2176}177 178define <8 x i16> @test_vrev32Q16(ptr %A) nounwind {179; CHECK-LABEL: test_vrev32Q16:180; CHECK: @ %bb.0:181; CHECK-NEXT: vld1.64 {d16, d17}, [r0]182; CHECK-NEXT: vrev32.16 q8, q8183; CHECK-NEXT: vmov r0, r1, d16184; CHECK-NEXT: vmov r2, r3, d17185; CHECK-NEXT: mov pc, lr186 %tmp1 = load <8 x i16>, ptr %A187 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>188 ret <8 x i16> %tmp2189}190 191define <8 x half> @test_vrev32Qf16(ptr %A) nounwind {192; CHECK-LABEL: test_vrev32Qf16:193; CHECK: @ %bb.0:194; CHECK-NEXT: vld1.64 {d16, d17}, [r0]195; CHECK-NEXT: vrev32.16 q8, q8196; CHECK-NEXT: vmov r0, r1, d16197; CHECK-NEXT: vmov r2, r3, d17198; CHECK-NEXT: mov pc, lr199 %tmp1 = load <8 x half>, ptr %A200 %tmp2 = shufflevector <8 x half> %tmp1, <8 x half> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>201 ret <8 x half> %tmp2202}203 204define <8 x i8> @test_vrev16D8(ptr %A) nounwind {205; CHECK-LABEL: test_vrev16D8:206; CHECK: @ %bb.0:207; CHECK-NEXT: vldr d16, [r0]208; CHECK-NEXT: vrev16.8 d16, d16209; CHECK-NEXT: vmov r0, r1, d16210; CHECK-NEXT: mov pc, lr211 %tmp1 = load <8 x i8>, ptr %A212 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>213 ret <8 x i8> %tmp2214}215 216define <16 x i8> @test_vrev16Q8(ptr %A) nounwind {217; CHECK-LABEL: test_vrev16Q8:218; CHECK: @ %bb.0:219; CHECK-NEXT: vld1.64 {d16, d17}, [r0]220; CHECK-NEXT: vrev16.8 q8, q8221; CHECK-NEXT: vmov r0, r1, d16222; CHECK-NEXT: vmov r2, r3, d17223; CHECK-NEXT: mov pc, lr224 %tmp1 = load <16 x i8>, ptr %A225 %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>226 ret <16 x i8> %tmp2227}228 229; Undef shuffle indices should not prevent matching to VREV:230 231define <8 x i8> @test_vrev64D8_undef(ptr %A) nounwind {232; CHECK-LABEL: test_vrev64D8_undef:233; CHECK: @ %bb.0:234; CHECK-NEXT: vldr d16, [r0]235; CHECK-NEXT: vrev64.8 d16, d16236; CHECK-NEXT: vmov r0, r1, d16237; CHECK-NEXT: mov pc, lr238 %tmp1 = load <8 x i8>, ptr %A239 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>240 ret <8 x i8> %tmp2241}242 243define <8 x i16> @test_vrev32Q16_undef(ptr %A) nounwind {244; CHECK-LABEL: test_vrev32Q16_undef:245; CHECK: @ %bb.0:246; CHECK-NEXT: vld1.64 {d16, d17}, [r0]247; CHECK-NEXT: vrev32.16 q8, q8248; CHECK-NEXT: vmov r0, r1, d16249; CHECK-NEXT: vmov r2, r3, d17250; CHECK-NEXT: mov pc, lr251 %tmp1 = load <8 x i16>, ptr %A252 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>253 ret <8 x i16> %tmp2254}255 256define <8 x half> @test_vrev32Qf16_undef(ptr %A) nounwind {257; CHECK-LABEL: test_vrev32Qf16_undef:258; CHECK: @ %bb.0:259; CHECK-NEXT: vld1.64 {d16, d17}, [r0]260; CHECK-NEXT: vrev32.16 q8, q8261; CHECK-NEXT: vmov r0, r1, d16262; CHECK-NEXT: vmov r2, r3, d17263; CHECK-NEXT: mov pc, lr264 %tmp1 = load <8 x half>, ptr %A265 %tmp2 = shufflevector <8 x half> %tmp1, <8 x half> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>266 ret <8 x half> %tmp2267}268 269; A vcombine feeding a VREV should not obscure things. Radar 8597007.270 271define void @test_with_vcombine(ptr %v) nounwind {272; CHECK-LABEL: test_with_vcombine:273; CHECK: @ %bb.0:274; CHECK-NEXT: vld1.64 {d16, d17}, [r0:128]275; CHECK-NEXT: vadd.f32 d18, d17, d17276; CHECK-NEXT: vrev64.32 d16, d16277; CHECK-NEXT: vrev64.32 d17, d18278; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]279; CHECK-NEXT: mov pc, lr280 %tmp1 = load <4 x float>, ptr %v, align 16281 %tmp2 = bitcast <4 x float> %tmp1 to <2 x double>282 %tmp3 = extractelement <2 x double> %tmp2, i32 0283 %tmp4 = bitcast double %tmp3 to <2 x float>284 %tmp5 = extractelement <2 x double> %tmp2, i32 1285 %tmp6 = bitcast double %tmp5 to <2 x float>286 %tmp7 = fadd <2 x float> %tmp6, %tmp6287 %tmp8 = shufflevector <2 x float> %tmp4, <2 x float> %tmp7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>288 store <4 x float> %tmp8, ptr %v, align 16289 ret void290}291 292; The type <2 x i16> is legalized to <2 x i32> and need to be trunc-stored293; to <2 x i16> when stored to memory.294define void @test_vrev64(ptr nocapture %source, ptr nocapture %dst) nounwind ssp {295; CHECK-LABEL: test_vrev64:296; CHECK: @ %bb.0: @ %entry297; CHECK-NEXT: vld1.32 {d16, d17}, [r0]298; CHECK-NEXT: vmov.u16 r0, d17[2]299; CHECK-NEXT: vmov.u16 r2, d17[1]300; CHECK-NEXT: vmov.32 d16[0], r0301; CHECK-NEXT: vmov.32 d16[1], r2302; CHECK-NEXT: vuzp.16 d16, d17303; CHECK-NEXT: vst1.32 {d16[0]}, [r1:32]304; CHECK-NEXT: mov pc, lr305entry:306 %tmp2 = load <8 x i16>, ptr %source, align 4307 %tmp3 = extractelement <8 x i16> %tmp2, i32 6308 %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0309 %tmp9 = extractelement <8 x i16> %tmp2, i32 5310 %tmp11 = insertelement <2 x i16> %tmp5, i16 %tmp9, i32 1311 store <2 x i16> %tmp11, ptr %dst, align 4312 ret void313}314 315; Test vrev of float4316define void @float_vrev64(ptr nocapture %source, ptr nocapture %dest) nounwind noinline ssp {317; CHECK-LABEL: float_vrev64:318; CHECK: @ %bb.0: @ %entry319; CHECK-NEXT: vmov.i32 q8, #0x0320; CHECK-NEXT: vld1.32 {d18, d19}, [r0]321; CHECK-NEXT: add r0, r1, #176322; CHECK-NEXT: vext.32 q8, q9, q8, #3323; CHECK-NEXT: vrev64.32 q8, q8324; CHECK-NEXT: vst1.32 {d16, d17}, [r0]325; CHECK-NEXT: mov pc, lr326entry:327 %tmp2 = load <4 x float>, ptr %source, align 4328 %tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0>329 %arrayidx8 = getelementptr inbounds <4 x float>, ptr %dest, i32 11330 store <4 x float> %tmp5, ptr %arrayidx8, align 4331 ret void332}333 334define <4 x i32> @test_vrev32_bswap(<4 x i32> %source) nounwind {335; CHECK-LABEL: test_vrev32_bswap:336; CHECK: @ %bb.0:337; CHECK-NEXT: vmov d17, r2, r3338; CHECK-NEXT: vmov d16, r0, r1339; CHECK-NEXT: vrev32.8 q8, q8340; CHECK-NEXT: vmov r0, r1, d16341; CHECK-NEXT: vmov r2, r3, d17342; CHECK-NEXT: mov pc, lr343 %bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %source)344 ret <4 x i32> %bswap345}346 347declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone348