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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=armv8 -mattr=+neon %s -o - | FileCheck %s3 4declare float @llvm.arm.neon.vrintn.f32(float) nounwind readnone5declare <2 x float> @llvm.arm.neon.vrintn.v2f32(<2 x float>) nounwind readnone6declare <4 x float> @llvm.arm.neon.vrintn.v4f32(<4 x float>) nounwind readnone7 8define float @vrintn_f32(ptr %A) nounwind {9; CHECK-LABEL: vrintn_f32:10; CHECK: @ %bb.0:11; CHECK-NEXT: vldr s0, [r0]12; CHECK-NEXT: vrintn.f32 s0, s013; CHECK-NEXT: vmov r0, s014; CHECK-NEXT: bx lr15 %tmp1 = load float, ptr %A16 %tmp2 = call float @llvm.arm.neon.vrintn.f32(float %tmp1)17 ret float %tmp218}19 20define <2 x float> @frintn_2s(<2 x float> %A) nounwind {21; CHECK-LABEL: frintn_2s:22; CHECK: @ %bb.0:23; CHECK-NEXT: vmov d16, r0, r124; CHECK-NEXT: vrintn.f32 d16, d1625; CHECK-NEXT: vmov r0, r1, d1626; CHECK-NEXT: bx lr27 %tmp3 = call <2 x float> @llvm.arm.neon.vrintn.v2f32(<2 x float> %A)28 ret <2 x float> %tmp329}30 31define <4 x float> @frintn_4s(<4 x float> %A) nounwind {32; CHECK-LABEL: frintn_4s:33; CHECK: @ %bb.0:34; CHECK-NEXT: vmov d17, r2, r335; CHECK-NEXT: vmov d16, r0, r136; CHECK-NEXT: vrintn.f32 q8, q837; CHECK-NEXT: vmov r0, r1, d1638; CHECK-NEXT: vmov r2, r3, d1739; CHECK-NEXT: bx lr40 %tmp3 = call <4 x float> @llvm.arm.neon.vrintn.v4f32(<4 x float> %A)41 ret <4 x float> %tmp342}43 44define <4 x half> @roundeven_4h(<4 x half> %A) nounwind {45; CHECK-LABEL: roundeven_4h:46; CHECK: @ %bb.0:47; CHECK-NEXT: vmov s0, r348; CHECK-NEXT: vcvtb.f32.f16 s0, s049; CHECK-NEXT: vmov s2, r250; CHECK-NEXT: vrintn.f32 s0, s051; CHECK-NEXT: vcvtb.f32.f16 s2, s252; CHECK-NEXT: vrintn.f32 s2, s253; CHECK-NEXT: vcvtb.f16.f32 s0, s054; CHECK-NEXT: vcvtb.f16.f32 s2, s255; CHECK-NEXT: vmov r2, s056; CHECK-NEXT: vmov s0, r157; CHECK-NEXT: vmov r3, s258; CHECK-NEXT: vcvtb.f32.f16 s0, s059; CHECK-NEXT: vmov s2, r060; CHECK-NEXT: vrintn.f32 s0, s061; CHECK-NEXT: vcvtb.f32.f16 s2, s262; CHECK-NEXT: vcvtb.f16.f32 s0, s063; CHECK-NEXT: vrintn.f32 s2, s264; CHECK-NEXT: vmov r0, s065; CHECK-NEXT: vcvtb.f16.f32 s2, s266; CHECK-NEXT: vmov r1, s267; CHECK-NEXT: pkhbt r2, r3, r2, lsl #1668; CHECK-NEXT: pkhbt r0, r1, r0, lsl #1669; CHECK-NEXT: vmov d16, r0, r270; CHECK-NEXT: vmov.u16 r0, d16[0]71; CHECK-NEXT: vmov.u16 r1, d16[1]72; CHECK-NEXT: vmov.u16 r2, d16[2]73; CHECK-NEXT: vmov.u16 r3, d16[3]74; CHECK-NEXT: bx lr75 %tmp3 = call <4 x half> @llvm.roundeven.v4f16(<4 x half> %A)76 ret <4 x half> %tmp377}78 79define <2 x float> @roundeven_2s(<2 x float> %A) nounwind {80; CHECK-LABEL: roundeven_2s:81; CHECK: @ %bb.0:82; CHECK-NEXT: vmov d16, r0, r183; CHECK-NEXT: vrintn.f32 d16, d1684; CHECK-NEXT: vmov r0, r1, d1685; CHECK-NEXT: bx lr86 %tmp3 = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %A)87 ret <2 x float> %tmp388}89 90define <4 x float> @roundeven_4s(<4 x float> %A) nounwind {91; CHECK-LABEL: roundeven_4s:92; CHECK: @ %bb.0:93; CHECK-NEXT: vmov d17, r2, r394; CHECK-NEXT: vmov d16, r0, r195; CHECK-NEXT: vrintn.f32 q8, q896; CHECK-NEXT: vmov r0, r1, d1697; CHECK-NEXT: vmov r2, r3, d1798; CHECK-NEXT: bx lr99 %tmp3 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %A)100 ret <4 x float> %tmp3101}102 103define <2 x double> @roundeven_2d(<2 x double> %A) nounwind {104; CHECK-LABEL: roundeven_2d:105; CHECK: @ %bb.0:106; CHECK-NEXT: vmov d16, r2, r3107; CHECK-NEXT: vmov d17, r0, r1108; CHECK-NEXT: vrintn.f64 d16, d16109; CHECK-NEXT: vrintn.f64 d17, d17110; CHECK-NEXT: vmov r2, r3, d16111; CHECK-NEXT: vmov r0, r1, d17112; CHECK-NEXT: bx lr113 %tmp3 = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %A)114 ret <2 x double> %tmp3115}116 117declare <4 x half> @llvm.roundeven.v4f16(<4 x half>) nounwind readnone118declare <2 x float> @llvm.roundeven.v2f32(<2 x float>) nounwind readnone119declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) nounwind readnone120declare <2 x double> @llvm.roundeven.v2f64(<2 x double>) nounwind readnone121