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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=armv8a--none-eabi -mattr=+fullfp16 -float-abi=hard | FileCheck %s3 4@varhalf = global half 0.05@vardouble = global double 0.06define void @test_vsel32sgt(i32 %lhs, i32 %rhs, ptr %a_ptr, ptr %b_ptr) {7; CHECK-LABEL: test_vsel32sgt:8; CHECK: @ %bb.0:9; CHECK-NEXT: vldr.16 s0, [r2]10; CHECK-NEXT: vldr.16 s2, [r3]11; CHECK-NEXT: cmp r0, r112; CHECK-NEXT: movw r0, :lower16:varhalf13; CHECK-NEXT: vselgt.f16 s0, s0, s214; CHECK-NEXT: movt r0, :upper16:varhalf15; CHECK-NEXT: vstr.16 s0, [r0]16; CHECK-NEXT: bx lr17 %a = load volatile half, ptr %a_ptr18 %b = load volatile half, ptr %b_ptr19 %tst1 = icmp sgt i32 %lhs, %rhs20 %val1 = select i1 %tst1, half %a, half %b21 store half %val1, ptr @varhalf22 ret void23}24 25define void @test_vsel32sge(i32 %lhs, i32 %rhs, ptr %a_ptr, ptr %b_ptr) {26; CHECK-LABEL: test_vsel32sge:27; CHECK: @ %bb.0:28; CHECK-NEXT: vldr.16 s0, [r2]29; CHECK-NEXT: vldr.16 s2, [r3]30; CHECK-NEXT: cmp r0, r131; CHECK-NEXT: movw r0, :lower16:varhalf32; CHECK-NEXT: vselge.f16 s0, s0, s233; CHECK-NEXT: movt r0, :upper16:varhalf34; CHECK-NEXT: vstr.16 s0, [r0]35; CHECK-NEXT: bx lr36 %a = load volatile half, ptr %a_ptr37 %b = load volatile half, ptr %b_ptr38 %tst1 = icmp sge i32 %lhs, %rhs39 %val1 = select i1 %tst1, half %a, half %b40 store half %val1, ptr @varhalf41 ret void42}43 44define void @test_vsel32eq(i32 %lhs, i32 %rhs, ptr %a_ptr, ptr %b_ptr) {45; CHECK-LABEL: test_vsel32eq:46; CHECK: @ %bb.0:47; CHECK-NEXT: vldr.16 s0, [r2]48; CHECK-NEXT: vldr.16 s2, [r3]49; CHECK-NEXT: cmp r0, r150; CHECK-NEXT: movw r0, :lower16:varhalf51; CHECK-NEXT: vseleq.f16 s0, s0, s252; CHECK-NEXT: movt r0, :upper16:varhalf53; CHECK-NEXT: vstr.16 s0, [r0]54; CHECK-NEXT: bx lr55 %a = load volatile half, ptr %a_ptr56 %b = load volatile half, ptr %b_ptr57 %tst1 = icmp eq i32 %lhs, %rhs58 %val1 = select i1 %tst1, half %a, half %b59 store half %val1, ptr @varhalf60 ret void61}62 63define void @test_vsel32slt(i32 %lhs, i32 %rhs, ptr %a_ptr, ptr %b_ptr) {64; CHECK-LABEL: test_vsel32slt:65; CHECK: @ %bb.0:66; CHECK-NEXT: vldr.16 s0, [r2]67; CHECK-NEXT: vldr.16 s2, [r3]68; CHECK-NEXT: cmp r0, r169; CHECK-NEXT: movw r0, :lower16:varhalf70; CHECK-NEXT: vselge.f16 s0, s2, s071; CHECK-NEXT: movt r0, :upper16:varhalf72; CHECK-NEXT: vstr.16 s0, [r0]73; CHECK-NEXT: bx lr74 %a = load volatile half, ptr %a_ptr75 %b = load volatile half, ptr %b_ptr76 %tst1 = icmp slt i32 %lhs, %rhs77 %val1 = select i1 %tst1, half %a, half %b78 store half %val1, ptr @varhalf79 ret void80}81 82define void @test_vsel32sle(i32 %lhs, i32 %rhs, ptr %a_ptr, ptr %b_ptr) {83; CHECK-LABEL: test_vsel32sle:84; CHECK: @ %bb.0:85; CHECK-NEXT: vldr.16 s0, [r2]86; CHECK-NEXT: vldr.16 s2, [r3]87; CHECK-NEXT: cmp r0, r188; CHECK-NEXT: movw r0, :lower16:varhalf89; CHECK-NEXT: vselgt.f16 s0, s2, s090; CHECK-NEXT: movt r0, :upper16:varhalf91; CHECK-NEXT: vstr.16 s0, [r0]92; CHECK-NEXT: bx lr93 %a = load volatile half, ptr %a_ptr94 %b = load volatile half, ptr %b_ptr95 %tst1 = icmp sle i32 %lhs, %rhs96 %val1 = select i1 %tst1, half %a, half %b97 store half %val1, ptr @varhalf98 ret void99}100 101define void @test_vsel32ogt(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {102; CHECK-LABEL: test_vsel32ogt:103; CHECK: @ %bb.0:104; CHECK-NEXT: vldr.16 s0, [r2]105; CHECK-NEXT: vldr.16 s2, [r3]106; CHECK-NEXT: vldr.16 s4, [r0]107; CHECK-NEXT: vldr.16 s6, [r1]108; CHECK-NEXT: movw r0, :lower16:varhalf109; CHECK-NEXT: vcmp.f16 s4, s6110; CHECK-NEXT: movt r0, :upper16:varhalf111; CHECK-NEXT: vmrs APSR_nzcv, fpscr112; CHECK-NEXT: vselgt.f16 s0, s0, s2113; CHECK-NEXT: vstr.16 s0, [r0]114; CHECK-NEXT: bx lr115 %a = load volatile half, ptr %a_ptr116 %b = load volatile half, ptr %b_ptr117 %lhs = load volatile half, ptr %lhs_ptr118 %rhs = load volatile half, ptr %rhs_ptr119 %tst1 = fcmp ogt half %lhs, %rhs120 %val1 = select i1 %tst1, half %a, half %b121 store half %val1, ptr @varhalf122 ret void123}124 125define void @test_vsel32oge(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {126; CHECK-LABEL: test_vsel32oge:127; CHECK: @ %bb.0:128; CHECK-NEXT: vldr.16 s0, [r2]129; CHECK-NEXT: vldr.16 s2, [r3]130; CHECK-NEXT: vldr.16 s4, [r0]131; CHECK-NEXT: vldr.16 s6, [r1]132; CHECK-NEXT: movw r0, :lower16:varhalf133; CHECK-NEXT: vcmp.f16 s4, s6134; CHECK-NEXT: movt r0, :upper16:varhalf135; CHECK-NEXT: vmrs APSR_nzcv, fpscr136; CHECK-NEXT: vselge.f16 s0, s0, s2137; CHECK-NEXT: vstr.16 s0, [r0]138; CHECK-NEXT: bx lr139 %a = load volatile half, ptr %a_ptr140 %b = load volatile half, ptr %b_ptr141 %lhs = load volatile half, ptr %lhs_ptr142 %rhs = load volatile half, ptr %rhs_ptr143 %tst1 = fcmp oge half %lhs, %rhs144 %val1 = select i1 %tst1, half %a, half %b145 store half %val1, ptr @varhalf146 ret void147}148 149define void @test_vsel32oeq(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {150; CHECK-LABEL: test_vsel32oeq:151; CHECK: @ %bb.0:152; CHECK-NEXT: vldr.16 s0, [r2]153; CHECK-NEXT: vldr.16 s2, [r3]154; CHECK-NEXT: vldr.16 s4, [r0]155; CHECK-NEXT: vldr.16 s6, [r1]156; CHECK-NEXT: movw r0, :lower16:varhalf157; CHECK-NEXT: vcmp.f16 s4, s6158; CHECK-NEXT: movt r0, :upper16:varhalf159; CHECK-NEXT: vmrs APSR_nzcv, fpscr160; CHECK-NEXT: vseleq.f16 s0, s0, s2161; CHECK-NEXT: vstr.16 s0, [r0]162; CHECK-NEXT: bx lr163 %a = load volatile half, ptr %a_ptr164 %b = load volatile half, ptr %b_ptr165 %lhs = load volatile half, ptr %lhs_ptr166 %rhs = load volatile half, ptr %rhs_ptr167 %tst1 = fcmp oeq half %lhs, %rhs168 %val1 = select i1 %tst1, half %a, half %b169 store half %val1, ptr @varhalf170 ret void171}172 173define void @test_vsel32ugt(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {174; CHECK-LABEL: test_vsel32ugt:175; CHECK: @ %bb.0:176; CHECK-NEXT: vldr.16 s0, [r2]177; CHECK-NEXT: vldr.16 s2, [r3]178; CHECK-NEXT: vldr.16 s4, [r0]179; CHECK-NEXT: vldr.16 s6, [r1]180; CHECK-NEXT: movw r0, :lower16:varhalf181; CHECK-NEXT: vcmp.f16 s6, s4182; CHECK-NEXT: movt r0, :upper16:varhalf183; CHECK-NEXT: vmrs APSR_nzcv, fpscr184; CHECK-NEXT: vselge.f16 s0, s2, s0185; CHECK-NEXT: vstr.16 s0, [r0]186; CHECK-NEXT: bx lr187 %a = load volatile half, ptr %a_ptr188 %b = load volatile half, ptr %b_ptr189 %lhs = load volatile half, ptr %lhs_ptr190 %rhs = load volatile half, ptr %rhs_ptr191 %tst1 = fcmp ugt half %lhs, %rhs192 %val1 = select i1 %tst1, half %a, half %b193 store half %val1, ptr @varhalf194 ret void195}196 197define void @test_vsel32uge(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {198; CHECK-LABEL: test_vsel32uge:199; CHECK: @ %bb.0:200; CHECK-NEXT: vldr.16 s0, [r2]201; CHECK-NEXT: vldr.16 s2, [r3]202; CHECK-NEXT: vldr.16 s4, [r0]203; CHECK-NEXT: vldr.16 s6, [r1]204; CHECK-NEXT: movw r0, :lower16:varhalf205; CHECK-NEXT: vcmp.f16 s6, s4206; CHECK-NEXT: movt r0, :upper16:varhalf207; CHECK-NEXT: vmrs APSR_nzcv, fpscr208; CHECK-NEXT: vselgt.f16 s0, s2, s0209; CHECK-NEXT: vstr.16 s0, [r0]210; CHECK-NEXT: bx lr211 %a = load volatile half, ptr %a_ptr212 %b = load volatile half, ptr %b_ptr213 %lhs = load volatile half, ptr %lhs_ptr214 %rhs = load volatile half, ptr %rhs_ptr215 %tst1 = fcmp uge half %lhs, %rhs216 %val1 = select i1 %tst1, half %a, half %b217 store half %val1, ptr @varhalf218 ret void219}220 221define void @test_vsel32olt(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {222; CHECK-LABEL: test_vsel32olt:223; CHECK: @ %bb.0:224; CHECK-NEXT: vldr.16 s0, [r2]225; CHECK-NEXT: vldr.16 s2, [r3]226; CHECK-NEXT: vldr.16 s4, [r0]227; CHECK-NEXT: vldr.16 s6, [r1]228; CHECK-NEXT: movw r0, :lower16:varhalf229; CHECK-NEXT: vcmp.f16 s6, s4230; CHECK-NEXT: movt r0, :upper16:varhalf231; CHECK-NEXT: vmrs APSR_nzcv, fpscr232; CHECK-NEXT: vselgt.f16 s0, s0, s2233; CHECK-NEXT: vstr.16 s0, [r0]234; CHECK-NEXT: bx lr235 %a = load volatile half, ptr %a_ptr236 %b = load volatile half, ptr %b_ptr237 %lhs = load volatile half, ptr %lhs_ptr238 %rhs = load volatile half, ptr %rhs_ptr239 %tst1 = fcmp olt half %lhs, %rhs240 %val1 = select i1 %tst1, half %a, half %b241 store half %val1, ptr @varhalf242 ret void243}244 245define void @test_vsel32ult(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {246; CHECK-LABEL: test_vsel32ult:247; CHECK: @ %bb.0:248; CHECK-NEXT: vldr.16 s0, [r2]249; CHECK-NEXT: vldr.16 s2, [r3]250; CHECK-NEXT: vldr.16 s4, [r0]251; CHECK-NEXT: vldr.16 s6, [r1]252; CHECK-NEXT: movw r0, :lower16:varhalf253; CHECK-NEXT: vcmp.f16 s4, s6254; CHECK-NEXT: movt r0, :upper16:varhalf255; CHECK-NEXT: vmrs APSR_nzcv, fpscr256; CHECK-NEXT: vselge.f16 s0, s2, s0257; CHECK-NEXT: vstr.16 s0, [r0]258; CHECK-NEXT: bx lr259 %a = load volatile half, ptr %a_ptr260 %b = load volatile half, ptr %b_ptr261 %lhs = load volatile half, ptr %lhs_ptr262 %rhs = load volatile half, ptr %rhs_ptr263 %tst1 = fcmp ult half %lhs, %rhs264 %val1 = select i1 %tst1, half %a, half %b265 store half %val1, ptr @varhalf266 ret void267}268 269define void @test_vsel32ole(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {270; CHECK-LABEL: test_vsel32ole:271; CHECK: @ %bb.0:272; CHECK-NEXT: vldr.16 s0, [r2]273; CHECK-NEXT: vldr.16 s2, [r3]274; CHECK-NEXT: vldr.16 s4, [r0]275; CHECK-NEXT: vldr.16 s6, [r1]276; CHECK-NEXT: movw r0, :lower16:varhalf277; CHECK-NEXT: vcmp.f16 s6, s4278; CHECK-NEXT: movt r0, :upper16:varhalf279; CHECK-NEXT: vmrs APSR_nzcv, fpscr280; CHECK-NEXT: vselge.f16 s0, s0, s2281; CHECK-NEXT: vstr.16 s0, [r0]282; CHECK-NEXT: bx lr283 %a = load volatile half, ptr %a_ptr284 %b = load volatile half, ptr %b_ptr285 %lhs = load volatile half, ptr %lhs_ptr286 %rhs = load volatile half, ptr %rhs_ptr287 %tst1 = fcmp ole half %lhs, %rhs288 %val1 = select i1 %tst1, half %a, half %b289 store half %val1, ptr @varhalf290 ret void291}292 293define void @test_vsel32ule(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {294; CHECK-LABEL: test_vsel32ule:295; CHECK: @ %bb.0:296; CHECK-NEXT: vldr.16 s0, [r2]297; CHECK-NEXT: vldr.16 s2, [r3]298; CHECK-NEXT: vldr.16 s4, [r0]299; CHECK-NEXT: vldr.16 s6, [r1]300; CHECK-NEXT: movw r0, :lower16:varhalf301; CHECK-NEXT: vcmp.f16 s4, s6302; CHECK-NEXT: movt r0, :upper16:varhalf303; CHECK-NEXT: vmrs APSR_nzcv, fpscr304; CHECK-NEXT: vselgt.f16 s0, s2, s0305; CHECK-NEXT: vstr.16 s0, [r0]306; CHECK-NEXT: bx lr307 %a = load volatile half, ptr %a_ptr308 %b = load volatile half, ptr %b_ptr309 %lhs = load volatile half, ptr %lhs_ptr310 %rhs = load volatile half, ptr %rhs_ptr311 %tst1 = fcmp ule half %lhs, %rhs312 %val1 = select i1 %tst1, half %a, half %b313 store half %val1, ptr @varhalf314 ret void315}316 317define void @test_vsel32ord(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {318; CHECK-LABEL: test_vsel32ord:319; CHECK: @ %bb.0:320; CHECK-NEXT: vldr.16 s0, [r2]321; CHECK-NEXT: vldr.16 s2, [r3]322; CHECK-NEXT: vldr.16 s4, [r0]323; CHECK-NEXT: vldr.16 s6, [r1]324; CHECK-NEXT: movw r0, :lower16:varhalf325; CHECK-NEXT: vcmp.f16 s4, s6326; CHECK-NEXT: movt r0, :upper16:varhalf327; CHECK-NEXT: vmrs APSR_nzcv, fpscr328; CHECK-NEXT: vselvs.f16 s0, s2, s0329; CHECK-NEXT: vstr.16 s0, [r0]330; CHECK-NEXT: bx lr331 %a = load volatile half, ptr %a_ptr332 %b = load volatile half, ptr %b_ptr333 %lhs = load volatile half, ptr %lhs_ptr334 %rhs = load volatile half, ptr %rhs_ptr335 %tst1 = fcmp ord half %lhs, %rhs336 %val1 = select i1 %tst1, half %a, half %b337 store half %val1, ptr @varhalf338 ret void339}340 341define void @test_vsel32une(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {342; CHECK-LABEL: test_vsel32une:343; CHECK: @ %bb.0:344; CHECK-NEXT: vldr.16 s0, [r2]345; CHECK-NEXT: vldr.16 s2, [r3]346; CHECK-NEXT: vldr.16 s4, [r0]347; CHECK-NEXT: vldr.16 s6, [r1]348; CHECK-NEXT: movw r0, :lower16:varhalf349; CHECK-NEXT: vcmp.f16 s4, s6350; CHECK-NEXT: movt r0, :upper16:varhalf351; CHECK-NEXT: vmrs APSR_nzcv, fpscr352; CHECK-NEXT: vseleq.f16 s0, s2, s0353; CHECK-NEXT: vstr.16 s0, [r0]354; CHECK-NEXT: bx lr355 %a = load volatile half, ptr %a_ptr356 %b = load volatile half, ptr %b_ptr357 %lhs = load volatile half, ptr %lhs_ptr358 %rhs = load volatile half, ptr %rhs_ptr359 %tst1 = fcmp une half %lhs, %rhs360 %val1 = select i1 %tst1, half %a, half %b361 store half %val1, ptr @varhalf362 ret void363}364 365define void @test_vsel32uno(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {366; CHECK-LABEL: test_vsel32uno:367; CHECK: @ %bb.0:368; CHECK-NEXT: vldr.16 s0, [r2]369; CHECK-NEXT: vldr.16 s2, [r3]370; CHECK-NEXT: vldr.16 s4, [r0]371; CHECK-NEXT: vldr.16 s6, [r1]372; CHECK-NEXT: movw r0, :lower16:varhalf373; CHECK-NEXT: vcmp.f16 s4, s6374; CHECK-NEXT: movt r0, :upper16:varhalf375; CHECK-NEXT: vmrs APSR_nzcv, fpscr376; CHECK-NEXT: vselvs.f16 s0, s0, s2377; CHECK-NEXT: vstr.16 s0, [r0]378; CHECK-NEXT: bx lr379 %a = load volatile half, ptr %a_ptr380 %b = load volatile half, ptr %b_ptr381 %lhs = load volatile half, ptr %lhs_ptr382 %rhs = load volatile half, ptr %rhs_ptr383 %tst1 = fcmp uno half %lhs, %rhs384 %val1 = select i1 %tst1, half %a, half %b385 store half %val1, ptr @varhalf386 ret void387}388 389 390define void @test_vsel32ogt_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {391; CHECK-LABEL: test_vsel32ogt_nnan:392; CHECK: @ %bb.0:393; CHECK-NEXT: vldr.16 s0, [r2]394; CHECK-NEXT: vldr.16 s2, [r3]395; CHECK-NEXT: vldr.16 s4, [r0]396; CHECK-NEXT: vldr.16 s6, [r1]397; CHECK-NEXT: movw r0, :lower16:varhalf398; CHECK-NEXT: vcmp.f16 s4, s6399; CHECK-NEXT: movt r0, :upper16:varhalf400; CHECK-NEXT: vmrs APSR_nzcv, fpscr401; CHECK-NEXT: vselgt.f16 s0, s0, s2402; CHECK-NEXT: vstr.16 s0, [r0]403; CHECK-NEXT: bx lr404 %a = load volatile half, ptr %a_ptr405 %b = load volatile half, ptr %b_ptr406 %lhs = load volatile half, ptr %lhs_ptr407 %rhs = load volatile half, ptr %rhs_ptr408 %tst1 = fcmp nnan ogt half %lhs, %rhs409 %val1 = select i1 %tst1, half %a, half %b410 store half %val1, ptr @varhalf411 ret void412}413 414define void @test_vsel32oge_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {415; CHECK-LABEL: test_vsel32oge_nnan:416; CHECK: @ %bb.0:417; CHECK-NEXT: vldr.16 s0, [r2]418; CHECK-NEXT: vldr.16 s2, [r3]419; CHECK-NEXT: vldr.16 s4, [r0]420; CHECK-NEXT: vldr.16 s6, [r1]421; CHECK-NEXT: movw r0, :lower16:varhalf422; CHECK-NEXT: vcmp.f16 s4, s6423; CHECK-NEXT: movt r0, :upper16:varhalf424; CHECK-NEXT: vmrs APSR_nzcv, fpscr425; CHECK-NEXT: vselge.f16 s0, s0, s2426; CHECK-NEXT: vstr.16 s0, [r0]427; CHECK-NEXT: bx lr428 %a = load volatile half, ptr %a_ptr429 %b = load volatile half, ptr %b_ptr430 %lhs = load volatile half, ptr %lhs_ptr431 %rhs = load volatile half, ptr %rhs_ptr432 %tst1 = fcmp nnan oge half %lhs, %rhs433 %val1 = select i1 %tst1, half %a, half %b434 store half %val1, ptr @varhalf435 ret void436}437 438define void @test_vsel32oeq_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {439; CHECK-LABEL: test_vsel32oeq_nnan:440; CHECK: @ %bb.0:441; CHECK-NEXT: vldr.16 s0, [r2]442; CHECK-NEXT: vldr.16 s2, [r3]443; CHECK-NEXT: vldr.16 s4, [r0]444; CHECK-NEXT: vldr.16 s6, [r1]445; CHECK-NEXT: movw r0, :lower16:varhalf446; CHECK-NEXT: vcmp.f16 s4, s6447; CHECK-NEXT: movt r0, :upper16:varhalf448; CHECK-NEXT: vmrs APSR_nzcv, fpscr449; CHECK-NEXT: vseleq.f16 s0, s0, s2450; CHECK-NEXT: vstr.16 s0, [r0]451; CHECK-NEXT: bx lr452 %a = load volatile half, ptr %a_ptr453 %b = load volatile half, ptr %b_ptr454 %lhs = load volatile half, ptr %lhs_ptr455 %rhs = load volatile half, ptr %rhs_ptr456 %tst1 = fcmp nnan oeq half %lhs, %rhs457 %val1 = select i1 %tst1, half %a, half %b458 store half %val1, ptr @varhalf459 ret void460}461 462define void @test_vsel32ugt_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {463; CHECK-LABEL: test_vsel32ugt_nnan:464; CHECK: @ %bb.0:465; CHECK-NEXT: vldr.16 s0, [r2]466; CHECK-NEXT: vldr.16 s2, [r3]467; CHECK-NEXT: vldr.16 s4, [r0]468; CHECK-NEXT: vldr.16 s6, [r1]469; CHECK-NEXT: movw r0, :lower16:varhalf470; CHECK-NEXT: vcmp.f16 s4, s6471; CHECK-NEXT: movt r0, :upper16:varhalf472; CHECK-NEXT: vmrs APSR_nzcv, fpscr473; CHECK-NEXT: vselgt.f16 s0, s0, s2474; CHECK-NEXT: vstr.16 s0, [r0]475; CHECK-NEXT: bx lr476 %a = load volatile half, ptr %a_ptr477 %b = load volatile half, ptr %b_ptr478 %lhs = load volatile half, ptr %lhs_ptr479 %rhs = load volatile half, ptr %rhs_ptr480 %tst1 = fcmp nnan ugt half %lhs, %rhs481 %val1 = select i1 %tst1, half %a, half %b482 store half %val1, ptr @varhalf483 ret void484}485 486define void @test_vsel32uge_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {487; CHECK-LABEL: test_vsel32uge_nnan:488; CHECK: @ %bb.0:489; CHECK-NEXT: vldr.16 s0, [r2]490; CHECK-NEXT: vldr.16 s2, [r3]491; CHECK-NEXT: vldr.16 s4, [r0]492; CHECK-NEXT: vldr.16 s6, [r1]493; CHECK-NEXT: movw r0, :lower16:varhalf494; CHECK-NEXT: vcmp.f16 s4, s6495; CHECK-NEXT: movt r0, :upper16:varhalf496; CHECK-NEXT: vmrs APSR_nzcv, fpscr497; CHECK-NEXT: vselge.f16 s0, s0, s2498; CHECK-NEXT: vstr.16 s0, [r0]499; CHECK-NEXT: bx lr500 %a = load volatile half, ptr %a_ptr501 %b = load volatile half, ptr %b_ptr502 %lhs = load volatile half, ptr %lhs_ptr503 %rhs = load volatile half, ptr %rhs_ptr504 %tst1 = fcmp nnan uge half %lhs, %rhs505 %val1 = select i1 %tst1, half %a, half %b506 store half %val1, ptr @varhalf507 ret void508}509 510define void @test_vsel32olt_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {511; CHECK-LABEL: test_vsel32olt_nnan:512; CHECK: @ %bb.0:513; CHECK-NEXT: vldr.16 s0, [r2]514; CHECK-NEXT: vldr.16 s2, [r3]515; CHECK-NEXT: vldr.16 s4, [r0]516; CHECK-NEXT: vldr.16 s6, [r1]517; CHECK-NEXT: movw r0, :lower16:varhalf518; CHECK-NEXT: vcmp.f16 s6, s4519; CHECK-NEXT: movt r0, :upper16:varhalf520; CHECK-NEXT: vmrs APSR_nzcv, fpscr521; CHECK-NEXT: vselgt.f16 s0, s0, s2522; CHECK-NEXT: vstr.16 s0, [r0]523; CHECK-NEXT: bx lr524 %a = load volatile half, ptr %a_ptr525 %b = load volatile half, ptr %b_ptr526 %lhs = load volatile half, ptr %lhs_ptr527 %rhs = load volatile half, ptr %rhs_ptr528 %tst1 = fcmp nnan olt half %lhs, %rhs529 %val1 = select i1 %tst1, half %a, half %b530 store half %val1, ptr @varhalf531 ret void532}533 534define void @test_vsel32ult_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {535; CHECK-LABEL: test_vsel32ult_nnan:536; CHECK: @ %bb.0:537; CHECK-NEXT: vldr.16 s0, [r2]538; CHECK-NEXT: vldr.16 s2, [r3]539; CHECK-NEXT: vldr.16 s4, [r0]540; CHECK-NEXT: vldr.16 s6, [r1]541; CHECK-NEXT: movw r0, :lower16:varhalf542; CHECK-NEXT: vcmp.f16 s6, s4543; CHECK-NEXT: movt r0, :upper16:varhalf544; CHECK-NEXT: vmrs APSR_nzcv, fpscr545; CHECK-NEXT: vselgt.f16 s0, s0, s2546; CHECK-NEXT: vstr.16 s0, [r0]547; CHECK-NEXT: bx lr548 %a = load volatile half, ptr %a_ptr549 %b = load volatile half, ptr %b_ptr550 %lhs = load volatile half, ptr %lhs_ptr551 %rhs = load volatile half, ptr %rhs_ptr552 %tst1 = fcmp nnan ult half %lhs, %rhs553 %val1 = select i1 %tst1, half %a, half %b554 store half %val1, ptr @varhalf555 ret void556}557 558define void @test_vsel32ole_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {559; CHECK-LABEL: test_vsel32ole_nnan:560; CHECK: @ %bb.0:561; CHECK-NEXT: vldr.16 s0, [r2]562; CHECK-NEXT: vldr.16 s2, [r3]563; CHECK-NEXT: vldr.16 s4, [r0]564; CHECK-NEXT: vldr.16 s6, [r1]565; CHECK-NEXT: movw r0, :lower16:varhalf566; CHECK-NEXT: vcmp.f16 s6, s4567; CHECK-NEXT: movt r0, :upper16:varhalf568; CHECK-NEXT: vmrs APSR_nzcv, fpscr569; CHECK-NEXT: vselge.f16 s0, s0, s2570; CHECK-NEXT: vstr.16 s0, [r0]571; CHECK-NEXT: bx lr572 %a = load volatile half, ptr %a_ptr573 %b = load volatile half, ptr %b_ptr574 %lhs = load volatile half, ptr %lhs_ptr575 %rhs = load volatile half, ptr %rhs_ptr576 %tst1 = fcmp nnan ole half %lhs, %rhs577 %val1 = select i1 %tst1, half %a, half %b578 store half %val1, ptr @varhalf579 ret void580}581 582define void @test_vsel32ule_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {583; CHECK-LABEL: test_vsel32ule_nnan:584; CHECK: @ %bb.0:585; CHECK-NEXT: vldr.16 s0, [r2]586; CHECK-NEXT: vldr.16 s2, [r3]587; CHECK-NEXT: vldr.16 s4, [r0]588; CHECK-NEXT: vldr.16 s6, [r1]589; CHECK-NEXT: movw r0, :lower16:varhalf590; CHECK-NEXT: vcmp.f16 s6, s4591; CHECK-NEXT: movt r0, :upper16:varhalf592; CHECK-NEXT: vmrs APSR_nzcv, fpscr593; CHECK-NEXT: vselge.f16 s0, s0, s2594; CHECK-NEXT: vstr.16 s0, [r0]595; CHECK-NEXT: bx lr596 %a = load volatile half, ptr %a_ptr597 %b = load volatile half, ptr %b_ptr598 %lhs = load volatile half, ptr %lhs_ptr599 %rhs = load volatile half, ptr %rhs_ptr600 %tst1 = fcmp nnan ule half %lhs, %rhs601 %val1 = select i1 %tst1, half %a, half %b602 store half %val1, ptr @varhalf603 ret void604}605 606define void @test_vsel32ord_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {607; CHECK-LABEL: test_vsel32ord_nnan:608; CHECK: @ %bb.0:609; CHECK-NEXT: vldr.16 s0, [r2]610; CHECK-NEXT: vldr.16 s2, [r3]611; CHECK-NEXT: vldr.16 s4, [r0]612; CHECK-NEXT: vldr.16 s6, [r1]613; CHECK-NEXT: movw r0, :lower16:varhalf614; CHECK-NEXT: vcmp.f16 s4, s6615; CHECK-NEXT: movt r0, :upper16:varhalf616; CHECK-NEXT: vmrs APSR_nzcv, fpscr617; CHECK-NEXT: vselvs.f16 s0, s2, s0618; CHECK-NEXT: vstr.16 s0, [r0]619; CHECK-NEXT: bx lr620 %a = load volatile half, ptr %a_ptr621 %b = load volatile half, ptr %b_ptr622 %lhs = load volatile half, ptr %lhs_ptr623 %rhs = load volatile half, ptr %rhs_ptr624 %tst1 = fcmp nnan ord half %lhs, %rhs625 %val1 = select i1 %tst1, half %a, half %b626 store half %val1, ptr @varhalf627 ret void628}629 630define void @test_vsel32une_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {631; CHECK-LABEL: test_vsel32une_nnan:632; CHECK: @ %bb.0:633; CHECK-NEXT: vldr.16 s0, [r2]634; CHECK-NEXT: vldr.16 s2, [r3]635; CHECK-NEXT: vldr.16 s4, [r0]636; CHECK-NEXT: vldr.16 s6, [r1]637; CHECK-NEXT: movw r0, :lower16:varhalf638; CHECK-NEXT: vcmp.f16 s4, s6639; CHECK-NEXT: movt r0, :upper16:varhalf640; CHECK-NEXT: vmrs APSR_nzcv, fpscr641; CHECK-NEXT: vseleq.f16 s0, s2, s0642; CHECK-NEXT: vstr.16 s0, [r0]643; CHECK-NEXT: bx lr644 %a = load volatile half, ptr %a_ptr645 %b = load volatile half, ptr %b_ptr646 %lhs = load volatile half, ptr %lhs_ptr647 %rhs = load volatile half, ptr %rhs_ptr648 %tst1 = fcmp nnan une half %lhs, %rhs649 %val1 = select i1 %tst1, half %a, half %b650 store half %val1, ptr @varhalf651 ret void652}653 654define void @test_vsel32uno_nnan(ptr %lhs_ptr, ptr %rhs_ptr, ptr %a_ptr, ptr %b_ptr) {655; CHECK-LABEL: test_vsel32uno_nnan:656; CHECK: @ %bb.0:657; CHECK-NEXT: vldr.16 s0, [r2]658; CHECK-NEXT: vldr.16 s2, [r3]659; CHECK-NEXT: vldr.16 s4, [r0]660; CHECK-NEXT: vldr.16 s6, [r1]661; CHECK-NEXT: movw r0, :lower16:varhalf662; CHECK-NEXT: vcmp.f16 s4, s6663; CHECK-NEXT: movt r0, :upper16:varhalf664; CHECK-NEXT: vmrs APSR_nzcv, fpscr665; CHECK-NEXT: vselvs.f16 s0, s0, s2666; CHECK-NEXT: vstr.16 s0, [r0]667; CHECK-NEXT: bx lr668 %a = load volatile half, ptr %a_ptr669 %b = load volatile half, ptr %b_ptr670 %lhs = load volatile half, ptr %lhs_ptr671 %rhs = load volatile half, ptr %rhs_ptr672 %tst1 = fcmp nnan uno half %lhs, %rhs673 %val1 = select i1 %tst1, half %a, half %b674 store half %val1, ptr @varhalf675 ret void676}677