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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes='print<cost-model>' -mtriple=arm-apple-ios6.0.0 -mcpu=cortex-a8 2>&1 -disable-output | FileCheck %s --check-prefix=COST3; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s4; Make sure that ARM backend with NEON handles vselect.5 6define void @vmax_v4i32(ptr %m, <4 x i32> %a, <4 x i32> %b) {7; CHECK-LABEL: vmax_v4i32:8; CHECK: @ %bb.0:9; CHECK-NEXT: add r1, sp, #810; CHECK-NEXT: vldr d17, [sp]11; CHECK-NEXT: vld1.64 {d18, d19}, [r1]12; CHECK-NEXT: vmov d16, r2, r313; CHECK-NEXT: vmax.s32 q8, q8, q914; CHECK-NEXT: vst1.64 {d16, d17}, [r0]15; CHECK-NEXT: mov pc, lr16 %cmpres = icmp sgt <4 x i32> %a, %b17 %maxres = select <4 x i1> %cmpres, <4 x i32> %a, <4 x i32> %b18 store <4 x i32> %maxres, ptr %m19 ret void20}21 22%T0_10 = type <16 x i16>23%T1_10 = type <16 x i1>24define void @func_blend10(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storeaddr) {25; CHECK-LABEL: func_blend10:26; CHECK: @ %bb.0:27; CHECK-NEXT: vld1.16 {d16, d17}, [r1:128]!28; CHECK-NEXT: vld1.16 {d18, d19}, [r0:128]!29; CHECK-NEXT: vmin.s16 q8, q9, q830; CHECK-NEXT: vld1.64 {d20, d21}, [r1:128]31; CHECK-NEXT: vld1.64 {d18, d19}, [r0:128]32; CHECK-NEXT: vmin.s16 q9, q9, q1033; CHECK-NEXT: vst1.16 {d16, d17}, [r3:128]!34; CHECK-NEXT: vst1.64 {d18, d19}, [r3:128]35; CHECK-NEXT: mov pc, lr36; COST: func_blend1037; COST: cost of 0 {{.*}} icmp38; COST: cost of 4 {{.*}} select39 40 %v0 = load %T0_10, ptr %loadaddr41 %v1 = load %T0_10, ptr %loadaddr242 %c = icmp slt %T0_10 %v0, %v143 %r = select %T1_10 %c, %T0_10 %v0, %T0_10 %v144 store %T0_10 %r, ptr %storeaddr45 ret void46}47 48%T0_14 = type <8 x i32>49%T1_14 = type <8 x i1>50define void @func_blend14(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storeaddr) {51; CHECK-LABEL: func_blend14:52; CHECK: @ %bb.0:53; CHECK-NEXT: vld1.32 {d16, d17}, [r1:128]!54; CHECK-NEXT: vld1.32 {d18, d19}, [r0:128]!55; CHECK-NEXT: vmin.s32 q8, q9, q856; CHECK-NEXT: vld1.64 {d20, d21}, [r1:128]57; CHECK-NEXT: vld1.64 {d18, d19}, [r0:128]58; CHECK-NEXT: vmin.s32 q9, q9, q1059; CHECK-NEXT: vst1.32 {d16, d17}, [r3:128]!60; CHECK-NEXT: vst1.64 {d18, d19}, [r3:128]61; CHECK-NEXT: mov pc, lr62; COST: func_blend1463; COST: cost of 0 {{.*}} icmp64; COST: cost of 4 {{.*}} select65 %v0 = load %T0_14, ptr %loadaddr66 %v1 = load %T0_14, ptr %loadaddr267 %c = icmp slt %T0_14 %v0, %v168 %r = select %T1_14 %c, %T0_14 %v0, %T0_14 %v169 store %T0_14 %r, ptr %storeaddr70 ret void71}72 73%T0_15 = type <16 x i32>74%T1_15 = type <16 x i1>75define void @func_blend15(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storeaddr) {76; CHECK-LABEL: func_blend15:77; CHECK: @ %bb.0:78; CHECK-NEXT: vld1.32 {d16, d17}, [r1:128]!79; CHECK-NEXT: vld1.32 {d18, d19}, [r0:128]!80; CHECK-NEXT: vmin.s32 q8, q9, q881; CHECK-NEXT: vld1.32 {d20, d21}, [r1:128]!82; CHECK-NEXT: vld1.32 {d22, d23}, [r0:128]!83; CHECK-NEXT: vmin.s32 q10, q11, q1084; CHECK-NEXT: vld1.32 {d24, d25}, [r1:128]!85; CHECK-NEXT: vld1.32 {d26, d27}, [r0:128]!86; CHECK-NEXT: vmin.s32 q12, q13, q1287; CHECK-NEXT: vld1.64 {d18, d19}, [r1:128]88; CHECK-NEXT: vld1.64 {d22, d23}, [r0:128]89; CHECK-NEXT: vmin.s32 q9, q11, q990; CHECK-NEXT: vst1.32 {d16, d17}, [r3:128]!91; CHECK-NEXT: vst1.32 {d20, d21}, [r3:128]!92; CHECK-NEXT: vst1.32 {d24, d25}, [r3:128]!93; CHECK-NEXT: vst1.64 {d18, d19}, [r3:128]94; CHECK-NEXT: mov pc, lr95; COST: func_blend1596; COST: cost of 0 {{.*}} icmp97; COST: cost of 8 {{.*}} select98 99 %v0 = load %T0_15, ptr %loadaddr100 %v1 = load %T0_15, ptr %loadaddr2101 %c = icmp slt %T0_15 %v0, %v1102 %r = select %T1_15 %c, %T0_15 %v0, %T0_15 %v1103 store %T0_15 %r, ptr %storeaddr104 ret void105}106 107; We adjusted the cost model of the following selects. When we improve code108; lowering we also need to adjust the cost.109%T0_18 = type <4 x i64>110%T1_18 = type <4 x i1>111define void @func_blend18(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storeaddr) {112; CHECK-LABEL: func_blend18:113; CHECK: @ %bb.0:114; CHECK-NEXT: .save {r4, r5, r6, lr}115; CHECK-NEXT: push {r4, r5, r6, lr}116; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!117; CHECK-NEXT: vld1.64 {d22, d23}, [r0:128]!118; CHECK-NEXT: vmov r4, r6, d16119; CHECK-NEXT: vld1.64 {d18, d19}, [r1:128]120; CHECK-NEXT: vld1.64 {d20, d21}, [r0:128]121; CHECK-NEXT: vmov lr, r12, d18122; CHECK-NEXT: mov r0, #0123; CHECK-NEXT: vmov r2, r1, d20124; CHECK-NEXT: subs r2, r2, lr125; CHECK-NEXT: vmov r2, r5, d22126; CHECK-NEXT: sbcs r1, r1, r12127; CHECK-NEXT: mov r1, #0128; CHECK-NEXT: movlt r1, #1129; CHECK-NEXT: cmp r1, #0130; CHECK-NEXT: mvnne r1, #0131; CHECK-NEXT: subs r2, r2, r4132; CHECK-NEXT: sbcs r6, r5, r6133; CHECK-NEXT: vmov r2, r12, d17134; CHECK-NEXT: vmov r5, r4, d23135; CHECK-NEXT: mov r6, #0136; CHECK-NEXT: movlt r6, #1137; CHECK-NEXT: cmp r6, #0138; CHECK-NEXT: mvnne r6, #0139; CHECK-NEXT: subs r2, r5, r2140; CHECK-NEXT: sbcs r2, r4, r12141; CHECK-NEXT: vmov lr, r12, d19142; CHECK-NEXT: vmov r4, r5, d21143; CHECK-NEXT: mov r2, #0144; CHECK-NEXT: movlt r2, #1145; CHECK-NEXT: cmp r2, #0146; CHECK-NEXT: mvnne r2, #0147; CHECK-NEXT: vdup.32 d25, r2148; CHECK-NEXT: vdup.32 d24, r6149; CHECK-NEXT: vbit q8, q11, q12150; CHECK-NEXT: subs r4, r4, lr151; CHECK-NEXT: sbcs r5, r5, r12152; CHECK-NEXT: movlt r0, #1153; CHECK-NEXT: cmp r0, #0154; CHECK-NEXT: mvnne r0, #0155; CHECK-NEXT: vdup.32 d27, r0156; CHECK-NEXT: vdup.32 d26, r1157; CHECK-NEXT: vbit q9, q10, q13158; CHECK-NEXT: vst1.64 {d16, d17}, [r3:128]!159; CHECK-NEXT: vst1.64 {d18, d19}, [r3:128]160; CHECK-NEXT: pop {r4, r5, r6, lr}161; CHECK-NEXT: mov pc, lr162; COST: func_blend18163; COST: cost of 0 {{.*}} icmp164; COST: cost of 21 {{.*}} select165 %v0 = load %T0_18, ptr %loadaddr166 %v1 = load %T0_18, ptr %loadaddr2167 %c = icmp slt %T0_18 %v0, %v1168 %r = select %T1_18 %c, %T0_18 %v0, %T0_18 %v1169 store %T0_18 %r, ptr %storeaddr170 ret void171}172 173%T0_19 = type <8 x i64>174%T1_19 = type <8 x i1>175define void @func_blend19(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storeaddr) {176; CHECK-LABEL: func_blend19:177; CHECK: @ %bb.0:178; CHECK-NEXT: .save {r4, r5, r6, lr}179; CHECK-NEXT: push {r4, r5, r6, lr}180; CHECK-NEXT: vld1.64 {d28, d29}, [r1:128]!181; CHECK-NEXT: mov lr, #0182; CHECK-NEXT: vld1.64 {d30, d31}, [r0:128]!183; CHECK-NEXT: vld1.64 {d20, d21}, [r1:128]!184; CHECK-NEXT: vld1.64 {d24, d25}, [r0:128]!185; CHECK-NEXT: vld1.64 {d22, d23}, [r1:128]!186; CHECK-NEXT: vld1.64 {d26, d27}, [r0:128]!187; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]188; CHECK-NEXT: vld1.64 {d18, d19}, [r0:128]189; CHECK-NEXT: vmov r0, r12, d16190; CHECK-NEXT: vmov r1, r2, d18191; CHECK-NEXT: subs r0, r1, r0192; CHECK-NEXT: vmov r1, r4, d25193; CHECK-NEXT: sbcs r0, r2, r12194; CHECK-NEXT: mov r12, #0195; CHECK-NEXT: vmov r2, r0, d21196; CHECK-NEXT: movlt r12, #1197; CHECK-NEXT: cmp r12, #0198; CHECK-NEXT: mvnne r12, #0199; CHECK-NEXT: subs r1, r1, r2200; CHECK-NEXT: sbcs r0, r4, r0201; CHECK-NEXT: vmov r2, r4, d24202; CHECK-NEXT: mov r0, #0203; CHECK-NEXT: movlt r0, #1204; CHECK-NEXT: cmp r0, #0205; CHECK-NEXT: mvnne r0, #0206; CHECK-NEXT: vdup.32 d1, r0207; CHECK-NEXT: vmov r0, r1, d20208; CHECK-NEXT: subs r0, r2, r0209; CHECK-NEXT: sbcs r0, r4, r1210; CHECK-NEXT: vmov r2, r4, d26211; CHECK-NEXT: mov r0, #0212; CHECK-NEXT: movlt r0, #1213; CHECK-NEXT: cmp r0, #0214; CHECK-NEXT: mvnne r0, #0215; CHECK-NEXT: vdup.32 d0, r0216; CHECK-NEXT: vmov r0, r1, d22217; CHECK-NEXT: subs r0, r2, r0218; CHECK-NEXT: mov r2, #0219; CHECK-NEXT: sbcs r0, r4, r1220; CHECK-NEXT: vmov r4, r5, d31221; CHECK-NEXT: vmov r0, r1, d29222; CHECK-NEXT: movlt r2, #1223; CHECK-NEXT: cmp r2, #0224; CHECK-NEXT: mvnne r2, #0225; CHECK-NEXT: subs r0, r4, r0226; CHECK-NEXT: sbcs r0, r5, r1227; CHECK-NEXT: vmov r4, r5, d30228; CHECK-NEXT: mov r0, #0229; CHECK-NEXT: movlt r0, #1230; CHECK-NEXT: cmp r0, #0231; CHECK-NEXT: mvnne r0, #0232; CHECK-NEXT: vdup.32 d3, r0233; CHECK-NEXT: vmov r0, r1, d28234; CHECK-NEXT: subs r0, r4, r0235; CHECK-NEXT: sbcs r0, r5, r1236; CHECK-NEXT: vmov r4, r5, d27237; CHECK-NEXT: mov r0, #0238; CHECK-NEXT: movlt r0, #1239; CHECK-NEXT: cmp r0, #0240; CHECK-NEXT: mvnne r0, #0241; CHECK-NEXT: vdup.32 d2, r0242; CHECK-NEXT: vmov r0, r1, d23243; CHECK-NEXT: vbit q14, q15, q1244; CHECK-NEXT: vbit q10, q12, q0245; CHECK-NEXT: subs r0, r4, r0246; CHECK-NEXT: sbcs r0, r5, r1247; CHECK-NEXT: vmov r1, r4, d17248; CHECK-NEXT: vmov r5, r6, d19249; CHECK-NEXT: mov r0, #0250; CHECK-NEXT: movlt r0, #1251; CHECK-NEXT: cmp r0, #0252; CHECK-NEXT: mvnne r0, #0253; CHECK-NEXT: vdup.32 d31, r0254; CHECK-NEXT: vdup.32 d30, r2255; CHECK-NEXT: vbit q11, q13, q15256; CHECK-NEXT: vst1.64 {d28, d29}, [r3:128]!257; CHECK-NEXT: subs r1, r5, r1258; CHECK-NEXT: sbcs r1, r6, r4259; CHECK-NEXT: movlt lr, #1260; CHECK-NEXT: cmp lr, #0261; CHECK-NEXT: mvnne lr, #0262; CHECK-NEXT: vdup.32 d3, lr263; CHECK-NEXT: vdup.32 d2, r12264; CHECK-NEXT: vbit q8, q9, q1265; CHECK-NEXT: vst1.64 {d20, d21}, [r3:128]!266; CHECK-NEXT: vst1.64 {d22, d23}, [r3:128]!267; CHECK-NEXT: vst1.64 {d16, d17}, [r3:128]268; CHECK-NEXT: pop {r4, r5, r6, lr}269; CHECK-NEXT: mov pc, lr270; COST: func_blend19271; COST: cost of 0 {{.*}} icmp272; COST: cost of 54 {{.*}} select273 %v0 = load %T0_19, ptr %loadaddr274 %v1 = load %T0_19, ptr %loadaddr2275 %c = icmp slt %T0_19 %v0, %v1276 %r = select %T1_19 %c, %T0_19 %v0, %T0_19 %v1277 store %T0_19 %r, ptr %storeaddr278 ret void279}280 281%T0_20 = type <16 x i64>282%T1_20 = type <16 x i1>283define void @func_blend20(ptr %loadaddr, ptr %loadaddr2, ptr %blend, ptr %storeaddr) {284; CHECK-LABEL: func_blend20:285; CHECK: @ %bb.0:286; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}287; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}288; CHECK-NEXT: .vsave {d8, d9}289; CHECK-NEXT: vpush {d8, d9}290; CHECK-NEXT: add r8, r1, #64291; CHECK-NEXT: add lr, r0, #64292; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]!293; CHECK-NEXT: mov r12, #0294; CHECK-NEXT: vld1.64 {d24, d25}, [r0:128]!295; CHECK-NEXT: vmov r4, r5, d17296; CHECK-NEXT: vmov r6, r7, d25297; CHECK-NEXT: vld1.64 {d18, d19}, [lr:128]!298; CHECK-NEXT: vld1.64 {d20, d21}, [r8:128]!299; CHECK-NEXT: vld1.64 {d22, d23}, [r8:128]!300; CHECK-NEXT: vld1.64 {d0, d1}, [lr:128]!301; CHECK-NEXT: subs r4, r6, r4302; CHECK-NEXT: sbcs r4, r7, r5303; CHECK-NEXT: vmov r5, r6, d16304; CHECK-NEXT: vmov r7, r2, d24305; CHECK-NEXT: mov r4, #0306; CHECK-NEXT: movlt r4, #1307; CHECK-NEXT: cmp r4, #0308; CHECK-NEXT: mvnne r4, #0309; CHECK-NEXT: vdup.32 d27, r4310; CHECK-NEXT: subs r5, r7, r5311; CHECK-NEXT: sbcs r2, r2, r6312; CHECK-NEXT: vmov r5, r6, d1313; CHECK-NEXT: mov r2, #0314; CHECK-NEXT: movlt r2, #1315; CHECK-NEXT: cmp r2, #0316; CHECK-NEXT: mvnne r2, #0317; CHECK-NEXT: vdup.32 d26, r2318; CHECK-NEXT: vmov r2, r4, d23319; CHECK-NEXT: vbit q8, q12, q13320; CHECK-NEXT: vld1.64 {d24, d25}, [r0:128]!321; CHECK-NEXT: vld1.64 {d26, d27}, [r1:128]!322; CHECK-NEXT: vld1.64 {d28, d29}, [lr:128]!323; CHECK-NEXT: subs r2, r5, r2324; CHECK-NEXT: sbcs r2, r6, r4325; CHECK-NEXT: vmov r4, r5, d22326; CHECK-NEXT: vmov r6, r7, d0327; CHECK-NEXT: mov r2, #0328; CHECK-NEXT: movlt r2, #1329; CHECK-NEXT: cmp r2, #0330; CHECK-NEXT: mvnne r2, #0331; CHECK-NEXT: vdup.32 d3, r2332; CHECK-NEXT: subs r4, r6, r4333; CHECK-NEXT: sbcs r4, r7, r5334; CHECK-NEXT: vmov r2, r5, d27335; CHECK-NEXT: vmov r6, r7, d25336; CHECK-NEXT: mov r4, #0337; CHECK-NEXT: movlt r4, #1338; CHECK-NEXT: cmp r4, #0339; CHECK-NEXT: mvnne r4, #0340; CHECK-NEXT: vdup.32 d2, r4341; CHECK-NEXT: subs r2, r6, r2342; CHECK-NEXT: sbcs r2, r7, r5343; CHECK-NEXT: vmov r6, r7, d24344; CHECK-NEXT: mov r2, #0345; CHECK-NEXT: movlt r2, #1346; CHECK-NEXT: cmp r2, #0347; CHECK-NEXT: mvnne r2, #0348; CHECK-NEXT: vdup.32 d5, r2349; CHECK-NEXT: vmov r2, r5, d26350; CHECK-NEXT: subs r2, r6, r2351; CHECK-NEXT: sbcs r2, r7, r5352; CHECK-NEXT: vmov r6, r7, d19353; CHECK-NEXT: mov r2, #0354; CHECK-NEXT: movlt r2, #1355; CHECK-NEXT: cmp r2, #0356; CHECK-NEXT: mvnne r2, #0357; CHECK-NEXT: vdup.32 d4, r2358; CHECK-NEXT: vmov r2, r5, d21359; CHECK-NEXT: subs r2, r6, r2360; CHECK-NEXT: sbcs r2, r7, r5361; CHECK-NEXT: vmov r6, r7, d18362; CHECK-NEXT: mov r2, #0363; CHECK-NEXT: movlt r2, #1364; CHECK-NEXT: cmp r2, #0365; CHECK-NEXT: mvnne r2, #0366; CHECK-NEXT: vdup.32 d31, r2367; CHECK-NEXT: vmov r2, r5, d20368; CHECK-NEXT: subs r2, r6, r2369; CHECK-NEXT: sbcs r2, r7, r5370; CHECK-NEXT: mov r2, #0371; CHECK-NEXT: movlt r2, #1372; CHECK-NEXT: cmp r2, #0373; CHECK-NEXT: mvnne r2, #0374; CHECK-NEXT: vdup.32 d30, r2375; CHECK-NEXT: vbif q9, q10, q15376; CHECK-NEXT: vld1.64 {d30, d31}, [r8:128]!377; CHECK-NEXT: vld1.64 {d20, d21}, [r8:128]378; CHECK-NEXT: vbit q13, q12, q2379; CHECK-NEXT: vld1.64 {d24, d25}, [lr:128]380; CHECK-NEXT: vmov r2, r7, d21381; CHECK-NEXT: vbit q11, q0, q1382; CHECK-NEXT: mov lr, #0383; CHECK-NEXT: vmov r6, r5, d25384; CHECK-NEXT: vld1.64 {d4, d5}, [r1:128]!385; CHECK-NEXT: vld1.64 {d6, d7}, [r0:128]!386; CHECK-NEXT: vld1.64 {d0, d1}, [r1:128]387; CHECK-NEXT: vld1.64 {d2, d3}, [r0:128]388; CHECK-NEXT: subs r1, r6, r2389; CHECK-NEXT: vmov r0, r6, d2390; CHECK-NEXT: sbcs r1, r5, r7391; CHECK-NEXT: vmov r2, r7, d0392; CHECK-NEXT: movlt lr, #1393; CHECK-NEXT: cmp lr, #0394; CHECK-NEXT: mvnne lr, #0395; CHECK-NEXT: subs r0, r0, r2396; CHECK-NEXT: sbcs r0, r6, r7397; CHECK-NEXT: vmov r2, r7, d30398; CHECK-NEXT: vmov r6, r5, d28399; CHECK-NEXT: mov r0, #0400; CHECK-NEXT: movlt r0, #1401; CHECK-NEXT: cmp r0, #0402; CHECK-NEXT: mvnne r0, #0403; CHECK-NEXT: subs r2, r6, r2404; CHECK-NEXT: sbcs r2, r5, r7405; CHECK-NEXT: vmov r7, r6, d31406; CHECK-NEXT: vmov r5, r4, d29407; CHECK-NEXT: mov r2, #0408; CHECK-NEXT: movlt r2, #1409; CHECK-NEXT: cmp r2, #0410; CHECK-NEXT: mvnne r2, #0411; CHECK-NEXT: subs r7, r5, r7412; CHECK-NEXT: vmov r5, r1, d7413; CHECK-NEXT: sbcs r7, r4, r6414; CHECK-NEXT: mov r4, #0415; CHECK-NEXT: vmov r7, r6, d5416; CHECK-NEXT: movlt r4, #1417; CHECK-NEXT: cmp r4, #0418; CHECK-NEXT: mvnne r4, #0419; CHECK-NEXT: subs r5, r5, r7420; CHECK-NEXT: sbcs r1, r1, r6421; CHECK-NEXT: vmov r6, r7, d6422; CHECK-NEXT: mov r1, #0423; CHECK-NEXT: movlt r1, #1424; CHECK-NEXT: cmp r1, #0425; CHECK-NEXT: mvnne r1, #0426; CHECK-NEXT: vdup.32 d9, r1427; CHECK-NEXT: vmov r1, r5, d4428; CHECK-NEXT: subs r1, r6, r1429; CHECK-NEXT: sbcs r1, r7, r5430; CHECK-NEXT: vmov r6, r7, d3431; CHECK-NEXT: mov r1, #0432; CHECK-NEXT: movlt r1, #1433; CHECK-NEXT: cmp r1, #0434; CHECK-NEXT: mvnne r1, #0435; CHECK-NEXT: vdup.32 d8, r1436; CHECK-NEXT: vmov r1, r5, d1437; CHECK-NEXT: vbit q2, q3, q4438; CHECK-NEXT: vdup.32 d9, r4439; CHECK-NEXT: vdup.32 d8, r2440; CHECK-NEXT: subs r1, r6, r1441; CHECK-NEXT: sbcs r1, r7, r5442; CHECK-NEXT: vmov r5, r6, d24443; CHECK-NEXT: mov r1, #0444; CHECK-NEXT: movlt r1, #1445; CHECK-NEXT: cmp r1, #0446; CHECK-NEXT: mvnne r1, #0447; CHECK-NEXT: vdup.32 d7, r1448; CHECK-NEXT: vmov r1, r4, d20449; CHECK-NEXT: vdup.32 d6, r0450; CHECK-NEXT: subs r1, r5, r1451; CHECK-NEXT: mov r1, r3452; CHECK-NEXT: sbcs r0, r6, r4453; CHECK-NEXT: vst1.64 {d16, d17}, [r1:128]!454; CHECK-NEXT: vorr q8, q4, q4455; CHECK-NEXT: movlt r12, #1456; CHECK-NEXT: cmp r12, #0457; CHECK-NEXT: vbsl q8, q14, q15458; CHECK-NEXT: vdup.32 d29, lr459; CHECK-NEXT: vorr q15, q3, q3460; CHECK-NEXT: mvnne r12, #0461; CHECK-NEXT: vdup.32 d28, r12462; CHECK-NEXT: add r0, r3, #64463; CHECK-NEXT: vbsl q15, q1, q0464; CHECK-NEXT: vst1.64 {d26, d27}, [r1:128]!465; CHECK-NEXT: vbit q10, q12, q14466; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]!467; CHECK-NEXT: vst1.64 {d22, d23}, [r0:128]!468; CHECK-NEXT: vst1.64 {d4, d5}, [r1:128]!469; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]!470; CHECK-NEXT: vst1.64 {d30, d31}, [r1:128]471; CHECK-NEXT: vst1.64 {d20, d21}, [r0:128]472; CHECK-NEXT: vpop {d8, d9}473; CHECK-NEXT: pop {r4, r5, r6, r7, r8, lr}474; CHECK-NEXT: mov pc, lr475; COST: func_blend20476; COST: cost of 0 {{.*}} icmp477; COST: cost of 108 {{.*}} select478 %v0 = load %T0_20, ptr %loadaddr479 %v1 = load %T0_20, ptr %loadaddr2480 %c = icmp slt %T0_20 %v0, %v1481 %r = select %T1_20 %c, %T0_20 %v0, %T0_20 %v1482 store %T0_20 %r, ptr %storeaddr483 ret void484}485