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1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3define <8 x i8> @vshls8(ptr %A, ptr %B) nounwind {4;CHECK-LABEL: vshls8:5;CHECK: vshl.u86 %tmp1 = load <8 x i8>, ptr %A7 %tmp2 = load <8 x i8>, ptr %B8 %tmp3 = shl <8 x i8> %tmp1, %tmp29 ret <8 x i8> %tmp310}11 12define <4 x i16> @vshls16(ptr %A, ptr %B) nounwind {13;CHECK-LABEL: vshls16:14;CHECK: vshl.u1615 %tmp1 = load <4 x i16>, ptr %A16 %tmp2 = load <4 x i16>, ptr %B17 %tmp3 = shl <4 x i16> %tmp1, %tmp218 ret <4 x i16> %tmp319}20 21define <2 x i32> @vshls32(ptr %A, ptr %B) nounwind {22;CHECK-LABEL: vshls32:23;CHECK: vshl.u3224 %tmp1 = load <2 x i32>, ptr %A25 %tmp2 = load <2 x i32>, ptr %B26 %tmp3 = shl <2 x i32> %tmp1, %tmp227 ret <2 x i32> %tmp328}29 30define <1 x i64> @vshls64(ptr %A, ptr %B) nounwind {31;CHECK-LABEL: vshls64:32;CHECK: vshl.u6433 %tmp1 = load <1 x i64>, ptr %A34 %tmp2 = load <1 x i64>, ptr %B35 %tmp3 = shl <1 x i64> %tmp1, %tmp236 ret <1 x i64> %tmp337}38 39define <8 x i8> @vshli8(ptr %A) nounwind {40;CHECK-LABEL: vshli8:41;CHECK: vshl.i842 %tmp1 = load <8 x i8>, ptr %A43 %tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >44 ret <8 x i8> %tmp245}46 47define <4 x i16> @vshli16(ptr %A) nounwind {48;CHECK-LABEL: vshli16:49;CHECK: vshl.i1650 %tmp1 = load <4 x i16>, ptr %A51 %tmp2 = shl <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >52 ret <4 x i16> %tmp253}54 55define <2 x i32> @vshli32(ptr %A) nounwind {56;CHECK-LABEL: vshli32:57;CHECK: vshl.i3258 %tmp1 = load <2 x i32>, ptr %A59 %tmp2 = shl <2 x i32> %tmp1, < i32 31, i32 31 >60 ret <2 x i32> %tmp261}62 63define <1 x i64> @vshli64(ptr %A) nounwind {64;CHECK-LABEL: vshli64:65;CHECK: vshl.i6466 %tmp1 = load <1 x i64>, ptr %A67 %tmp2 = shl <1 x i64> %tmp1, < i64 63 >68 ret <1 x i64> %tmp269}70 71define <16 x i8> @vshlQs8(ptr %A, ptr %B) nounwind {72;CHECK-LABEL: vshlQs8:73;CHECK: vshl.u874 %tmp1 = load <16 x i8>, ptr %A75 %tmp2 = load <16 x i8>, ptr %B76 %tmp3 = shl <16 x i8> %tmp1, %tmp277 ret <16 x i8> %tmp378}79 80define <8 x i16> @vshlQs16(ptr %A, ptr %B) nounwind {81;CHECK-LABEL: vshlQs16:82;CHECK: vshl.u1683 %tmp1 = load <8 x i16>, ptr %A84 %tmp2 = load <8 x i16>, ptr %B85 %tmp3 = shl <8 x i16> %tmp1, %tmp286 ret <8 x i16> %tmp387}88 89define <4 x i32> @vshlQs32(ptr %A, ptr %B) nounwind {90;CHECK-LABEL: vshlQs32:91;CHECK: vshl.u3292 %tmp1 = load <4 x i32>, ptr %A93 %tmp2 = load <4 x i32>, ptr %B94 %tmp3 = shl <4 x i32> %tmp1, %tmp295 ret <4 x i32> %tmp396}97 98define <2 x i64> @vshlQs64(ptr %A, ptr %B) nounwind {99;CHECK-LABEL: vshlQs64:100;CHECK: vshl.u64101 %tmp1 = load <2 x i64>, ptr %A102 %tmp2 = load <2 x i64>, ptr %B103 %tmp3 = shl <2 x i64> %tmp1, %tmp2104 ret <2 x i64> %tmp3105}106 107define <16 x i8> @vshlQi8(ptr %A) nounwind {108;CHECK-LABEL: vshlQi8:109;CHECK: vshl.i8110 %tmp1 = load <16 x i8>, ptr %A111 %tmp2 = shl <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >112 ret <16 x i8> %tmp2113}114 115define <8 x i16> @vshlQi16(ptr %A) nounwind {116;CHECK-LABEL: vshlQi16:117;CHECK: vshl.i16118 %tmp1 = load <8 x i16>, ptr %A119 %tmp2 = shl <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >120 ret <8 x i16> %tmp2121}122 123define <4 x i32> @vshlQi32(ptr %A) nounwind {124;CHECK-LABEL: vshlQi32:125;CHECK: vshl.i32126 %tmp1 = load <4 x i32>, ptr %A127 %tmp2 = shl <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >128 ret <4 x i32> %tmp2129}130 131define <2 x i64> @vshlQi64(ptr %A) nounwind {132;CHECK-LABEL: vshlQi64:133;CHECK: vshl.i64134 %tmp1 = load <2 x i64>, ptr %A135 %tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 >136 ret <2 x i64> %tmp2137}138 139define <8 x i8> @vlshru8(ptr %A, ptr %B) nounwind {140;CHECK-LABEL: vlshru8:141;CHECK: vneg.s8142;CHECK: vshl.u8143 %tmp1 = load <8 x i8>, ptr %A144 %tmp2 = load <8 x i8>, ptr %B145 %tmp3 = lshr <8 x i8> %tmp1, %tmp2146 ret <8 x i8> %tmp3147}148 149define <4 x i16> @vlshru16(ptr %A, ptr %B) nounwind {150;CHECK-LABEL: vlshru16:151;CHECK: vneg.s16152;CHECK: vshl.u16153 %tmp1 = load <4 x i16>, ptr %A154 %tmp2 = load <4 x i16>, ptr %B155 %tmp3 = lshr <4 x i16> %tmp1, %tmp2156 ret <4 x i16> %tmp3157}158 159define <2 x i32> @vlshru32(ptr %A, ptr %B) nounwind {160;CHECK-LABEL: vlshru32:161;CHECK: vneg.s32162;CHECK: vshl.u32163 %tmp1 = load <2 x i32>, ptr %A164 %tmp2 = load <2 x i32>, ptr %B165 %tmp3 = lshr <2 x i32> %tmp1, %tmp2166 ret <2 x i32> %tmp3167}168 169define <1 x i64> @vlshru64(ptr %A, ptr %B) nounwind {170;CHECK-LABEL: vlshru64:171;CHECK: vsub.i64172;CHECK: vshl.u64173 %tmp1 = load <1 x i64>, ptr %A174 %tmp2 = load <1 x i64>, ptr %B175 %tmp3 = lshr <1 x i64> %tmp1, %tmp2176 ret <1 x i64> %tmp3177}178 179define <8 x i8> @vlshri8(ptr %A) nounwind {180;CHECK-LABEL: vlshri8:181;CHECK: vshr.u8182 %tmp1 = load <8 x i8>, ptr %A183 %tmp2 = lshr <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >184 ret <8 x i8> %tmp2185}186 187define <4 x i16> @vlshri16(ptr %A) nounwind {188;CHECK-LABEL: vlshri16:189;CHECK: vshr.u16190 %tmp1 = load <4 x i16>, ptr %A191 %tmp2 = lshr <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >192 ret <4 x i16> %tmp2193}194 195define <2 x i32> @vlshri32(ptr %A) nounwind {196;CHECK-LABEL: vlshri32:197;CHECK: vshr.u32198 %tmp1 = load <2 x i32>, ptr %A199 %tmp2 = lshr <2 x i32> %tmp1, < i32 31, i32 31 >200 ret <2 x i32> %tmp2201}202 203define <1 x i64> @vlshri64(ptr %A) nounwind {204;CHECK-LABEL: vlshri64:205;CHECK: vshr.u64206 %tmp1 = load <1 x i64>, ptr %A207 %tmp2 = lshr <1 x i64> %tmp1, < i64 63 >208 ret <1 x i64> %tmp2209}210 211define <16 x i8> @vlshrQu8(ptr %A, ptr %B) nounwind {212;CHECK-LABEL: vlshrQu8:213;CHECK: vneg.s8214;CHECK: vshl.u8215 %tmp1 = load <16 x i8>, ptr %A216 %tmp2 = load <16 x i8>, ptr %B217 %tmp3 = lshr <16 x i8> %tmp1, %tmp2218 ret <16 x i8> %tmp3219}220 221define <8 x i16> @vlshrQu16(ptr %A, ptr %B) nounwind {222;CHECK-LABEL: vlshrQu16:223;CHECK: vneg.s16224;CHECK: vshl.u16225 %tmp1 = load <8 x i16>, ptr %A226 %tmp2 = load <8 x i16>, ptr %B227 %tmp3 = lshr <8 x i16> %tmp1, %tmp2228 ret <8 x i16> %tmp3229}230 231define <4 x i32> @vlshrQu32(ptr %A, ptr %B) nounwind {232;CHECK-LABEL: vlshrQu32:233;CHECK: vneg.s32234;CHECK: vshl.u32235 %tmp1 = load <4 x i32>, ptr %A236 %tmp2 = load <4 x i32>, ptr %B237 %tmp3 = lshr <4 x i32> %tmp1, %tmp2238 ret <4 x i32> %tmp3239}240 241define <2 x i64> @vlshrQu64(ptr %A, ptr %B) nounwind {242;CHECK-LABEL: vlshrQu64:243;CHECK: vsub.i64244;CHECK: vshl.u64245 %tmp1 = load <2 x i64>, ptr %A246 %tmp2 = load <2 x i64>, ptr %B247 %tmp3 = lshr <2 x i64> %tmp1, %tmp2248 ret <2 x i64> %tmp3249}250 251define <16 x i8> @vlshrQi8(ptr %A) nounwind {252;CHECK-LABEL: vlshrQi8:253;CHECK: vshr.u8254 %tmp1 = load <16 x i8>, ptr %A255 %tmp2 = lshr <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >256 ret <16 x i8> %tmp2257}258 259define <8 x i16> @vlshrQi16(ptr %A) nounwind {260;CHECK-LABEL: vlshrQi16:261;CHECK: vshr.u16262 %tmp1 = load <8 x i16>, ptr %A263 %tmp2 = lshr <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >264 ret <8 x i16> %tmp2265}266 267define <4 x i32> @vlshrQi32(ptr %A) nounwind {268;CHECK-LABEL: vlshrQi32:269;CHECK: vshr.u32270 %tmp1 = load <4 x i32>, ptr %A271 %tmp2 = lshr <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >272 ret <4 x i32> %tmp2273}274 275define <2 x i64> @vlshrQi64(ptr %A) nounwind {276;CHECK-LABEL: vlshrQi64:277;CHECK: vshr.u64278 %tmp1 = load <2 x i64>, ptr %A279 %tmp2 = lshr <2 x i64> %tmp1, < i64 63, i64 63 >280 ret <2 x i64> %tmp2281}282 283; Example that requires splitting and expanding a vector shift.284define <2 x i64> @update(<2 x i64> %val) nounwind readnone {285entry:286 %shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1]287 ret <2 x i64> %shr288}289 290define <8 x i8> @vashrs8(ptr %A, ptr %B) nounwind {291;CHECK-LABEL: vashrs8:292;CHECK: vneg.s8293;CHECK: vshl.s8294 %tmp1 = load <8 x i8>, ptr %A295 %tmp2 = load <8 x i8>, ptr %B296 %tmp3 = ashr <8 x i8> %tmp1, %tmp2297 ret <8 x i8> %tmp3298}299 300define <4 x i16> @vashrs16(ptr %A, ptr %B) nounwind {301;CHECK-LABEL: vashrs16:302;CHECK: vneg.s16303;CHECK: vshl.s16304 %tmp1 = load <4 x i16>, ptr %A305 %tmp2 = load <4 x i16>, ptr %B306 %tmp3 = ashr <4 x i16> %tmp1, %tmp2307 ret <4 x i16> %tmp3308}309 310define <2 x i32> @vashrs32(ptr %A, ptr %B) nounwind {311;CHECK-LABEL: vashrs32:312;CHECK: vneg.s32313;CHECK: vshl.s32314 %tmp1 = load <2 x i32>, ptr %A315 %tmp2 = load <2 x i32>, ptr %B316 %tmp3 = ashr <2 x i32> %tmp1, %tmp2317 ret <2 x i32> %tmp3318}319 320define <1 x i64> @vashrs64(ptr %A, ptr %B) nounwind {321;CHECK-LABEL: vashrs64:322;CHECK: vsub.i64323;CHECK: vshl.s64324 %tmp1 = load <1 x i64>, ptr %A325 %tmp2 = load <1 x i64>, ptr %B326 %tmp3 = ashr <1 x i64> %tmp1, %tmp2327 ret <1 x i64> %tmp3328}329 330define <8 x i8> @vashri8(ptr %A) nounwind {331;CHECK-LABEL: vashri8:332;CHECK: vshr.s8333 %tmp1 = load <8 x i8>, ptr %A334 %tmp2 = ashr <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >335 ret <8 x i8> %tmp2336}337 338define <4 x i16> @vashri16(ptr %A) nounwind {339;CHECK-LABEL: vashri16:340;CHECK: vshr.s16341 %tmp1 = load <4 x i16>, ptr %A342 %tmp2 = ashr <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >343 ret <4 x i16> %tmp2344}345 346define <2 x i32> @vashri32(ptr %A) nounwind {347;CHECK-LABEL: vashri32:348;CHECK: vshr.s32349 %tmp1 = load <2 x i32>, ptr %A350 %tmp2 = ashr <2 x i32> %tmp1, < i32 31, i32 31 >351 ret <2 x i32> %tmp2352}353 354define <1 x i64> @vashri64(ptr %A) nounwind {355;CHECK-LABEL: vashri64:356;CHECK: vshr.s64357 %tmp1 = load <1 x i64>, ptr %A358 %tmp2 = ashr <1 x i64> %tmp1, < i64 63 >359 ret <1 x i64> %tmp2360}361 362define <16 x i8> @vashrQs8(ptr %A, ptr %B) nounwind {363;CHECK-LABEL: vashrQs8:364;CHECK: vneg.s8365;CHECK: vshl.s8366 %tmp1 = load <16 x i8>, ptr %A367 %tmp2 = load <16 x i8>, ptr %B368 %tmp3 = ashr <16 x i8> %tmp1, %tmp2369 ret <16 x i8> %tmp3370}371 372define <8 x i16> @vashrQs16(ptr %A, ptr %B) nounwind {373;CHECK-LABEL: vashrQs16:374;CHECK: vneg.s16375;CHECK: vshl.s16376 %tmp1 = load <8 x i16>, ptr %A377 %tmp2 = load <8 x i16>, ptr %B378 %tmp3 = ashr <8 x i16> %tmp1, %tmp2379 ret <8 x i16> %tmp3380}381 382define <4 x i32> @vashrQs32(ptr %A, ptr %B) nounwind {383;CHECK-LABEL: vashrQs32:384;CHECK: vneg.s32385;CHECK: vshl.s32386 %tmp1 = load <4 x i32>, ptr %A387 %tmp2 = load <4 x i32>, ptr %B388 %tmp3 = ashr <4 x i32> %tmp1, %tmp2389 ret <4 x i32> %tmp3390}391 392define <2 x i64> @vashrQs64(ptr %A, ptr %B) nounwind {393;CHECK-LABEL: vashrQs64:394;CHECK: vsub.i64395;CHECK: vshl.s64396 %tmp1 = load <2 x i64>, ptr %A397 %tmp2 = load <2 x i64>, ptr %B398 %tmp3 = ashr <2 x i64> %tmp1, %tmp2399 ret <2 x i64> %tmp3400}401 402define <16 x i8> @vashrQi8(ptr %A) nounwind {403;CHECK-LABEL: vashrQi8:404;CHECK: vshr.s8405 %tmp1 = load <16 x i8>, ptr %A406 %tmp2 = ashr <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >407 ret <16 x i8> %tmp2408}409 410define <8 x i16> @vashrQi16(ptr %A) nounwind {411;CHECK-LABEL: vashrQi16:412;CHECK: vshr.s16413 %tmp1 = load <8 x i16>, ptr %A414 %tmp2 = ashr <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >415 ret <8 x i16> %tmp2416}417 418define <4 x i32> @vashrQi32(ptr %A) nounwind {419;CHECK-LABEL: vashrQi32:420;CHECK: vshr.s32421 %tmp1 = load <4 x i32>, ptr %A422 %tmp2 = ashr <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >423 ret <4 x i32> %tmp2424}425 426define <2 x i64> @vashrQi64(ptr %A) nounwind {427;CHECK-LABEL: vashrQi64:428;CHECK: vshr.s64429 %tmp1 = load <2 x i64>, ptr %A430 %tmp2 = ashr <2 x i64> %tmp1, < i64 63, i64 63 >431 ret <2 x i64> %tmp2432}433