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1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3define <8 x i8> @vsli8(ptr %A, ptr %B) nounwind {4;CHECK-LABEL: vsli8:5;CHECK: vsli.86 %tmp1 = load <8 x i8>, ptr %A7 %tmp2 = load <8 x i8>, ptr %B8 %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)9 ret <8 x i8> %tmp310}11 12define <4 x i16> @vsli16(ptr %A, ptr %B) nounwind {13;CHECK-LABEL: vsli16:14;CHECK: vsli.1615 %tmp1 = load <4 x i16>, ptr %A16 %tmp2 = load <4 x i16>, ptr %B17 %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)18 ret <4 x i16> %tmp319}20 21define <2 x i32> @vsli32(ptr %A, ptr %B) nounwind {22;CHECK-LABEL: vsli32:23;CHECK: vsli.3224 %tmp1 = load <2 x i32>, ptr %A25 %tmp2 = load <2 x i32>, ptr %B26 %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 31, i32 31 >)27 ret <2 x i32> %tmp328}29 30define <1 x i64> @vsli64(ptr %A, ptr %B) nounwind {31;CHECK-LABEL: vsli64:32;CHECK: vsli.6433 %tmp1 = load <1 x i64>, ptr %A34 %tmp2 = load <1 x i64>, ptr %B35 %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 63 >)36 ret <1 x i64> %tmp337}38 39define <16 x i8> @vsliQ8(ptr %A, ptr %B) nounwind {40;CHECK-LABEL: vsliQ8:41;CHECK: vsli.842 %tmp1 = load <16 x i8>, ptr %A43 %tmp2 = load <16 x i8>, ptr %B44 %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)45 ret <16 x i8> %tmp346}47 48define <8 x i16> @vsliQ16(ptr %A, ptr %B) nounwind {49;CHECK-LABEL: vsliQ16:50;CHECK: vsli.1651 %tmp1 = load <8 x i16>, ptr %A52 %tmp2 = load <8 x i16>, ptr %B53 %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)54 ret <8 x i16> %tmp355}56 57define <4 x i32> @vsliQ32(ptr %A, ptr %B) nounwind {58;CHECK-LABEL: vsliQ32:59;CHECK: vsli.3260 %tmp1 = load <4 x i32>, ptr %A61 %tmp2 = load <4 x i32>, ptr %B62 %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)63 ret <4 x i32> %tmp364}65 66define <2 x i64> @vsliQ64(ptr %A, ptr %B) nounwind {67;CHECK-LABEL: vsliQ64:68;CHECK: vsli.6469 %tmp1 = load <2 x i64>, ptr %A70 %tmp2 = load <2 x i64>, ptr %B71 %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 63, i64 63 >)72 ret <2 x i64> %tmp373}74 75define <8 x i8> @vsri8(ptr %A, ptr %B) nounwind {76;CHECK-LABEL: vsri8:77;CHECK: vsri.878 %tmp1 = load <8 x i8>, ptr %A79 %tmp2 = load <8 x i8>, ptr %B80 %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)81 ret <8 x i8> %tmp382}83 84define <4 x i16> @vsri16(ptr %A, ptr %B) nounwind {85;CHECK-LABEL: vsri16:86;CHECK: vsri.1687 %tmp1 = load <4 x i16>, ptr %A88 %tmp2 = load <4 x i16>, ptr %B89 %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)90 ret <4 x i16> %tmp391}92 93define <2 x i32> @vsri32(ptr %A, ptr %B) nounwind {94;CHECK-LABEL: vsri32:95;CHECK: vsri.3296 %tmp1 = load <2 x i32>, ptr %A97 %tmp2 = load <2 x i32>, ptr %B98 %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)99 ret <2 x i32> %tmp3100}101 102define <1 x i64> @vsri64(ptr %A, ptr %B) nounwind {103;CHECK-LABEL: vsri64:104;CHECK: vsri.64105 %tmp1 = load <1 x i64>, ptr %A106 %tmp2 = load <1 x i64>, ptr %B107 %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 -64 >)108 ret <1 x i64> %tmp3109}110 111define <16 x i8> @vsriQ8(ptr %A, ptr %B) nounwind {112;CHECK-LABEL: vsriQ8:113;CHECK: vsri.8114 %tmp1 = load <16 x i8>, ptr %A115 %tmp2 = load <16 x i8>, ptr %B116 %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)117 ret <16 x i8> %tmp3118}119 120define <8 x i16> @vsriQ16(ptr %A, ptr %B) nounwind {121;CHECK-LABEL: vsriQ16:122;CHECK: vsri.16123 %tmp1 = load <8 x i16>, ptr %A124 %tmp2 = load <8 x i16>, ptr %B125 %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)126 ret <8 x i16> %tmp3127}128 129define <4 x i32> @vsriQ32(ptr %A, ptr %B) nounwind {130;CHECK-LABEL: vsriQ32:131;CHECK: vsri.32132 %tmp1 = load <4 x i32>, ptr %A133 %tmp2 = load <4 x i32>, ptr %B134 %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)135 ret <4 x i32> %tmp3136}137 138define <2 x i64> @vsriQ64(ptr %A, ptr %B) nounwind {139;CHECK-LABEL: vsriQ64:140;CHECK: vsri.64141 %tmp1 = load <2 x i64>, ptr %A142 %tmp2 = load <2 x i64>, ptr %B143 %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)144 ret <2 x i64> %tmp3145}146 147declare <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone148declare <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone149declare <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone150declare <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64>, <1 x i64>, <1 x i64>) nounwind readnone151 152declare <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone153declare <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone154declare <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone155declare <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone156