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1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3define <8 x i8> @vshls8(ptr %A, ptr %B) nounwind {4;CHECK-LABEL: vshls8:5;CHECK: vshl.s86 %tmp1 = load <8 x i8>, ptr %A7 %tmp2 = load <8 x i8>, ptr %B8 %tmp3 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)9 ret <8 x i8> %tmp310}11 12define <4 x i16> @vshls16(ptr %A, ptr %B) nounwind {13;CHECK-LABEL: vshls16:14;CHECK: vshl.s1615 %tmp1 = load <4 x i16>, ptr %A16 %tmp2 = load <4 x i16>, ptr %B17 %tmp3 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)18 ret <4 x i16> %tmp319}20 21define <2 x i32> @vshls32(ptr %A, ptr %B) nounwind {22;CHECK-LABEL: vshls32:23;CHECK: vshl.s3224 %tmp1 = load <2 x i32>, ptr %A25 %tmp2 = load <2 x i32>, ptr %B26 %tmp3 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)27 ret <2 x i32> %tmp328}29 30define <1 x i64> @vshls64(ptr %A, ptr %B) nounwind {31;CHECK-LABEL: vshls64:32;CHECK: vshl.s6433 %tmp1 = load <1 x i64>, ptr %A34 %tmp2 = load <1 x i64>, ptr %B35 %tmp3 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)36 ret <1 x i64> %tmp337}38 39define <8 x i8> @vshlu8(ptr %A, ptr %B) nounwind {40;CHECK-LABEL: vshlu8:41;CHECK: vshl.u842 %tmp1 = load <8 x i8>, ptr %A43 %tmp2 = load <8 x i8>, ptr %B44 %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)45 ret <8 x i8> %tmp346}47 48define <4 x i16> @vshlu16(ptr %A, ptr %B) nounwind {49;CHECK-LABEL: vshlu16:50;CHECK: vshl.u1651 %tmp1 = load <4 x i16>, ptr %A52 %tmp2 = load <4 x i16>, ptr %B53 %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)54 ret <4 x i16> %tmp355}56 57define <2 x i32> @vshlu32(ptr %A, ptr %B) nounwind {58;CHECK-LABEL: vshlu32:59;CHECK: vshl.u3260 %tmp1 = load <2 x i32>, ptr %A61 %tmp2 = load <2 x i32>, ptr %B62 %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)63 ret <2 x i32> %tmp364}65 66define <1 x i64> @vshlu64(ptr %A, ptr %B) nounwind {67;CHECK-LABEL: vshlu64:68;CHECK: vshl.u6469 %tmp1 = load <1 x i64>, ptr %A70 %tmp2 = load <1 x i64>, ptr %B71 %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)72 ret <1 x i64> %tmp373}74 75define <16 x i8> @vshlQs8(ptr %A, ptr %B) nounwind {76;CHECK-LABEL: vshlQs8:77;CHECK: vshl.s878 %tmp1 = load <16 x i8>, ptr %A79 %tmp2 = load <16 x i8>, ptr %B80 %tmp3 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)81 ret <16 x i8> %tmp382}83 84define <8 x i16> @vshlQs16(ptr %A, ptr %B) nounwind {85;CHECK-LABEL: vshlQs16:86;CHECK: vshl.s1687 %tmp1 = load <8 x i16>, ptr %A88 %tmp2 = load <8 x i16>, ptr %B89 %tmp3 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)90 ret <8 x i16> %tmp391}92 93define <4 x i32> @vshlQs32(ptr %A, ptr %B) nounwind {94;CHECK-LABEL: vshlQs32:95;CHECK: vshl.s3296 %tmp1 = load <4 x i32>, ptr %A97 %tmp2 = load <4 x i32>, ptr %B98 %tmp3 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)99 ret <4 x i32> %tmp3100}101 102define <2 x i64> @vshlQs64(ptr %A, ptr %B) nounwind {103;CHECK-LABEL: vshlQs64:104;CHECK: vshl.s64105 %tmp1 = load <2 x i64>, ptr %A106 %tmp2 = load <2 x i64>, ptr %B107 %tmp3 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)108 ret <2 x i64> %tmp3109}110 111define <16 x i8> @vshlQu8(ptr %A, ptr %B) nounwind {112;CHECK-LABEL: vshlQu8:113;CHECK: vshl.u8114 %tmp1 = load <16 x i8>, ptr %A115 %tmp2 = load <16 x i8>, ptr %B116 %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)117 ret <16 x i8> %tmp3118}119 120define <8 x i16> @vshlQu16(ptr %A, ptr %B) nounwind {121;CHECK-LABEL: vshlQu16:122;CHECK: vshl.u16123 %tmp1 = load <8 x i16>, ptr %A124 %tmp2 = load <8 x i16>, ptr %B125 %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)126 ret <8 x i16> %tmp3127}128 129define <4 x i32> @vshlQu32(ptr %A, ptr %B) nounwind {130;CHECK-LABEL: vshlQu32:131;CHECK: vshl.u32132 %tmp1 = load <4 x i32>, ptr %A133 %tmp2 = load <4 x i32>, ptr %B134 %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)135 ret <4 x i32> %tmp3136}137 138define <2 x i64> @vshlQu64(ptr %A, ptr %B) nounwind {139;CHECK-LABEL: vshlQu64:140;CHECK: vshl.u64141 %tmp1 = load <2 x i64>, ptr %A142 %tmp2 = load <2 x i64>, ptr %B143 %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)144 ret <2 x i64> %tmp3145}146 147; For left shifts by immediates, the signedness is irrelevant.148; Test a mix of both signed and unsigned intrinsics.149 150define <8 x i8> @vshli8(ptr %A) nounwind {151;CHECK-LABEL: vshli8:152;CHECK: vshl.i8153 %tmp1 = load <8 x i8>, ptr %A154 %tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)155 ret <8 x i8> %tmp2156}157 158define <4 x i16> @vshli16(ptr %A) nounwind {159;CHECK-LABEL: vshli16:160;CHECK: vshl.i16161 %tmp1 = load <4 x i16>, ptr %A162 %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)163 ret <4 x i16> %tmp2164}165 166define <2 x i32> @vshli32(ptr %A) nounwind {167;CHECK-LABEL: vshli32:168;CHECK: vshl.i32169 %tmp1 = load <2 x i32>, ptr %A170 %tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)171 ret <2 x i32> %tmp2172}173 174define <1 x i64> @vshli64(ptr %A) nounwind {175;CHECK-LABEL: vshli64:176;CHECK: vshl.i64177 %tmp1 = load <1 x i64>, ptr %A178 %tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)179 ret <1 x i64> %tmp2180}181 182define <16 x i8> @vshlQi8(ptr %A) nounwind {183;CHECK-LABEL: vshlQi8:184;CHECK: vshl.i8185 %tmp1 = load <16 x i8>, ptr %A186 %tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)187 ret <16 x i8> %tmp2188}189 190define <8 x i16> @vshlQi16(ptr %A) nounwind {191;CHECK-LABEL: vshlQi16:192;CHECK: vshl.i16193 %tmp1 = load <8 x i16>, ptr %A194 %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)195 ret <8 x i16> %tmp2196}197 198define <4 x i32> @vshlQi32(ptr %A) nounwind {199;CHECK-LABEL: vshlQi32:200;CHECK: vshl.i32201 %tmp1 = load <4 x i32>, ptr %A202 %tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)203 ret <4 x i32> %tmp2204}205 206define <2 x i64> @vshlQi64(ptr %A) nounwind {207;CHECK-LABEL: vshlQi64:208;CHECK: vshl.i64209 %tmp1 = load <2 x i64>, ptr %A210 %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)211 ret <2 x i64> %tmp2212}213 214; Right shift by immediate:215 216define <8 x i8> @vshrs8(ptr %A) nounwind {217;CHECK-LABEL: vshrs8:218;CHECK: vshr.s8219 %tmp1 = load <8 x i8>, ptr %A220 %tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)221 ret <8 x i8> %tmp2222}223 224define <4 x i16> @vshrs16(ptr %A) nounwind {225;CHECK-LABEL: vshrs16:226;CHECK: vshr.s16227 %tmp1 = load <4 x i16>, ptr %A228 %tmp2 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)229 ret <4 x i16> %tmp2230}231 232define <2 x i32> @vshrs32(ptr %A) nounwind {233;CHECK-LABEL: vshrs32:234;CHECK: vshr.s32235 %tmp1 = load <2 x i32>, ptr %A236 %tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)237 ret <2 x i32> %tmp2238}239 240define <1 x i64> @vshrs64(ptr %A) nounwind {241;CHECK-LABEL: vshrs64:242;CHECK: vshr.s64243 %tmp1 = load <1 x i64>, ptr %A244 %tmp2 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)245 ret <1 x i64> %tmp2246}247 248define <8 x i8> @vshru8(ptr %A) nounwind {249;CHECK-LABEL: vshru8:250;CHECK: vshr.u8251 %tmp1 = load <8 x i8>, ptr %A252 %tmp2 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)253 ret <8 x i8> %tmp2254}255 256define <4 x i16> @vshru16(ptr %A) nounwind {257;CHECK-LABEL: vshru16:258;CHECK: vshr.u16259 %tmp1 = load <4 x i16>, ptr %A260 %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)261 ret <4 x i16> %tmp2262}263 264define <2 x i32> @vshru32(ptr %A) nounwind {265;CHECK-LABEL: vshru32:266;CHECK: vshr.u32267 %tmp1 = load <2 x i32>, ptr %A268 %tmp2 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)269 ret <2 x i32> %tmp2270}271 272define <1 x i64> @vshru64(ptr %A) nounwind {273;CHECK-LABEL: vshru64:274;CHECK: vshr.u64275 %tmp1 = load <1 x i64>, ptr %A276 %tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)277 ret <1 x i64> %tmp2278}279 280define <16 x i8> @vshrQs8(ptr %A) nounwind {281;CHECK-LABEL: vshrQs8:282;CHECK: vshr.s8283 %tmp1 = load <16 x i8>, ptr %A284 %tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)285 ret <16 x i8> %tmp2286}287 288define <8 x i16> @vshrQs16(ptr %A) nounwind {289;CHECK-LABEL: vshrQs16:290;CHECK: vshr.s16291 %tmp1 = load <8 x i16>, ptr %A292 %tmp2 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)293 ret <8 x i16> %tmp2294}295 296define <4 x i32> @vshrQs32(ptr %A) nounwind {297;CHECK-LABEL: vshrQs32:298;CHECK: vshr.s32299 %tmp1 = load <4 x i32>, ptr %A300 %tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)301 ret <4 x i32> %tmp2302}303 304define <2 x i64> @vshrQs64(ptr %A) nounwind {305;CHECK-LABEL: vshrQs64:306;CHECK: vshr.s64307 %tmp1 = load <2 x i64>, ptr %A308 %tmp2 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)309 ret <2 x i64> %tmp2310}311 312define <16 x i8> @vshrQu8(ptr %A) nounwind {313;CHECK-LABEL: vshrQu8:314;CHECK: vshr.u8315 %tmp1 = load <16 x i8>, ptr %A316 %tmp2 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)317 ret <16 x i8> %tmp2318}319 320define <8 x i16> @vshrQu16(ptr %A) nounwind {321;CHECK-LABEL: vshrQu16:322;CHECK: vshr.u16323 %tmp1 = load <8 x i16>, ptr %A324 %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)325 ret <8 x i16> %tmp2326}327 328define <4 x i32> @vshrQu32(ptr %A) nounwind {329;CHECK-LABEL: vshrQu32:330;CHECK: vshr.u32331 %tmp1 = load <4 x i32>, ptr %A332 %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)333 ret <4 x i32> %tmp2334}335 336define <2 x i64> @vshrQu64(ptr %A) nounwind {337;CHECK-LABEL: vshrQu64:338;CHECK: vshr.u64339 %tmp1 = load <2 x i64>, ptr %A340 %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)341 ret <2 x i64> %tmp2342}343 344declare <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone345declare <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone346declare <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone347declare <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone348 349declare <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone350declare <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone351declare <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone352declare <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone353 354declare <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone355declare <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone356declare <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone357declare <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone358 359declare <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone360declare <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone361declare <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone362declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone363 364define <8 x i8> @vrshls8(ptr %A, ptr %B) nounwind {365;CHECK-LABEL: vrshls8:366;CHECK: vrshl.s8367 %tmp1 = load <8 x i8>, ptr %A368 %tmp2 = load <8 x i8>, ptr %B369 %tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)370 ret <8 x i8> %tmp3371}372 373define <4 x i16> @vrshls16(ptr %A, ptr %B) nounwind {374;CHECK-LABEL: vrshls16:375;CHECK: vrshl.s16376 %tmp1 = load <4 x i16>, ptr %A377 %tmp2 = load <4 x i16>, ptr %B378 %tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)379 ret <4 x i16> %tmp3380}381 382define <2 x i32> @vrshls32(ptr %A, ptr %B) nounwind {383;CHECK-LABEL: vrshls32:384;CHECK: vrshl.s32385 %tmp1 = load <2 x i32>, ptr %A386 %tmp2 = load <2 x i32>, ptr %B387 %tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)388 ret <2 x i32> %tmp3389}390 391define <1 x i64> @vrshls64(ptr %A, ptr %B) nounwind {392;CHECK-LABEL: vrshls64:393;CHECK: vrshl.s64394 %tmp1 = load <1 x i64>, ptr %A395 %tmp2 = load <1 x i64>, ptr %B396 %tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)397 ret <1 x i64> %tmp3398}399 400define <8 x i8> @vrshlu8(ptr %A, ptr %B) nounwind {401;CHECK-LABEL: vrshlu8:402;CHECK: vrshl.u8403 %tmp1 = load <8 x i8>, ptr %A404 %tmp2 = load <8 x i8>, ptr %B405 %tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)406 ret <8 x i8> %tmp3407}408 409define <4 x i16> @vrshlu16(ptr %A, ptr %B) nounwind {410;CHECK-LABEL: vrshlu16:411;CHECK: vrshl.u16412 %tmp1 = load <4 x i16>, ptr %A413 %tmp2 = load <4 x i16>, ptr %B414 %tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)415 ret <4 x i16> %tmp3416}417 418define <2 x i32> @vrshlu32(ptr %A, ptr %B) nounwind {419;CHECK-LABEL: vrshlu32:420;CHECK: vrshl.u32421 %tmp1 = load <2 x i32>, ptr %A422 %tmp2 = load <2 x i32>, ptr %B423 %tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)424 ret <2 x i32> %tmp3425}426 427define <1 x i64> @vrshlu64(ptr %A, ptr %B) nounwind {428;CHECK-LABEL: vrshlu64:429;CHECK: vrshl.u64430 %tmp1 = load <1 x i64>, ptr %A431 %tmp2 = load <1 x i64>, ptr %B432 %tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)433 ret <1 x i64> %tmp3434}435 436define <16 x i8> @vrshlQs8(ptr %A, ptr %B) nounwind {437;CHECK-LABEL: vrshlQs8:438;CHECK: vrshl.s8439 %tmp1 = load <16 x i8>, ptr %A440 %tmp2 = load <16 x i8>, ptr %B441 %tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)442 ret <16 x i8> %tmp3443}444 445define <8 x i16> @vrshlQs16(ptr %A, ptr %B) nounwind {446;CHECK-LABEL: vrshlQs16:447;CHECK: vrshl.s16448 %tmp1 = load <8 x i16>, ptr %A449 %tmp2 = load <8 x i16>, ptr %B450 %tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)451 ret <8 x i16> %tmp3452}453 454define <4 x i32> @vrshlQs32(ptr %A, ptr %B) nounwind {455;CHECK-LABEL: vrshlQs32:456;CHECK: vrshl.s32457 %tmp1 = load <4 x i32>, ptr %A458 %tmp2 = load <4 x i32>, ptr %B459 %tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)460 ret <4 x i32> %tmp3461}462 463define <2 x i64> @vrshlQs64(ptr %A, ptr %B) nounwind {464;CHECK-LABEL: vrshlQs64:465;CHECK: vrshl.s64466 %tmp1 = load <2 x i64>, ptr %A467 %tmp2 = load <2 x i64>, ptr %B468 %tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)469 ret <2 x i64> %tmp3470}471 472define <16 x i8> @vrshlQu8(ptr %A, ptr %B) nounwind {473;CHECK-LABEL: vrshlQu8:474;CHECK: vrshl.u8475 %tmp1 = load <16 x i8>, ptr %A476 %tmp2 = load <16 x i8>, ptr %B477 %tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)478 ret <16 x i8> %tmp3479}480 481define <8 x i16> @vrshlQu16(ptr %A, ptr %B) nounwind {482;CHECK-LABEL: vrshlQu16:483;CHECK: vrshl.u16484 %tmp1 = load <8 x i16>, ptr %A485 %tmp2 = load <8 x i16>, ptr %B486 %tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)487 ret <8 x i16> %tmp3488}489 490define <4 x i32> @vrshlQu32(ptr %A, ptr %B) nounwind {491;CHECK-LABEL: vrshlQu32:492;CHECK: vrshl.u32493 %tmp1 = load <4 x i32>, ptr %A494 %tmp2 = load <4 x i32>, ptr %B495 %tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)496 ret <4 x i32> %tmp3497}498 499define <2 x i64> @vrshlQu64(ptr %A, ptr %B) nounwind {500;CHECK-LABEL: vrshlQu64:501;CHECK: vrshl.u64502 %tmp1 = load <2 x i64>, ptr %A503 %tmp2 = load <2 x i64>, ptr %B504 %tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)505 ret <2 x i64> %tmp3506}507 508define <8 x i8> @vrshrs8(ptr %A) nounwind {509;CHECK-LABEL: vrshrs8:510;CHECK: vrshr.s8511 %tmp1 = load <8 x i8>, ptr %A512 %tmp2 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)513 ret <8 x i8> %tmp2514}515 516define <4 x i16> @vrshrs16(ptr %A) nounwind {517;CHECK-LABEL: vrshrs16:518;CHECK: vrshr.s16519 %tmp1 = load <4 x i16>, ptr %A520 %tmp2 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)521 ret <4 x i16> %tmp2522}523 524define <2 x i32> @vrshrs32(ptr %A) nounwind {525;CHECK-LABEL: vrshrs32:526;CHECK: vrshr.s32527 %tmp1 = load <2 x i32>, ptr %A528 %tmp2 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)529 ret <2 x i32> %tmp2530}531 532define <1 x i64> @vrshrs64(ptr %A) nounwind {533;CHECK-LABEL: vrshrs64:534;CHECK: vrshr.s64535 %tmp1 = load <1 x i64>, ptr %A536 %tmp2 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)537 ret <1 x i64> %tmp2538}539 540define <8 x i8> @vrshru8(ptr %A) nounwind {541;CHECK-LABEL: vrshru8:542;CHECK: vrshr.u8543 %tmp1 = load <8 x i8>, ptr %A544 %tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)545 ret <8 x i8> %tmp2546}547 548define <4 x i16> @vrshru16(ptr %A) nounwind {549;CHECK-LABEL: vrshru16:550;CHECK: vrshr.u16551 %tmp1 = load <4 x i16>, ptr %A552 %tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)553 ret <4 x i16> %tmp2554}555 556define <2 x i32> @vrshru32(ptr %A) nounwind {557;CHECK-LABEL: vrshru32:558;CHECK: vrshr.u32559 %tmp1 = load <2 x i32>, ptr %A560 %tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)561 ret <2 x i32> %tmp2562}563 564define <1 x i64> @vrshru64(ptr %A) nounwind {565;CHECK-LABEL: vrshru64:566;CHECK: vrshr.u64567 %tmp1 = load <1 x i64>, ptr %A568 %tmp2 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)569 ret <1 x i64> %tmp2570}571 572define <16 x i8> @vrshrQs8(ptr %A) nounwind {573;CHECK-LABEL: vrshrQs8:574;CHECK: vrshr.s8575 %tmp1 = load <16 x i8>, ptr %A576 %tmp2 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)577 ret <16 x i8> %tmp2578}579 580define <8 x i16> @vrshrQs16(ptr %A) nounwind {581;CHECK-LABEL: vrshrQs16:582;CHECK: vrshr.s16583 %tmp1 = load <8 x i16>, ptr %A584 %tmp2 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)585 ret <8 x i16> %tmp2586}587 588define <4 x i32> @vrshrQs32(ptr %A) nounwind {589;CHECK-LABEL: vrshrQs32:590;CHECK: vrshr.s32591 %tmp1 = load <4 x i32>, ptr %A592 %tmp2 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)593 ret <4 x i32> %tmp2594}595 596define <2 x i64> @vrshrQs64(ptr %A) nounwind {597;CHECK-LABEL: vrshrQs64:598;CHECK: vrshr.s64599 %tmp1 = load <2 x i64>, ptr %A600 %tmp2 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)601 ret <2 x i64> %tmp2602}603 604define <16 x i8> @vrshrQu8(ptr %A) nounwind {605;CHECK-LABEL: vrshrQu8:606;CHECK: vrshr.u8607 %tmp1 = load <16 x i8>, ptr %A608 %tmp2 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)609 ret <16 x i8> %tmp2610}611 612define <8 x i16> @vrshrQu16(ptr %A) nounwind {613;CHECK-LABEL: vrshrQu16:614;CHECK: vrshr.u16615 %tmp1 = load <8 x i16>, ptr %A616 %tmp2 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)617 ret <8 x i16> %tmp2618}619 620define <4 x i32> @vrshrQu32(ptr %A) nounwind {621;CHECK-LABEL: vrshrQu32:622;CHECK: vrshr.u32623 %tmp1 = load <4 x i32>, ptr %A624 %tmp2 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)625 ret <4 x i32> %tmp2626}627 628define <2 x i64> @vrshrQu64(ptr %A) nounwind {629;CHECK-LABEL: vrshrQu64:630;CHECK: vrshr.u64631 %tmp1 = load <2 x i64>, ptr %A632 %tmp2 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)633 ret <2 x i64> %tmp2634}635 636declare <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone637declare <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone638declare <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone639declare <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone640 641declare <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone642declare <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone643declare <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone644declare <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone645 646declare <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone647declare <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone648declare <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone649declare <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone650 651declare <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone652declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone653declare <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone654declare <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone655