117 lines · plain
1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3define <8 x i16> @vshlls8(ptr %A) nounwind {4;CHECK-LABEL: vshlls8:5;CHECK: vshll.s86 %tmp1 = load <8 x i8>, ptr %A7 %sext = sext <8 x i8> %tmp1 to <8 x i16>8 %shift = shl <8 x i16> %sext, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>9 ret <8 x i16> %shift10}11 12define <4 x i32> @vshlls16(ptr %A) nounwind {13;CHECK-LABEL: vshlls16:14;CHECK: vshll.s1615 %tmp1 = load <4 x i16>, ptr %A16 %sext = sext <4 x i16> %tmp1 to <4 x i32>17 %shift = shl <4 x i32> %sext, <i32 15, i32 15, i32 15, i32 15>18 ret <4 x i32> %shift19}20 21define <2 x i64> @vshlls32(ptr %A) nounwind {22;CHECK-LABEL: vshlls32:23;CHECK: vshll.s3224 %tmp1 = load <2 x i32>, ptr %A25 %sext = sext <2 x i32> %tmp1 to <2 x i64>26 %shift = shl <2 x i64> %sext, <i64 31, i64 31>27 ret <2 x i64> %shift28}29 30define <8 x i16> @vshllu8(ptr %A) nounwind {31;CHECK-LABEL: vshllu8:32;CHECK: vshll.u833 %tmp1 = load <8 x i8>, ptr %A34 %zext = zext <8 x i8> %tmp1 to <8 x i16>35 %shift = shl <8 x i16> %zext, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>36 ret <8 x i16> %shift37}38 39define <4 x i32> @vshllu16(ptr %A) nounwind {40;CHECK-LABEL: vshllu16:41;CHECK: vshll.u1642 %tmp1 = load <4 x i16>, ptr %A43 %zext = zext <4 x i16> %tmp1 to <4 x i32>44 %shift = shl <4 x i32> %zext, <i32 15, i32 15, i32 15, i32 15>45 ret <4 x i32> %shift46}47 48define <2 x i64> @vshllu32(ptr %A) nounwind {49;CHECK-LABEL: vshllu32:50;CHECK: vshll.u3251 %tmp1 = load <2 x i32>, ptr %A52 %zext = zext <2 x i32> %tmp1 to <2 x i64>53 %shift = shl <2 x i64> %zext, <i64 31, i64 31>54 ret <2 x i64> %shift55}56 57; The following tests use the maximum shift count, so the signedness is58; irrelevant. Test both signed and unsigned versions.59define <8 x i16> @vshlli8(ptr %A) nounwind {60;CHECK-LABEL: vshlli8:61;CHECK: vshll.i862 %tmp1 = load <8 x i8>, ptr %A63 %sext = sext <8 x i8> %tmp1 to <8 x i16>64 %shift = shl <8 x i16> %sext, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>65 ret <8 x i16> %shift66}67 68define <4 x i32> @vshlli16(ptr %A) nounwind {69;CHECK-LABEL: vshlli16:70;CHECK: vshll.i1671 %tmp1 = load <4 x i16>, ptr %A72 %zext = zext <4 x i16> %tmp1 to <4 x i32>73 %shift = shl <4 x i32> %zext, <i32 16, i32 16, i32 16, i32 16>74 ret <4 x i32> %shift75}76 77define <2 x i64> @vshlli32(ptr %A) nounwind {78;CHECK-LABEL: vshlli32:79;CHECK: vshll.i3280 %tmp1 = load <2 x i32>, ptr %A81 %zext = zext <2 x i32> %tmp1 to <2 x i64>82 %shift = shl <2 x i64> %zext, <i64 32, i64 32>83 ret <2 x i64> %shift84}85 86; And these have a shift just out of range so separate vmovl and vshl87; instructions are needed.88define <8 x i16> @vshllu8_bad(ptr %A) nounwind {89; CHECK-LABEL: vshllu8_bad:90; CHECK: vmovl.u891; CHECK: vshl.i1692 %tmp1 = load <8 x i8>, ptr %A93 %zext = zext <8 x i8> %tmp1 to <8 x i16>94 %shift = shl <8 x i16> %zext, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>95 ret <8 x i16> %shift96}97 98define <4 x i32> @vshlls16_bad(ptr %A) nounwind {99; CHECK-LABEL: vshlls16_bad:100; CHECK: vmovl.u16101; CHECK: vshl.i32102 %tmp1 = load <4 x i16>, ptr %A103 %sext = sext <4 x i16> %tmp1 to <4 x i32>104 %shift = shl <4 x i32> %sext, <i32 17, i32 17, i32 17, i32 17>105 ret <4 x i32> %shift106}107 108define <2 x i64> @vshllu32_bad(ptr %A) nounwind {109; CHECK-LABEL: vshllu32_bad:110; CHECK: vmovl.u32111; CHECK: vshl.i64112 %tmp1 = load <2 x i32>, ptr %A113 %zext = zext <2 x i32> %tmp1 to <2 x i64>114 %shift = shl <2 x i64> %zext, <i64 33, i64 33>115 ret <2 x i64> %shift116}117