342 lines · plain
1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s2 3define <8 x i8> @vsras8(ptr %A, ptr %B) nounwind {4;CHECK-LABEL: vsras8:5;CHECK: vsra.s86 %tmp1 = load <8 x i8>, ptr %A7 %tmp2 = load <8 x i8>, ptr %B8 %tmp3 = ashr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >9 %tmp4 = add <8 x i8> %tmp1, %tmp310 ret <8 x i8> %tmp411}12 13define <4 x i16> @vsras16(ptr %A, ptr %B) nounwind {14;CHECK-LABEL: vsras16:15;CHECK: vsra.s1616 %tmp1 = load <4 x i16>, ptr %A17 %tmp2 = load <4 x i16>, ptr %B18 %tmp3 = ashr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >19 %tmp4 = add <4 x i16> %tmp1, %tmp320 ret <4 x i16> %tmp421}22 23define <2 x i32> @vsras32(ptr %A, ptr %B) nounwind {24;CHECK-LABEL: vsras32:25;CHECK: vsra.s3226 %tmp1 = load <2 x i32>, ptr %A27 %tmp2 = load <2 x i32>, ptr %B28 %tmp3 = ashr <2 x i32> %tmp2, < i32 31, i32 31 >29 %tmp4 = add <2 x i32> %tmp1, %tmp330 ret <2 x i32> %tmp431}32 33define <1 x i64> @vsras64(ptr %A, ptr %B) nounwind {34;CHECK-LABEL: vsras64:35;CHECK: vsra.s6436 %tmp1 = load <1 x i64>, ptr %A37 %tmp2 = load <1 x i64>, ptr %B38 %tmp3 = ashr <1 x i64> %tmp2, < i64 63 >39 %tmp4 = add <1 x i64> %tmp1, %tmp340 ret <1 x i64> %tmp441}42 43define <16 x i8> @vsraQs8(ptr %A, ptr %B) nounwind {44;CHECK-LABEL: vsraQs8:45;CHECK: vsra.s846 %tmp1 = load <16 x i8>, ptr %A47 %tmp2 = load <16 x i8>, ptr %B48 %tmp3 = ashr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >49 %tmp4 = add <16 x i8> %tmp1, %tmp350 ret <16 x i8> %tmp451}52 53define <8 x i16> @vsraQs16(ptr %A, ptr %B) nounwind {54;CHECK-LABEL: vsraQs16:55;CHECK: vsra.s1656 %tmp1 = load <8 x i16>, ptr %A57 %tmp2 = load <8 x i16>, ptr %B58 %tmp3 = ashr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >59 %tmp4 = add <8 x i16> %tmp1, %tmp360 ret <8 x i16> %tmp461}62 63define <4 x i32> @vsraQs32(ptr %A, ptr %B) nounwind {64;CHECK-LABEL: vsraQs32:65;CHECK: vsra.s3266 %tmp1 = load <4 x i32>, ptr %A67 %tmp2 = load <4 x i32>, ptr %B68 %tmp3 = ashr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >69 %tmp4 = add <4 x i32> %tmp1, %tmp370 ret <4 x i32> %tmp471}72 73define <2 x i64> @vsraQs64(ptr %A, ptr %B) nounwind {74;CHECK-LABEL: vsraQs64:75;CHECK: vsra.s6476 %tmp1 = load <2 x i64>, ptr %A77 %tmp2 = load <2 x i64>, ptr %B78 %tmp3 = ashr <2 x i64> %tmp2, < i64 63, i64 63 >79 %tmp4 = add <2 x i64> %tmp1, %tmp380 ret <2 x i64> %tmp481}82 83define <8 x i8> @vsrau8(ptr %A, ptr %B) nounwind {84;CHECK-LABEL: vsrau8:85;CHECK: vsra.u886 %tmp1 = load <8 x i8>, ptr %A87 %tmp2 = load <8 x i8>, ptr %B88 %tmp3 = lshr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >89 %tmp4 = add <8 x i8> %tmp1, %tmp390 ret <8 x i8> %tmp491}92 93define <4 x i16> @vsrau16(ptr %A, ptr %B) nounwind {94;CHECK-LABEL: vsrau16:95;CHECK: vsra.u1696 %tmp1 = load <4 x i16>, ptr %A97 %tmp2 = load <4 x i16>, ptr %B98 %tmp3 = lshr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >99 %tmp4 = add <4 x i16> %tmp1, %tmp3100 ret <4 x i16> %tmp4101}102 103define <2 x i32> @vsrau32(ptr %A, ptr %B) nounwind {104;CHECK-LABEL: vsrau32:105;CHECK: vsra.u32106 %tmp1 = load <2 x i32>, ptr %A107 %tmp2 = load <2 x i32>, ptr %B108 %tmp3 = lshr <2 x i32> %tmp2, < i32 31, i32 31 >109 %tmp4 = add <2 x i32> %tmp1, %tmp3110 ret <2 x i32> %tmp4111}112 113define <1 x i64> @vsrau64(ptr %A, ptr %B) nounwind {114;CHECK-LABEL: vsrau64:115;CHECK: vsra.u64116 %tmp1 = load <1 x i64>, ptr %A117 %tmp2 = load <1 x i64>, ptr %B118 %tmp3 = lshr <1 x i64> %tmp2, < i64 63 >119 %tmp4 = add <1 x i64> %tmp1, %tmp3120 ret <1 x i64> %tmp4121}122 123define <16 x i8> @vsraQu8(ptr %A, ptr %B) nounwind {124;CHECK-LABEL: vsraQu8:125;CHECK: vsra.u8126 %tmp1 = load <16 x i8>, ptr %A127 %tmp2 = load <16 x i8>, ptr %B128 %tmp3 = lshr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >129 %tmp4 = add <16 x i8> %tmp1, %tmp3130 ret <16 x i8> %tmp4131}132 133define <8 x i16> @vsraQu16(ptr %A, ptr %B) nounwind {134;CHECK-LABEL: vsraQu16:135;CHECK: vsra.u16136 %tmp1 = load <8 x i16>, ptr %A137 %tmp2 = load <8 x i16>, ptr %B138 %tmp3 = lshr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >139 %tmp4 = add <8 x i16> %tmp1, %tmp3140 ret <8 x i16> %tmp4141}142 143define <4 x i32> @vsraQu32(ptr %A, ptr %B) nounwind {144;CHECK-LABEL: vsraQu32:145;CHECK: vsra.u32146 %tmp1 = load <4 x i32>, ptr %A147 %tmp2 = load <4 x i32>, ptr %B148 %tmp3 = lshr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >149 %tmp4 = add <4 x i32> %tmp1, %tmp3150 ret <4 x i32> %tmp4151}152 153define <2 x i64> @vsraQu64(ptr %A, ptr %B) nounwind {154;CHECK-LABEL: vsraQu64:155;CHECK: vsra.u64156 %tmp1 = load <2 x i64>, ptr %A157 %tmp2 = load <2 x i64>, ptr %B158 %tmp3 = lshr <2 x i64> %tmp2, < i64 63, i64 63 >159 %tmp4 = add <2 x i64> %tmp1, %tmp3160 ret <2 x i64> %tmp4161}162 163define <8 x i8> @vrsras8(ptr %A, ptr %B) nounwind {164;CHECK-LABEL: vrsras8:165;CHECK: vrsra.s8166 %tmp1 = load <8 x i8>, ptr %A167 %tmp2 = load <8 x i8>, ptr %B168 %tmp3 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)169 %tmp4 = add <8 x i8> %tmp1, %tmp3170 ret <8 x i8> %tmp4171}172 173define <4 x i16> @vrsras16(ptr %A, ptr %B) nounwind {174;CHECK-LABEL: vrsras16:175;CHECK: vrsra.s16176 %tmp1 = load <4 x i16>, ptr %A177 %tmp2 = load <4 x i16>, ptr %B178 %tmp3 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)179 %tmp4 = add <4 x i16> %tmp1, %tmp3180 ret <4 x i16> %tmp4181}182 183define <2 x i32> @vrsras32(ptr %A, ptr %B) nounwind {184;CHECK-LABEL: vrsras32:185;CHECK: vrsra.s32186 %tmp1 = load <2 x i32>, ptr %A187 %tmp2 = load <2 x i32>, ptr %B188 %tmp3 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)189 %tmp4 = add <2 x i32> %tmp1, %tmp3190 ret <2 x i32> %tmp4191}192 193define <1 x i64> @vrsras64(ptr %A, ptr %B) nounwind {194;CHECK-LABEL: vrsras64:195;CHECK: vrsra.s64196 %tmp1 = load <1 x i64>, ptr %A197 %tmp2 = load <1 x i64>, ptr %B198 %tmp3 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)199 %tmp4 = add <1 x i64> %tmp1, %tmp3200 ret <1 x i64> %tmp4201}202 203define <8 x i8> @vrsrau8(ptr %A, ptr %B) nounwind {204;CHECK-LABEL: vrsrau8:205;CHECK: vrsra.u8206 %tmp1 = load <8 x i8>, ptr %A207 %tmp2 = load <8 x i8>, ptr %B208 %tmp3 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)209 %tmp4 = add <8 x i8> %tmp1, %tmp3210 ret <8 x i8> %tmp4211}212 213define <4 x i16> @vrsrau16(ptr %A, ptr %B) nounwind {214;CHECK-LABEL: vrsrau16:215;CHECK: vrsra.u16216 %tmp1 = load <4 x i16>, ptr %A217 %tmp2 = load <4 x i16>, ptr %B218 %tmp3 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)219 %tmp4 = add <4 x i16> %tmp1, %tmp3220 ret <4 x i16> %tmp4221}222 223define <2 x i32> @vrsrau32(ptr %A, ptr %B) nounwind {224;CHECK-LABEL: vrsrau32:225;CHECK: vrsra.u32226 %tmp1 = load <2 x i32>, ptr %A227 %tmp2 = load <2 x i32>, ptr %B228 %tmp3 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)229 %tmp4 = add <2 x i32> %tmp1, %tmp3230 ret <2 x i32> %tmp4231}232 233define <1 x i64> @vrsrau64(ptr %A, ptr %B) nounwind {234;CHECK-LABEL: vrsrau64:235;CHECK: vrsra.u64236 %tmp1 = load <1 x i64>, ptr %A237 %tmp2 = load <1 x i64>, ptr %B238 %tmp3 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp2, <1 x i64> < i64 -64 >)239 %tmp4 = add <1 x i64> %tmp1, %tmp3240 ret <1 x i64> %tmp4241}242 243define <16 x i8> @vrsraQs8(ptr %A, ptr %B) nounwind {244;CHECK-LABEL: vrsraQs8:245;CHECK: vrsra.s8246 %tmp1 = load <16 x i8>, ptr %A247 %tmp2 = load <16 x i8>, ptr %B248 %tmp3 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)249 %tmp4 = add <16 x i8> %tmp1, %tmp3250 ret <16 x i8> %tmp4251}252 253define <8 x i16> @vrsraQs16(ptr %A, ptr %B) nounwind {254;CHECK-LABEL: vrsraQs16:255;CHECK: vrsra.s16256 %tmp1 = load <8 x i16>, ptr %A257 %tmp2 = load <8 x i16>, ptr %B258 %tmp3 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)259 %tmp4 = add <8 x i16> %tmp1, %tmp3260 ret <8 x i16> %tmp4261}262 263define <4 x i32> @vrsraQs32(ptr %A, ptr %B) nounwind {264;CHECK-LABEL: vrsraQs32:265;CHECK: vrsra.s32266 %tmp1 = load <4 x i32>, ptr %A267 %tmp2 = load <4 x i32>, ptr %B268 %tmp3 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)269 %tmp4 = add <4 x i32> %tmp1, %tmp3270 ret <4 x i32> %tmp4271}272 273define <2 x i64> @vrsraQs64(ptr %A, ptr %B) nounwind {274;CHECK-LABEL: vrsraQs64:275;CHECK: vrsra.s64276 %tmp1 = load <2 x i64>, ptr %A277 %tmp2 = load <2 x i64>, ptr %B278 %tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)279 %tmp4 = add <2 x i64> %tmp1, %tmp3280 ret <2 x i64> %tmp4281}282 283define <16 x i8> @vrsraQu8(ptr %A, ptr %B) nounwind {284;CHECK-LABEL: vrsraQu8:285;CHECK: vrsra.u8286 %tmp1 = load <16 x i8>, ptr %A287 %tmp2 = load <16 x i8>, ptr %B288 %tmp3 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)289 %tmp4 = add <16 x i8> %tmp1, %tmp3290 ret <16 x i8> %tmp4291}292 293define <8 x i16> @vrsraQu16(ptr %A, ptr %B) nounwind {294;CHECK-LABEL: vrsraQu16:295;CHECK: vrsra.u16296 %tmp1 = load <8 x i16>, ptr %A297 %tmp2 = load <8 x i16>, ptr %B298 %tmp3 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)299 %tmp4 = add <8 x i16> %tmp1, %tmp3300 ret <8 x i16> %tmp4301}302 303define <4 x i32> @vrsraQu32(ptr %A, ptr %B) nounwind {304;CHECK-LABEL: vrsraQu32:305;CHECK: vrsra.u32306 %tmp1 = load <4 x i32>, ptr %A307 %tmp2 = load <4 x i32>, ptr %B308 %tmp3 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)309 %tmp4 = add <4 x i32> %tmp1, %tmp3310 ret <4 x i32> %tmp4311}312 313define <2 x i64> @vrsraQu64(ptr %A, ptr %B) nounwind {314;CHECK-LABEL: vrsraQu64:315;CHECK: vrsra.u64316 %tmp1 = load <2 x i64>, ptr %A317 %tmp2 = load <2 x i64>, ptr %B318 %tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)319 %tmp4 = add <2 x i64> %tmp1, %tmp3320 ret <2 x i64> %tmp4321}322 323declare <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone324declare <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone325declare <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone326declare <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone327 328declare <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone329declare <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone330declare <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone331declare <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone332 333declare <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone334declare <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone335declare <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone336declare <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone337 338declare <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone339declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone340declare <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone341declare <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone342