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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=armv7a-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s3 4define <8 x i8> @vsubi8(<8 x i8> %A, <8 x i8> %B) {5; CHECK-LABEL: vsubi8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vsub.i8 d0, d0, d18; CHECK-NEXT: bx lr9 %tmp3 = sub <8 x i8> %A, %B10 ret <8 x i8> %tmp311}12 13define <4 x i16> @vsubi16(<4 x i16> %A, <4 x i16> %B) {14; CHECK-LABEL: vsubi16:15; CHECK: @ %bb.0:16; CHECK-NEXT: vsub.i16 d0, d0, d117; CHECK-NEXT: bx lr18 %tmp3 = sub <4 x i16> %A, %B19 ret <4 x i16> %tmp320}21 22define <2 x i32> @vsubi32(<2 x i32> %A, <2 x i32> %B) {23; CHECK-LABEL: vsubi32:24; CHECK: @ %bb.0:25; CHECK-NEXT: vsub.i32 d0, d0, d126; CHECK-NEXT: bx lr27 %tmp3 = sub <2 x i32> %A, %B28 ret <2 x i32> %tmp329}30 31define <1 x i64> @vsubi64(<1 x i64> %A, <1 x i64> %B) {32; CHECK-LABEL: vsubi64:33; CHECK: @ %bb.0:34; CHECK-NEXT: vsub.i64 d0, d0, d135; CHECK-NEXT: bx lr36 %tmp3 = sub <1 x i64> %A, %B37 ret <1 x i64> %tmp338}39 40define <2 x float> @vsubf32(<2 x float> %A, <2 x float> %B) {41; CHECK-LABEL: vsubf32:42; CHECK: @ %bb.0:43; CHECK-NEXT: vsub.f32 d0, d0, d144; CHECK-NEXT: bx lr45 %tmp3 = fsub <2 x float> %A, %B46 ret <2 x float> %tmp347}48 49define <16 x i8> @vsubQi8(<16 x i8> %A, <16 x i8> %B) {50; CHECK-LABEL: vsubQi8:51; CHECK: @ %bb.0:52; CHECK-NEXT: vsub.i8 q0, q0, q153; CHECK-NEXT: bx lr54 %tmp3 = sub <16 x i8> %A, %B55 ret <16 x i8> %tmp356}57 58define <8 x i16> @vsubQi16(<8 x i16> %A, <8 x i16> %B) {59; CHECK-LABEL: vsubQi16:60; CHECK: @ %bb.0:61; CHECK-NEXT: vsub.i16 q0, q0, q162; CHECK-NEXT: bx lr63 %tmp3 = sub <8 x i16> %A, %B64 ret <8 x i16> %tmp365}66 67define <4 x i32> @vsubQi32(<4 x i32> %A, <4 x i32> %B) {68; CHECK-LABEL: vsubQi32:69; CHECK: @ %bb.0:70; CHECK-NEXT: vsub.i32 q0, q0, q171; CHECK-NEXT: bx lr72 %tmp3 = sub <4 x i32> %A, %B73 ret <4 x i32> %tmp374}75 76define <2 x i64> @vsubQi64(<2 x i64> %A, <2 x i64> %B) {77; CHECK-LABEL: vsubQi64:78; CHECK: @ %bb.0:79; CHECK-NEXT: vsub.i64 q0, q0, q180; CHECK-NEXT: bx lr81 %tmp3 = sub <2 x i64> %A, %B82 ret <2 x i64> %tmp383}84 85define <4 x float> @vsubQf32(<4 x float> %A, <4 x float> %B) {86; CHECK-LABEL: vsubQf32:87; CHECK: @ %bb.0:88; CHECK-NEXT: vsub.f32 q0, q0, q189; CHECK-NEXT: bx lr90 %tmp3 = fsub <4 x float> %A, %B91 ret <4 x float> %tmp392}93 94define <8 x i8> @vrsubhni16(<8 x i16> %A, <8 x i16> %B) {95; CHECK-LABEL: vrsubhni16:96; CHECK: @ %bb.0:97; CHECK-NEXT: vrsubhn.i16 d0, q0, q198; CHECK-NEXT: bx lr99 %tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %A, <8 x i16> %B)100 ret <8 x i8> %tmp3101}102 103define <4 x i16> @vrsubhni32(<4 x i32> %A, <4 x i32> %B) {104; CHECK-LABEL: vrsubhni32:105; CHECK: @ %bb.0:106; CHECK-NEXT: vrsubhn.i32 d0, q0, q1107; CHECK-NEXT: bx lr108 %tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %A, <4 x i32> %B)109 ret <4 x i16> %tmp3110}111 112define <2 x i32> @vrsubhni64(<2 x i64> %A, <2 x i64> %B) {113; CHECK-LABEL: vrsubhni64:114; CHECK: @ %bb.0:115; CHECK-NEXT: vrsubhn.i64 d0, q0, q1116; CHECK-NEXT: bx lr117 %tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %A, <2 x i64> %B)118 ret <2 x i32> %tmp3119}120 121declare <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) readnone122declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) readnone123declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) readnone124 125define <8 x i8> @vsubhni16_natural(<8 x i16> %A, <8 x i16> %B) {126; CHECK-LABEL: vsubhni16_natural:127; CHECK: @ %bb.0:128; CHECK-NEXT: vsubhn.i16 d0, q0, q1129; CHECK-NEXT: bx lr130 %sum = sub <8 x i16> %A, %B131 %shift = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>132 %trunc = trunc <8 x i16> %shift to <8 x i8>133 ret <8 x i8> %trunc134}135 136define <4 x i16> @vsubhni32_natural(<4 x i32> %A, <4 x i32> %B) {137; CHECK-LABEL: vsubhni32_natural:138; CHECK: @ %bb.0:139; CHECK-NEXT: vsubhn.i32 d0, q0, q1140; CHECK-NEXT: bx lr141 %sum = sub <4 x i32> %A, %B142 %shift = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>143 %trunc = trunc <4 x i32> %shift to <4 x i16>144 ret <4 x i16> %trunc145}146 147define <2 x i32> @vsubhni64_natural(<2 x i64> %A, <2 x i64> %B) {148; CHECK-LABEL: vsubhni64_natural:149; CHECK: @ %bb.0:150; CHECK-NEXT: vsubhn.i64 d0, q0, q1151; CHECK-NEXT: bx lr152 %sum = sub <2 x i64> %A, %B153 %shift = lshr <2 x i64> %sum, <i64 32, i64 32>154 %trunc = trunc <2 x i64> %shift to <2 x i32>155 ret <2 x i32> %trunc156}157 158define <8 x i16> @vsubls8(<8 x i8> %A, <8 x i8> %B) {159; CHECK-LABEL: vsubls8:160; CHECK: @ %bb.0:161; CHECK-NEXT: vsubl.s8 q0, d0, d1162; CHECK-NEXT: bx lr163 %tmp3 = sext <8 x i8> %A to <8 x i16>164 %tmp4 = sext <8 x i8> %B to <8 x i16>165 %tmp5 = sub <8 x i16> %tmp3, %tmp4166 ret <8 x i16> %tmp5167}168 169define <4 x i32> @vsubls16(<4 x i16> %A, <4 x i16> %B) {170; CHECK-LABEL: vsubls16:171; CHECK: @ %bb.0:172; CHECK-NEXT: vsubl.s16 q0, d0, d1173; CHECK-NEXT: bx lr174 %tmp3 = sext <4 x i16> %A to <4 x i32>175 %tmp4 = sext <4 x i16> %B to <4 x i32>176 %tmp5 = sub <4 x i32> %tmp3, %tmp4177 ret <4 x i32> %tmp5178}179 180define <2 x i64> @vsubls32(<2 x i32> %A, <2 x i32> %B) {181; CHECK-LABEL: vsubls32:182; CHECK: @ %bb.0:183; CHECK-NEXT: vsubl.s32 q0, d0, d1184; CHECK-NEXT: bx lr185 %tmp3 = sext <2 x i32> %A to <2 x i64>186 %tmp4 = sext <2 x i32> %B to <2 x i64>187 %tmp5 = sub <2 x i64> %tmp3, %tmp4188 ret <2 x i64> %tmp5189}190 191define <8 x i16> @vsublu8(<8 x i8> %A, <8 x i8> %B) {192; CHECK-LABEL: vsublu8:193; CHECK: @ %bb.0:194; CHECK-NEXT: vsubl.u8 q0, d0, d1195; CHECK-NEXT: bx lr196 %tmp3 = zext <8 x i8> %A to <8 x i16>197 %tmp4 = zext <8 x i8> %B to <8 x i16>198 %tmp5 = sub <8 x i16> %tmp3, %tmp4199 ret <8 x i16> %tmp5200}201 202define <4 x i32> @vsublu16(<4 x i16> %A, <4 x i16> %B) {203; CHECK-LABEL: vsublu16:204; CHECK: @ %bb.0:205; CHECK-NEXT: vsubl.u16 q0, d0, d1206; CHECK-NEXT: bx lr207 %tmp3 = zext <4 x i16> %A to <4 x i32>208 %tmp4 = zext <4 x i16> %B to <4 x i32>209 %tmp5 = sub <4 x i32> %tmp3, %tmp4210 ret <4 x i32> %tmp5211}212 213define <2 x i64> @vsublu32(<2 x i32> %A, <2 x i32> %B) {214; CHECK-LABEL: vsublu32:215; CHECK: @ %bb.0:216; CHECK-NEXT: vsubl.u32 q0, d0, d1217; CHECK-NEXT: bx lr218 %tmp3 = zext <2 x i32> %A to <2 x i64>219 %tmp4 = zext <2 x i32> %B to <2 x i64>220 %tmp5 = sub <2 x i64> %tmp3, %tmp4221 ret <2 x i64> %tmp5222}223 224define <8 x i16> @vsubla8(<8 x i8> %A, <8 x i8> %B) {225; CHECK-LABEL: vsubla8:226; CHECK: @ %bb.0:227; CHECK-NEXT: vsubl.u8 q0, d0, d1228; CHECK-NEXT: vbic.i16 q0, #0xff00229; CHECK-NEXT: bx lr230 %tmp3 = zext <8 x i8> %A to <8 x i16>231 %tmp4 = zext <8 x i8> %B to <8 x i16>232 %tmp5 = sub <8 x i16> %tmp3, %tmp4233 %and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>234 ret <8 x i16> %and235}236 237define <4 x i32> @vsubla16(<4 x i16> %A, <4 x i16> %B) {238; CHECK-LABEL: vsubla16:239; CHECK: @ %bb.0:240; CHECK-NEXT: vmov.i32 q8, #0xffff241; CHECK-NEXT: vsubl.u16 q9, d0, d1242; CHECK-NEXT: vand q0, q9, q8243; CHECK-NEXT: bx lr244 %tmp3 = zext <4 x i16> %A to <4 x i32>245 %tmp4 = zext <4 x i16> %B to <4 x i32>246 %tmp5 = sub <4 x i32> %tmp3, %tmp4247 %and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535>248 ret <4 x i32> %and249}250 251define <2 x i64> @vsubla32(<2 x i32> %A, <2 x i32> %B) {252; CHECK-LABEL: vsubla32:253; CHECK: @ %bb.0:254; CHECK-NEXT: vmov.i64 q8, #0xffffffff255; CHECK-NEXT: vsubl.u32 q9, d0, d1256; CHECK-NEXT: vand q0, q9, q8257; CHECK-NEXT: bx lr258 %tmp3 = zext <2 x i32> %A to <2 x i64>259 %tmp4 = zext <2 x i32> %B to <2 x i64>260 %tmp5 = sub <2 x i64> %tmp3, %tmp4261 %and = and <2 x i64> %tmp5, <i64 4294967295, i64 4294967295>262 ret <2 x i64> %and263}264 265define <8 x i16> @vsubws8(<8 x i16> %A, <8 x i8> %B) {266; CHECK-LABEL: vsubws8:267; CHECK: @ %bb.0:268; CHECK-NEXT: vsubw.s8 q0, q0, d2269; CHECK-NEXT: bx lr270 %tmp3 = sext <8 x i8> %B to <8 x i16>271 %tmp4 = sub <8 x i16> %A, %tmp3272 ret <8 x i16> %tmp4273}274 275define <4 x i32> @vsubws16(<4 x i32> %A, <4 x i16> %B) {276; CHECK-LABEL: vsubws16:277; CHECK: @ %bb.0:278; CHECK-NEXT: vsubw.s16 q0, q0, d2279; CHECK-NEXT: bx lr280 %tmp3 = sext <4 x i16> %B to <4 x i32>281 %tmp4 = sub <4 x i32> %A, %tmp3282 ret <4 x i32> %tmp4283}284 285define <2 x i64> @vsubws32(<2 x i64> %A, <2 x i32> %B) {286; CHECK-LABEL: vsubws32:287; CHECK: @ %bb.0:288; CHECK-NEXT: vsubw.s32 q0, q0, d2289; CHECK-NEXT: bx lr290 %tmp3 = sext <2 x i32> %B to <2 x i64>291 %tmp4 = sub <2 x i64> %A, %tmp3292 ret <2 x i64> %tmp4293}294 295define <8 x i16> @vsubwu8(<8 x i16> %A, <8 x i8> %B) {296; CHECK-LABEL: vsubwu8:297; CHECK: @ %bb.0:298; CHECK-NEXT: vsubw.u8 q0, q0, d2299; CHECK-NEXT: bx lr300 %tmp3 = zext <8 x i8> %B to <8 x i16>301 %tmp4 = sub <8 x i16> %A, %tmp3302 ret <8 x i16> %tmp4303}304 305define <4 x i32> @vsubwu16(<4 x i32> %A, <4 x i16> %B) {306; CHECK-LABEL: vsubwu16:307; CHECK: @ %bb.0:308; CHECK-NEXT: vsubw.u16 q0, q0, d2309; CHECK-NEXT: bx lr310 %tmp3 = zext <4 x i16> %B to <4 x i32>311 %tmp4 = sub <4 x i32> %A, %tmp3312 ret <4 x i32> %tmp4313}314 315define <2 x i64> @vsubwu32(<2 x i64> %A, <2 x i32> %B) {316; CHECK-LABEL: vsubwu32:317; CHECK: @ %bb.0:318; CHECK-NEXT: vsubw.u32 q0, q0, d2319; CHECK-NEXT: bx lr320 %tmp3 = zext <2 x i32> %B to <2 x i64>321 %tmp4 = sub <2 x i64> %A, %tmp3322 ret <2 x i64> %tmp4323}324 325define <8 x i16> @vsubwa8(<8 x i16> %A, <8 x i8> %B) {326; CHECK-LABEL: vsubwa8:327; CHECK: @ %bb.0:328; CHECK-NEXT: vsubw.u8 q0, q0, d2329; CHECK-NEXT: vbic.i16 q0, #0xff00330; CHECK-NEXT: bx lr331 %tmp3 = zext <8 x i8> %B to <8 x i16>332 %tmp4 = sub <8 x i16> %A, %tmp3333 %and = and <8 x i16> %tmp4, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>334 ret <8 x i16> %and335}336 337define <4 x i32> @vsubwa16(<4 x i32> %A, <4 x i16> %B) {338; CHECK-LABEL: vsubwa16:339; CHECK: @ %bb.0:340; CHECK-NEXT: vmov.i32 q8, #0xffff341; CHECK-NEXT: vsubw.u16 q9, q0, d2342; CHECK-NEXT: vand q0, q9, q8343; CHECK-NEXT: bx lr344 %tmp3 = zext <4 x i16> %B to <4 x i32>345 %tmp4 = sub <4 x i32> %A, %tmp3346 %and = and <4 x i32> %tmp4, <i32 65535, i32 65535, i32 65535, i32 65535>347 ret <4 x i32> %and348}349 350define <2 x i64> @vsubwa32(<2 x i64> %A, <2 x i32> %B) {351; CHECK-LABEL: vsubwa32:352; CHECK: @ %bb.0:353; CHECK-NEXT: vmov.i64 q8, #0xffffffff354; CHECK-NEXT: vsubw.u32 q9, q0, d2355; CHECK-NEXT: vand q0, q9, q8356; CHECK-NEXT: bx lr357 %tmp3 = zext <2 x i32> %B to <2 x i64>358 %tmp4 = sub <2 x i64> %A, %tmp3359 %and = and <2 x i64> %tmp4, <i64 4294967295, i64 4294967295>360 ret <2 x i64> %and361}362