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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s3 4define <8 x i8> @vtrni8(ptr %A, ptr %B) nounwind {5; CHECK-LABEL: vtrni8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vldr d16, [r1]8; CHECK-NEXT: vldr d17, [r0]9; CHECK-NEXT: vtrn.8 d17, d1610; CHECK-NEXT: vadd.i8 d16, d17, d1611; CHECK-NEXT: vmov r0, r1, d1612; CHECK-NEXT: mov pc, lr13 %tmp1 = load <8 x i8>, ptr %A14 %tmp2 = load <8 x i8>, ptr %B15 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>16 %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>17 %tmp5 = add <8 x i8> %tmp3, %tmp418 ret <8 x i8> %tmp519}20 21define <16 x i8> @vtrni8_Qres(ptr %A, ptr %B) nounwind {22; CHECK-LABEL: vtrni8_Qres:23; CHECK: @ %bb.0:24; CHECK-NEXT: vldr d16, [r1]25; CHECK-NEXT: vldr d17, [r0]26; CHECK-NEXT: vtrn.8 d17, d1627; CHECK-NEXT: vmov r0, r1, d1728; CHECK-NEXT: vmov r2, r3, d1629; CHECK-NEXT: mov pc, lr30 %tmp1 = load <8 x i8>, ptr %A31 %tmp2 = load <8 x i8>, ptr %B32 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>33 ret <16 x i8> %tmp334}35 36define <4 x i16> @vtrni16(ptr %A, ptr %B) nounwind {37; CHECK-LABEL: vtrni16:38; CHECK: @ %bb.0:39; CHECK-NEXT: vldr d16, [r1]40; CHECK-NEXT: vldr d17, [r0]41; CHECK-NEXT: vtrn.16 d17, d1642; CHECK-NEXT: vadd.i16 d16, d17, d1643; CHECK-NEXT: vmov r0, r1, d1644; CHECK-NEXT: mov pc, lr45 %tmp1 = load <4 x i16>, ptr %A46 %tmp2 = load <4 x i16>, ptr %B47 %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>48 %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>49 %tmp5 = add <4 x i16> %tmp3, %tmp450 ret <4 x i16> %tmp551}52 53define <8 x i16> @vtrni16_Qres(ptr %A, ptr %B) nounwind {54; CHECK-LABEL: vtrni16_Qres:55; CHECK: @ %bb.0:56; CHECK-NEXT: vldr d16, [r1]57; CHECK-NEXT: vldr d17, [r0]58; CHECK-NEXT: vtrn.16 d17, d1659; CHECK-NEXT: vmov r0, r1, d1760; CHECK-NEXT: vmov r2, r3, d1661; CHECK-NEXT: mov pc, lr62 %tmp1 = load <4 x i16>, ptr %A63 %tmp2 = load <4 x i16>, ptr %B64 %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>65 ret <8 x i16> %tmp366}67 68define <2 x i32> @vtrni32(ptr %A, ptr %B) nounwind {69; CHECK-LABEL: vtrni32:70; CHECK: @ %bb.0:71; CHECK-NEXT: vldr d16, [r1]72; CHECK-NEXT: vldr d17, [r0]73; CHECK-NEXT: vtrn.32 d17, d1674; CHECK-NEXT: vmul.i32 d16, d17, d1675; CHECK-NEXT: vmov r0, r1, d1676; CHECK-NEXT: mov pc, lr77 %tmp1 = load <2 x i32>, ptr %A78 %tmp2 = load <2 x i32>, ptr %B79 %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>80 %tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>81 %tmp5 = mul <2 x i32> %tmp3, %tmp482 ret <2 x i32> %tmp583}84 85define <4 x i32> @vtrni32_Qres(ptr %A, ptr %B) nounwind {86; CHECK-LABEL: vtrni32_Qres:87; CHECK: @ %bb.0:88; CHECK-NEXT: vldr d16, [r1]89; CHECK-NEXT: vldr d17, [r0]90; CHECK-NEXT: vtrn.32 d17, d1691; CHECK-NEXT: vmov r0, r1, d1792; CHECK-NEXT: vmov r2, r3, d1693; CHECK-NEXT: mov pc, lr94 %tmp1 = load <2 x i32>, ptr %A95 %tmp2 = load <2 x i32>, ptr %B96 %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>97 ret <4 x i32> %tmp398}99 100define <2 x float> @vtrnf(ptr %A, ptr %B) nounwind {101; CHECK-LABEL: vtrnf:102; CHECK: @ %bb.0:103; CHECK-NEXT: vldr d16, [r1]104; CHECK-NEXT: vldr d17, [r0]105; CHECK-NEXT: vtrn.32 d17, d16106; CHECK-NEXT: vadd.f32 d16, d17, d16107; CHECK-NEXT: vmov r0, r1, d16108; CHECK-NEXT: mov pc, lr109 %tmp1 = load <2 x float>, ptr %A110 %tmp2 = load <2 x float>, ptr %B111 %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2>112 %tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3>113 %tmp5 = fadd <2 x float> %tmp3, %tmp4114 ret <2 x float> %tmp5115}116 117define <4 x float> @vtrnf_Qres(ptr %A, ptr %B) nounwind {118; CHECK-LABEL: vtrnf_Qres:119; CHECK: @ %bb.0:120; CHECK-NEXT: vldr d16, [r1]121; CHECK-NEXT: vldr d17, [r0]122; CHECK-NEXT: vtrn.32 d17, d16123; CHECK-NEXT: vmov r0, r1, d17124; CHECK-NEXT: vmov r2, r3, d16125; CHECK-NEXT: mov pc, lr126 %tmp1 = load <2 x float>, ptr %A127 %tmp2 = load <2 x float>, ptr %B128 %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>129 ret <4 x float> %tmp3130}131 132define <16 x i8> @vtrnQi8(ptr %A, ptr %B) nounwind {133; CHECK-LABEL: vtrnQi8:134; CHECK: @ %bb.0:135; CHECK-NEXT: vld1.64 {d16, d17}, [r1]136; CHECK-NEXT: vld1.64 {d18, d19}, [r0]137; CHECK-NEXT: vtrn.8 q9, q8138; CHECK-NEXT: vadd.i8 q8, q9, q8139; CHECK-NEXT: vmov r0, r1, d16140; CHECK-NEXT: vmov r2, r3, d17141; CHECK-NEXT: mov pc, lr142 %tmp1 = load <16 x i8>, ptr %A143 %tmp2 = load <16 x i8>, ptr %B144 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>145 %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>146 %tmp5 = add <16 x i8> %tmp3, %tmp4147 ret <16 x i8> %tmp5148}149 150define <32 x i8> @vtrnQi8_QQres(ptr %A, ptr %B) nounwind {151; CHECK-LABEL: vtrnQi8_QQres:152; CHECK: @ %bb.0:153; CHECK-NEXT: vld1.64 {d16, d17}, [r2]154; CHECK-NEXT: vld1.64 {d18, d19}, [r1]155; CHECK-NEXT: vtrn.8 q9, q8156; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!157; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]158; CHECK-NEXT: mov pc, lr159 %tmp1 = load <16 x i8>, ptr %A160 %tmp2 = load <16 x i8>, ptr %B161 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30, i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>162 ret <32 x i8> %tmp3163}164 165define <8 x i16> @vtrnQi16(ptr %A, ptr %B) nounwind {166; CHECK-LABEL: vtrnQi16:167; CHECK: @ %bb.0:168; CHECK-NEXT: vld1.64 {d16, d17}, [r1]169; CHECK-NEXT: vld1.64 {d18, d19}, [r0]170; CHECK-NEXT: vtrn.16 q9, q8171; CHECK-NEXT: vadd.i16 q8, q9, q8172; CHECK-NEXT: vmov r0, r1, d16173; CHECK-NEXT: vmov r2, r3, d17174; CHECK-NEXT: mov pc, lr175 %tmp1 = load <8 x i16>, ptr %A176 %tmp2 = load <8 x i16>, ptr %B177 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>178 %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>179 %tmp5 = add <8 x i16> %tmp3, %tmp4180 ret <8 x i16> %tmp5181}182 183define <16 x i16> @vtrnQi16_QQres(ptr %A, ptr %B) nounwind {184; CHECK-LABEL: vtrnQi16_QQres:185; CHECK: @ %bb.0:186; CHECK-NEXT: vld1.64 {d16, d17}, [r2]187; CHECK-NEXT: vld1.64 {d18, d19}, [r1]188; CHECK-NEXT: vtrn.16 q9, q8189; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!190; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]191; CHECK-NEXT: mov pc, lr192 %tmp1 = load <8 x i16>, ptr %A193 %tmp2 = load <8 x i16>, ptr %B194 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>195 ret <16 x i16> %tmp3196}197 198define <4 x i32> @vtrnQi32(ptr %A, ptr %B) nounwind {199; CHECK-LABEL: vtrnQi32:200; CHECK: @ %bb.0:201; CHECK-NEXT: vld1.64 {d16, d17}, [r1]202; CHECK-NEXT: vld1.64 {d18, d19}, [r0]203; CHECK-NEXT: vtrn.32 q9, q8204; CHECK-NEXT: vadd.i32 q8, q9, q8205; CHECK-NEXT: vmov r0, r1, d16206; CHECK-NEXT: vmov r2, r3, d17207; CHECK-NEXT: mov pc, lr208 %tmp1 = load <4 x i32>, ptr %A209 %tmp2 = load <4 x i32>, ptr %B210 %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>211 %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>212 %tmp5 = add <4 x i32> %tmp3, %tmp4213 ret <4 x i32> %tmp5214}215 216define <8 x i32> @vtrnQi32_QQres(ptr %A, ptr %B) nounwind {217; CHECK-LABEL: vtrnQi32_QQres:218; CHECK: @ %bb.0:219; CHECK-NEXT: vld1.64 {d16, d17}, [r2]220; CHECK-NEXT: vld1.64 {d18, d19}, [r1]221; CHECK-NEXT: vtrn.32 q9, q8222; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!223; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]224; CHECK-NEXT: mov pc, lr225 %tmp1 = load <4 x i32>, ptr %A226 %tmp2 = load <4 x i32>, ptr %B227 %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>228 ret <8 x i32> %tmp3229}230 231define <4 x float> @vtrnQf(ptr %A, ptr %B) nounwind {232; CHECK-LABEL: vtrnQf:233; CHECK: @ %bb.0:234; CHECK-NEXT: vld1.64 {d16, d17}, [r1]235; CHECK-NEXT: vld1.64 {d18, d19}, [r0]236; CHECK-NEXT: vtrn.32 q9, q8237; CHECK-NEXT: vadd.f32 q8, q9, q8238; CHECK-NEXT: vmov r0, r1, d16239; CHECK-NEXT: vmov r2, r3, d17240; CHECK-NEXT: mov pc, lr241 %tmp1 = load <4 x float>, ptr %A242 %tmp2 = load <4 x float>, ptr %B243 %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>244 %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>245 %tmp5 = fadd <4 x float> %tmp3, %tmp4246 ret <4 x float> %tmp5247}248 249define <8 x float> @vtrnQf_QQres(ptr %A, ptr %B) nounwind {250; CHECK-LABEL: vtrnQf_QQres:251; CHECK: @ %bb.0:252; CHECK-NEXT: vld1.64 {d16, d17}, [r2]253; CHECK-NEXT: vld1.64 {d18, d19}, [r1]254; CHECK-NEXT: vtrn.32 q9, q8255; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!256; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]257; CHECK-NEXT: mov pc, lr258 %tmp1 = load <4 x float>, ptr %A259 %tmp2 = load <4 x float>, ptr %B260 %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>261 ret <8 x float> %tmp3262}263 264 265define <8 x i8> @vtrni8_undef(ptr %A, ptr %B) nounwind {266; CHECK-LABEL: vtrni8_undef:267; CHECK: @ %bb.0:268; CHECK-NEXT: vldr d16, [r1]269; CHECK-NEXT: vldr d17, [r0]270; CHECK-NEXT: vtrn.8 d17, d16271; CHECK-NEXT: vadd.i8 d16, d17, d16272; CHECK-NEXT: vmov r0, r1, d16273; CHECK-NEXT: mov pc, lr274 %tmp1 = load <8 x i8>, ptr %A275 %tmp2 = load <8 x i8>, ptr %B276 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14>277 %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>278 %tmp5 = add <8 x i8> %tmp3, %tmp4279 ret <8 x i8> %tmp5280}281 282define <16 x i8> @vtrni8_undef_Qres(ptr %A, ptr %B) nounwind {283; CHECK-LABEL: vtrni8_undef_Qres:284; CHECK: @ %bb.0:285; CHECK-NEXT: vldr d16, [r1]286; CHECK-NEXT: vldr d17, [r0]287; CHECK-NEXT: vtrn.8 d17, d16288; CHECK-NEXT: vmov r0, r1, d17289; CHECK-NEXT: vmov r2, r3, d16290; CHECK-NEXT: mov pc, lr291 %tmp1 = load <8 x i8>, ptr %A292 %tmp2 = load <8 x i8>, ptr %B293 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>294 ret <16 x i8> %tmp3295}296 297define <8 x i16> @vtrnQi16_undef(ptr %A, ptr %B) nounwind {298; CHECK-LABEL: vtrnQi16_undef:299; CHECK: @ %bb.0:300; CHECK-NEXT: vld1.64 {d16, d17}, [r1]301; CHECK-NEXT: vld1.64 {d18, d19}, [r0]302; CHECK-NEXT: vtrn.16 q9, q8303; CHECK-NEXT: vadd.i16 q8, q9, q8304; CHECK-NEXT: vmov r0, r1, d16305; CHECK-NEXT: vmov r2, r3, d17306; CHECK-NEXT: mov pc, lr307 %tmp1 = load <8 x i16>, ptr %A308 %tmp2 = load <8 x i16>, ptr %B309 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14>310 %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>311 %tmp5 = add <8 x i16> %tmp3, %tmp4312 ret <8 x i16> %tmp5313}314 315define <16 x i16> @vtrnQi16_undef_QQres(ptr %A, ptr %B) nounwind {316; CHECK-LABEL: vtrnQi16_undef_QQres:317; CHECK: @ %bb.0:318; CHECK-NEXT: vld1.64 {d16, d17}, [r2]319; CHECK-NEXT: vld1.64 {d18, d19}, [r1]320; CHECK-NEXT: vtrn.16 q9, q8321; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!322; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]323; CHECK-NEXT: mov pc, lr324 %tmp1 = load <8 x i16>, ptr %A325 %tmp2 = load <8 x i16>, ptr %B326 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14, i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>327 ret <16 x i16> %tmp3328}329 330define <8 x i16> @vtrn_lower_shufflemask_undef(ptr %A, ptr %B) {331; CHECK-LABEL: vtrn_lower_shufflemask_undef:332; CHECK: @ %bb.0: @ %entry333; CHECK-NEXT: vldr d16, [r1]334; CHECK-NEXT: vldr d17, [r0]335; CHECK-NEXT: vtrn.16 d17, d16336; CHECK-NEXT: vmov r0, r1, d16337; CHECK-NEXT: vmov r2, r3, d16338; CHECK-NEXT: mov pc, lr339entry:340 %tmp1 = load <4 x i16>, ptr %A341 %tmp2 = load <4 x i16>, ptr %B342 %0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 5, i32 3, i32 7>343 ret <8 x i16> %0344}345 346; Here we get a build_vector node, where all the incoming extract_element347; values do modify the type. However, we get different input types, as some of348; them get truncated from i32 to i8 (from comparing cmp0 with cmp1) and some of349; them get truncated from i16 to i8 (from comparing cmp2 with cmp3).350define <8 x i8> @vtrn_mismatched_builvector0(<8 x i8> %tr0, <8 x i8> %tr1, <4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i16> %cmp2, <4 x i16> %cmp3) {351; CHECK-LABEL: vtrn_mismatched_builvector0:352; CHECK: @ %bb.0:353; CHECK-NEXT: mov r12, sp354; CHECK-NEXT: vld1.64 {d16, d17}, [r12]355; CHECK-NEXT: add r12, sp, #16356; CHECK-NEXT: vld1.64 {d18, d19}, [r12]357; CHECK-NEXT: vcgt.u32 q8, q9, q8358; CHECK-NEXT: vldr d20, [sp, #32]359; CHECK-NEXT: vldr d18, [sp, #40]360; CHECK-NEXT: vcgt.u16 d18, d18, d20361; CHECK-NEXT: vmovn.i32 d16, q8362; CHECK-NEXT: vmov d17, r2, r3363; CHECK-NEXT: vtrn.8 d16, d18364; CHECK-NEXT: vmov d18, r0, r1365; CHECK-NEXT: vshl.i8 d16, d16, #7366; CHECK-NEXT: vshr.s8 d16, d16, #7367; CHECK-NEXT: vbsl d16, d18, d17368; CHECK-NEXT: vmov r0, r1, d16369; CHECK-NEXT: mov pc, lr370 %c0 = icmp ult <4 x i32> %cmp0, %cmp1371 %c1 = icmp ult <4 x i16> %cmp2, %cmp3372 %c = shufflevector <4 x i1> %c0, <4 x i1> %c1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>373 %rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1374 ret <8 x i8> %rv375}376 377; Here we get a build_vector node, where half the incoming extract_element378; values do not modify the type (the values form cmp2), but half of them do379; (from the icmp operation).380; We need to extend the 4 x i8 to 4 x i16 in order to perform the vtrn381define <8 x i8> @vtrn_mismatched_builvector1(<8 x i8> %tr0, <8 x i8> %tr1, <4 x i32> %cmp0, <4 x i32> %cmp1, ptr %cmp2_ptr) {382; CHECK-LABEL: vtrn_mismatched_builvector1:383; CHECK: @ %bb.0:384; CHECK-NEXT: .save {r11, lr}385; CHECK-NEXT: push {r11, lr}386; CHECK-NEXT: add r12, sp, #8387; CHECK-NEXT: add lr, sp, #24388; CHECK-NEXT: vld1.64 {d16, d17}, [r12]389; CHECK-NEXT: ldr r12, [sp, #40]390; CHECK-NEXT: vld1.64 {d18, d19}, [lr]391; CHECK-NEXT: vcgt.u32 q8, q9, q8392; CHECK-NEXT: vld1.32 {d18[0]}, [r12:32]393; CHECK-NEXT: vmovl.u8 q9, d18394; CHECK-NEXT: vmovn.i32 d16, q8395; CHECK-NEXT: vmov d17, r2, r3396; CHECK-NEXT: vtrn.8 d16, d18397; CHECK-NEXT: vmov d18, r0, r1398; CHECK-NEXT: vshl.i8 d16, d16, #7399; CHECK-NEXT: vshr.s8 d16, d16, #7400; CHECK-NEXT: vbsl d16, d18, d17401; CHECK-NEXT: vmov r0, r1, d16402; CHECK-NEXT: pop {r11, lr}403; CHECK-NEXT: mov pc, lr404 %cmp2_load = load <4 x i8>, ptr %cmp2_ptr, align 4405 %cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1>406 %c0 = icmp ult <4 x i32> %cmp0, %cmp1407 %c = shufflevector <4 x i1> %c0, <4 x i1> %cmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>408 %rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1409 ret <8 x i8> %rv410}411 412; The shuffle mask is half a vtrn; we duplicate the half to produce the413; full result.414define void @lower_twice_no_vtrn(ptr %A, ptr %B, ptr %C) {415; CHECK-LABEL: lower_twice_no_vtrn:416; CHECK: @ %bb.0: @ %entry417; CHECK-NEXT: vldr d16, [r1]418; CHECK-NEXT: vldr d18, [r0]419; CHECK-NEXT: vtrn.16 d18, d16420; CHECK-NEXT: vorr d17, d16, d16421; CHECK-NEXT: vst1.64 {d16, d17}, [r2]422; CHECK-NEXT: mov pc, lr423entry:424 %tmp1 = load <4 x i16>, ptr %A425 %tmp2 = load <4 x i16>, ptr %B426 %0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 5, i32 3, i32 7, i32 1, i32 5, i32 3, i32 7>427 store <8 x i16> %0, ptr %C428 ret void429}430 431; The shuffle mask is half a vtrn; we duplicate the half to produce the432; full result.433define void @upper_twice_no_vtrn(ptr %A, ptr %B, ptr %C) {434; CHECK-LABEL: upper_twice_no_vtrn:435; CHECK: @ %bb.0: @ %entry436; CHECK-NEXT: vldr d16, [r1]437; CHECK-NEXT: vldr d18, [r0]438; CHECK-NEXT: vtrn.16 d18, d16439; CHECK-NEXT: vorr d19, d18, d18440; CHECK-NEXT: vst1.64 {d18, d19}, [r2]441; CHECK-NEXT: mov pc, lr442entry:443 %tmp1 = load <4 x i16>, ptr %A444 %tmp2 = load <4 x i16>, ptr %B445 %0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 6, i32 0, i32 4, i32 2, i32 6>446 store <8 x i16> %0, ptr %C447 ret void448}449 450define void @test_15xi16(ptr %next.gep, ptr %next.gep13) {451; CHECK-LABEL: test_15xi16:452; CHECK: @ %bb.0:453; CHECK-NEXT: add r2, r0, #2454; CHECK-NEXT: add r3, r0, #6455; CHECK-NEXT: vld1.16 {d16, d17}, [r2]!456; CHECK-NEXT: vld1.16 {d18}, [r2]!457; CHECK-NEXT: vld1.16 {d20, d21}, [r3]!458; CHECK-NEXT: ldr r2, [r2]459; CHECK-NEXT: vld1.16 {d22}, [r3]!460; CHECK-NEXT: vmov.16 d19[0], r2461; CHECK-NEXT: ldr r3, [r3]462; CHECK-NEXT: add r2, r0, #30463; CHECK-NEXT: add r0, r0, #34464; CHECK-NEXT: vmov.16 d19[1], r3465; CHECK-NEXT: vld1.16 {d19[2]}, [r2:16]466; CHECK-NEXT: vtrn.16 q8, q10467; CHECK-NEXT: vld1.16 {d19[3]}, [r0:16]468; CHECK-NEXT: vtrn.16 d18, d22469; CHECK-NEXT: vst1.16 {d16, d17}, [r1]!470; CHECK-NEXT: vst1.16 {d18, d19}, [r1]471; CHECK-NEXT: mov pc, lr472 %a = getelementptr inbounds nuw i8, ptr %next.gep, i32 2473 %b = load <15 x i16>, ptr %a, align 2474 %c = getelementptr inbounds nuw i8, ptr %next.gep, i32 6475 %d = load <15 x i16>, ptr %c, align 2476 %interleaved.vec = shufflevector <15 x i16> %b, <15 x i16> %d, <16 x i32> <i32 0, i32 15, i32 2, i32 17, i32 4, i32 19, i32 6, i32 21, i32 8, i32 23, i32 10, i32 25, i32 12, i32 27, i32 14, i32 29>477 store <16 x i16> %interleaved.vec, ptr %next.gep13, align 2478 ret void479}480