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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s3 4define <8 x i8> @vuzpi8(ptr %A, ptr %B) nounwind {5; CHECK-LABEL: vuzpi8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vldr d16, [r1]8; CHECK-NEXT: vldr d17, [r0]9; CHECK-NEXT: vuzp.8 d17, d1610; CHECK-NEXT: vmul.i8 d16, d17, d1611; CHECK-NEXT: vmov r0, r1, d1612; CHECK-NEXT: mov pc, lr13 %tmp1 = load <8 x i8>, ptr %A14 %tmp2 = load <8 x i8>, ptr %B15 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>16 %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>17 %tmp5 = mul <8 x i8> %tmp3, %tmp418 ret <8 x i8> %tmp519}20 21define <16 x i8> @vuzpi8_Qres(ptr %A, ptr %B) nounwind {22; CHECK-LABEL: vuzpi8_Qres:23; CHECK: @ %bb.0:24; CHECK-NEXT: vldr d16, [r1]25; CHECK-NEXT: vldr d17, [r0]26; CHECK-NEXT: vuzp.8 d17, d1627; CHECK-NEXT: vmov r0, r1, d1728; CHECK-NEXT: vmov r2, r3, d1629; CHECK-NEXT: mov pc, lr30 %tmp1 = load <8 x i8>, ptr %A31 %tmp2 = load <8 x i8>, ptr %B32 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>33 ret <16 x i8> %tmp334}35 36define <4 x i16> @vuzpi16(ptr %A, ptr %B) nounwind {37; CHECK-LABEL: vuzpi16:38; CHECK: @ %bb.0:39; CHECK-NEXT: vldr d16, [r1]40; CHECK-NEXT: vldr d17, [r0]41; CHECK-NEXT: vuzp.16 d17, d1642; CHECK-NEXT: vmul.i16 d16, d17, d1643; CHECK-NEXT: vmov r0, r1, d1644; CHECK-NEXT: mov pc, lr45 %tmp1 = load <4 x i16>, ptr %A46 %tmp2 = load <4 x i16>, ptr %B47 %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>48 %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>49 %tmp5 = mul <4 x i16> %tmp3, %tmp450 ret <4 x i16> %tmp551}52 53define <8 x i16> @vuzpi16_Qres(ptr %A, ptr %B) nounwind {54; CHECK-LABEL: vuzpi16_Qres:55; CHECK: @ %bb.0:56; CHECK-NEXT: vldr d16, [r1]57; CHECK-NEXT: vldr d17, [r0]58; CHECK-NEXT: vuzp.16 d17, d1659; CHECK-NEXT: vmov r0, r1, d1760; CHECK-NEXT: vmov r2, r3, d1661; CHECK-NEXT: mov pc, lr62 %tmp1 = load <4 x i16>, ptr %A63 %tmp2 = load <4 x i16>, ptr %B64 %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>65 ret <8 x i16> %tmp366}67 68; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.69 70define <16 x i8> @vuzpQi8(ptr %A, ptr %B) nounwind {71; CHECK-LABEL: vuzpQi8:72; CHECK: @ %bb.0:73; CHECK-NEXT: vld1.64 {d16, d17}, [r1]74; CHECK-NEXT: vld1.64 {d18, d19}, [r0]75; CHECK-NEXT: vuzp.8 q9, q876; CHECK-NEXT: vadd.i8 q8, q9, q877; CHECK-NEXT: vmov r0, r1, d1678; CHECK-NEXT: vmov r2, r3, d1779; CHECK-NEXT: mov pc, lr80 %tmp1 = load <16 x i8>, ptr %A81 %tmp2 = load <16 x i8>, ptr %B82 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>83 %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>84 %tmp5 = add <16 x i8> %tmp3, %tmp485 ret <16 x i8> %tmp586}87 88define <32 x i8> @vuzpQi8_QQres(ptr %A, ptr %B) nounwind {89; CHECK-LABEL: vuzpQi8_QQres:90; CHECK: @ %bb.0:91; CHECK-NEXT: vld1.64 {d16, d17}, [r2]92; CHECK-NEXT: vld1.64 {d18, d19}, [r1]93; CHECK-NEXT: vuzp.8 q9, q894; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!95; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]96; CHECK-NEXT: mov pc, lr97 %tmp1 = load <16 x i8>, ptr %A98 %tmp2 = load <16 x i8>, ptr %B99 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>100 ret <32 x i8> %tmp3101}102 103define <8 x i16> @vuzpQi16(ptr %A, ptr %B) nounwind {104; CHECK-LABEL: vuzpQi16:105; CHECK: @ %bb.0:106; CHECK-NEXT: vld1.64 {d16, d17}, [r1]107; CHECK-NEXT: vld1.64 {d18, d19}, [r0]108; CHECK-NEXT: vuzp.16 q9, q8109; CHECK-NEXT: vadd.i16 q8, q9, q8110; CHECK-NEXT: vmov r0, r1, d16111; CHECK-NEXT: vmov r2, r3, d17112; CHECK-NEXT: mov pc, lr113 %tmp1 = load <8 x i16>, ptr %A114 %tmp2 = load <8 x i16>, ptr %B115 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>116 %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>117 %tmp5 = add <8 x i16> %tmp3, %tmp4118 ret <8 x i16> %tmp5119}120 121define <16 x i16> @vuzpQi16_QQres(ptr %A, ptr %B) nounwind {122; CHECK-LABEL: vuzpQi16_QQres:123; CHECK: @ %bb.0:124; CHECK-NEXT: vld1.64 {d16, d17}, [r2]125; CHECK-NEXT: vld1.64 {d18, d19}, [r1]126; CHECK-NEXT: vuzp.16 q9, q8127; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!128; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]129; CHECK-NEXT: mov pc, lr130 %tmp1 = load <8 x i16>, ptr %A131 %tmp2 = load <8 x i16>, ptr %B132 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>133 ret <16 x i16> %tmp3134}135 136define <4 x i32> @vuzpQi32(ptr %A, ptr %B) nounwind {137; CHECK-LABEL: vuzpQi32:138; CHECK: @ %bb.0:139; CHECK-NEXT: vld1.64 {d16, d17}, [r1]140; CHECK-NEXT: vld1.64 {d18, d19}, [r0]141; CHECK-NEXT: vuzp.32 q9, q8142; CHECK-NEXT: vadd.i32 q8, q9, q8143; CHECK-NEXT: vmov r0, r1, d16144; CHECK-NEXT: vmov r2, r3, d17145; CHECK-NEXT: mov pc, lr146 %tmp1 = load <4 x i32>, ptr %A147 %tmp2 = load <4 x i32>, ptr %B148 %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>149 %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>150 %tmp5 = add <4 x i32> %tmp3, %tmp4151 ret <4 x i32> %tmp5152}153 154define <8 x i32> @vuzpQi32_QQres(ptr %A, ptr %B) nounwind {155; CHECK-LABEL: vuzpQi32_QQres:156; CHECK: @ %bb.0:157; CHECK-NEXT: vld1.64 {d16, d17}, [r2]158; CHECK-NEXT: vld1.64 {d18, d19}, [r1]159; CHECK-NEXT: vuzp.32 q9, q8160; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!161; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]162; CHECK-NEXT: mov pc, lr163 %tmp1 = load <4 x i32>, ptr %A164 %tmp2 = load <4 x i32>, ptr %B165 %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>166 ret <8 x i32> %tmp3167}168 169define <4 x float> @vuzpQf(ptr %A, ptr %B) nounwind {170; CHECK-LABEL: vuzpQf:171; CHECK: @ %bb.0:172; CHECK-NEXT: vld1.64 {d16, d17}, [r1]173; CHECK-NEXT: vld1.64 {d18, d19}, [r0]174; CHECK-NEXT: vuzp.32 q9, q8175; CHECK-NEXT: vadd.f32 q8, q9, q8176; CHECK-NEXT: vmov r0, r1, d16177; CHECK-NEXT: vmov r2, r3, d17178; CHECK-NEXT: mov pc, lr179 %tmp1 = load <4 x float>, ptr %A180 %tmp2 = load <4 x float>, ptr %B181 %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>182 %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>183 %tmp5 = fadd <4 x float> %tmp3, %tmp4184 ret <4 x float> %tmp5185}186 187define <8 x float> @vuzpQf_QQres(ptr %A, ptr %B) nounwind {188; CHECK-LABEL: vuzpQf_QQres:189; CHECK: @ %bb.0:190; CHECK-NEXT: vld1.64 {d16, d17}, [r2]191; CHECK-NEXT: vld1.64 {d18, d19}, [r1]192; CHECK-NEXT: vuzp.32 q9, q8193; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!194; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]195; CHECK-NEXT: mov pc, lr196 %tmp1 = load <4 x float>, ptr %A197 %tmp2 = load <4 x float>, ptr %B198 %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>199 ret <8 x float> %tmp3200}201 202; Undef shuffle indices should not prevent matching to VUZP:203 204define <8 x i8> @vuzpi8_undef(ptr %A, ptr %B) nounwind {205; CHECK-LABEL: vuzpi8_undef:206; CHECK: @ %bb.0:207; CHECK-NEXT: vldr d16, [r1]208; CHECK-NEXT: vldr d17, [r0]209; CHECK-NEXT: vuzp.8 d17, d16210; CHECK-NEXT: vmul.i8 d16, d17, d16211; CHECK-NEXT: vmov r0, r1, d16212; CHECK-NEXT: mov pc, lr213 %tmp1 = load <8 x i8>, ptr %A214 %tmp2 = load <8 x i8>, ptr %B215 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14>216 %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15>217 %tmp5 = mul <8 x i8> %tmp3, %tmp4218 ret <8 x i8> %tmp5219}220 221define <16 x i8> @vuzpi8_undef_Qres(ptr %A, ptr %B) nounwind {222; CHECK-LABEL: vuzpi8_undef_Qres:223; CHECK: @ %bb.0:224; CHECK-NEXT: vldr d16, [r1]225; CHECK-NEXT: vldr d17, [r0]226; CHECK-NEXT: vuzp.8 d17, d16227; CHECK-NEXT: vmov r0, r1, d17228; CHECK-NEXT: vmov r2, r3, d16229; CHECK-NEXT: mov pc, lr230 %tmp1 = load <8 x i8>, ptr %A231 %tmp2 = load <8 x i8>, ptr %B232 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15>233 ret <16 x i8> %tmp3234}235 236define <8 x i16> @vuzpQi16_undef(ptr %A, ptr %B) nounwind {237; CHECK-LABEL: vuzpQi16_undef:238; CHECK: @ %bb.0:239; CHECK-NEXT: vld1.64 {d16, d17}, [r1]240; CHECK-NEXT: vld1.64 {d18, d19}, [r0]241; CHECK-NEXT: vuzp.16 q9, q8242; CHECK-NEXT: vadd.i16 q8, q9, q8243; CHECK-NEXT: vmov r0, r1, d16244; CHECK-NEXT: vmov r2, r3, d17245; CHECK-NEXT: mov pc, lr246 %tmp1 = load <8 x i16>, ptr %A247 %tmp2 = load <8 x i16>, ptr %B248 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14>249 %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>250 %tmp5 = add <8 x i16> %tmp3, %tmp4251 ret <8 x i16> %tmp5252}253 254define <16 x i16> @vuzpQi16_undef_QQres(ptr %A, ptr %B) nounwind {255; CHECK-LABEL: vuzpQi16_undef_QQres:256; CHECK: @ %bb.0:257; CHECK-NEXT: vld1.64 {d16, d17}, [r2]258; CHECK-NEXT: vld1.64 {d18, d19}, [r1]259; CHECK-NEXT: vuzp.16 q9, q8260; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!261; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]262; CHECK-NEXT: mov pc, lr263 %tmp1 = load <8 x i16>, ptr %A264 %tmp2 = load <8 x i16>, ptr %B265 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>266 ret <16 x i16> %tmp3267}268 269define <8 x i16> @vuzp_lower_shufflemask_undef(ptr %A, ptr %B) {270; CHECK-LABEL: vuzp_lower_shufflemask_undef:271; CHECK: @ %bb.0: @ %entry272; CHECK-NEXT: vldr d16, [r1]273; CHECK-NEXT: vldr d17, [r0]274; CHECK-NEXT: vuzp.16 d17, d16275; CHECK-NEXT: vmov r0, r1, d16276; CHECK-NEXT: vmov r2, r3, d16277; CHECK-NEXT: mov pc, lr278entry:279 %tmp1 = load <4 x i16>, ptr %A280 %tmp2 = load <4 x i16>, ptr %B281 %0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 3, i32 5, i32 7>282 ret <8 x i16> %0283}284 285define <4 x i32> @vuzp_lower_shufflemask_zeroed(ptr %A, ptr %B) {286; CHECK-LABEL: vuzp_lower_shufflemask_zeroed:287; CHECK: @ %bb.0: @ %entry288; CHECK-NEXT: vldr d17, [r0]289; CHECK-NEXT: vorr d18, d17, d17290; CHECK-NEXT: vldr d16, [r1]291; CHECK-NEXT: vdup.32 d17, d17[0]292; CHECK-NEXT: vtrn.32 d18, d16293; CHECK-NEXT: vmov r0, r1, d17294; CHECK-NEXT: vmov r2, r3, d16295; CHECK-NEXT: mov pc, lr296entry:297 %tmp1 = load <2 x i32>, ptr %A298 %tmp2 = load <2 x i32>, ptr %B299 %0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 0, i32 1, i32 3>300 ret <4 x i32> %0301}302 303define void @vuzp_rev_shufflemask_vtrn(ptr %A, ptr %B, ptr %C) {304; CHECK-LABEL: vuzp_rev_shufflemask_vtrn:305; CHECK: @ %bb.0: @ %entry306; CHECK-NEXT: vldr d16, [r1]307; CHECK-NEXT: vldr d17, [r0]308; CHECK-NEXT: vtrn.32 d17, d16309; CHECK-NEXT: vst1.64 {d16, d17}, [r2]310; CHECK-NEXT: mov pc, lr311entry:312 %tmp1 = load <2 x i32>, ptr %A313 %tmp2 = load <2 x i32>, ptr %B314 %0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 0, i32 2>315 store <4 x i32> %0, ptr %C316 ret void317}318 319define <8 x i8> @cmpsel_trunc(<8 x i8> %in0, <8 x i8> %in1, <8 x i32> %cmp0, <8 x i32> %cmp1) {320; In order to create the select we need to truncate the vcgt result from a vector of i32 to a vector of i8.321; This results in a build_vector with mismatched types. We will generate two vmovn.i32 instructions to322; truncate from i32 to i16 and one vmovn.i16 to perform the final truncation for i8.323; CHECK-LABEL: cmpsel_trunc:324; CHECK: @ %bb.0:325; CHECK-NEXT: add r12, sp, #16326; CHECK-NEXT: vld1.64 {d16, d17}, [r12]327; CHECK-NEXT: mov r12, sp328; CHECK-NEXT: vld1.64 {d18, d19}, [r12]329; CHECK-NEXT: add r12, sp, #48330; CHECK-NEXT: vld1.64 {d20, d21}, [r12]331; CHECK-NEXT: add r12, sp, #32332; CHECK-NEXT: vcgt.u32 q8, q10, q8333; CHECK-NEXT: vld1.64 {d20, d21}, [r12]334; CHECK-NEXT: vcgt.u32 q9, q10, q9335; CHECK-NEXT: vmov d20, r2, r3336; CHECK-NEXT: vmovn.i32 d17, q8337; CHECK-NEXT: vmovn.i32 d16, q9338; CHECK-NEXT: vmov d18, r0, r1339; CHECK-NEXT: vmovn.i16 d16, q8340; CHECK-NEXT: vbsl d16, d18, d20341; CHECK-NEXT: vmov r0, r1, d16342; CHECK-NEXT: mov pc, lr343 %c = icmp ult <8 x i32> %cmp0, %cmp1344 %res = select <8 x i1> %c, <8 x i8> %in0, <8 x i8> %in1345 ret <8 x i8> %res346}347 348; Shuffle the result from the compare with a <4 x i8>.349; We need to extend the loaded <4 x i8> to <4 x i16>. Otherwise we wouldn't be able350; to perform the vuzp and get the vbsl mask.351define <8 x i8> @vuzp_trunc_and_shuffle(<8 x i8> %tr0, <8 x i8> %tr1,352; CHECK-LABEL: vuzp_trunc_and_shuffle:353; CHECK: @ %bb.0:354; CHECK-NEXT: .save {r11, lr}355; CHECK-NEXT: push {r11, lr}356; CHECK-NEXT: add r12, sp, #8357; CHECK-NEXT: add lr, sp, #24358; CHECK-NEXT: vld1.64 {d16, d17}, [r12]359; CHECK-NEXT: ldr r12, [sp, #40]360; CHECK-NEXT: vld1.64 {d18, d19}, [lr]361; CHECK-NEXT: vcgt.u32 q8, q9, q8362; CHECK-NEXT: vld1.32 {d18[0]}, [r12:32]363; CHECK-NEXT: vmovl.u8 q9, d18364; CHECK-NEXT: vmovn.i32 d16, q8365; CHECK-NEXT: vmov d17, r2, r3366; CHECK-NEXT: vuzp.8 d16, d18367; CHECK-NEXT: vmov d18, r0, r1368; CHECK-NEXT: vshl.i8 d16, d16, #7369; CHECK-NEXT: vshr.s8 d16, d16, #7370; CHECK-NEXT: vbsl d16, d18, d17371; CHECK-NEXT: vmov r0, r1, d16372; CHECK-NEXT: pop {r11, lr}373; CHECK-NEXT: mov pc, lr374 <4 x i32> %cmp0, <4 x i32> %cmp1, ptr %cmp2_ptr) {375 %cmp2_load = load <4 x i8>, ptr %cmp2_ptr, align 4376 %cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1>377 %c0 = icmp ult <4 x i32> %cmp0, %cmp1378 %c = shufflevector <4 x i1> %c0, <4 x i1> %cmp2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>379 %rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1380 ret <8 x i8> %rv381}382 383; Use an undef value for the <4 x i8> that is being shuffled with the compare result.384; This produces a build_vector with some of the operands undefs.385define <8 x i8> @vuzp_trunc_and_shuffle_undef_right(<8 x i8> %tr0, <8 x i8> %tr1,386; CHECK-LABEL: vuzp_trunc_and_shuffle_undef_right:387; CHECK: @ %bb.0:388; CHECK-NEXT: mov r12, sp389; CHECK-NEXT: vld1.64 {d16, d17}, [r12]390; CHECK-NEXT: add r12, sp, #16391; CHECK-NEXT: vld1.64 {d18, d19}, [r12]392; CHECK-NEXT: vcgt.u32 q8, q9, q8393; CHECK-NEXT: vmov d18, r0, r1394; CHECK-NEXT: vmovn.i32 d16, q8395; CHECK-NEXT: vuzp.8 d16, d17396; CHECK-NEXT: vmov d17, r2, r3397; CHECK-NEXT: vshl.i8 d16, d16, #7398; CHECK-NEXT: vshr.s8 d16, d16, #7399; CHECK-NEXT: vbsl d16, d18, d17400; CHECK-NEXT: vmov r0, r1, d16401; CHECK-NEXT: mov pc, lr402 <4 x i32> %cmp0, <4 x i32> %cmp1, ptr %cmp2_ptr) {403 %cmp2_load = load <4 x i8>, ptr %cmp2_ptr, align 4404 %cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1>405 %c0 = icmp ult <4 x i32> %cmp0, %cmp1406 %c = shufflevector <4 x i1> %c0, <4 x i1> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>407 %rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1408 ret <8 x i8> %rv409}410 411define <8 x i8> @vuzp_trunc_and_shuffle_undef_left(<8 x i8> %tr0, <8 x i8> %tr1,412; CHECK-LABEL: vuzp_trunc_and_shuffle_undef_left:413; CHECK: @ %bb.0:414; CHECK-NEXT: mov r12, sp415; CHECK-NEXT: vld1.64 {d16, d17}, [r12]416; CHECK-NEXT: add r12, sp, #16417; CHECK-NEXT: vld1.64 {d18, d19}, [r12]418; CHECK-NEXT: vcgt.u32 q8, q9, q8419; CHECK-NEXT: vldr d18, .LCPI22_0420; CHECK-NEXT: vmovn.i32 d16, q8421; CHECK-NEXT: vtbl.8 d16, {d16}, d18422; CHECK-NEXT: vmov d17, r2, r3423; CHECK-NEXT: vmov d18, r0, r1424; CHECK-NEXT: vshl.i8 d16, d16, #7425; CHECK-NEXT: vshr.s8 d16, d16, #7426; CHECK-NEXT: vbsl d16, d18, d17427; CHECK-NEXT: vmov r0, r1, d16428; CHECK-NEXT: mov pc, lr429; CHECK-NEXT: .p2align 3430; CHECK-NEXT: @ %bb.1:431; CHECK-NEXT: .LCPI22_0:432; CHECK-NEXT: .byte 255 @ 0xff433; CHECK-NEXT: .byte 255 @ 0xff434; CHECK-NEXT: .byte 255 @ 0xff435; CHECK-NEXT: .byte 255 @ 0xff436; CHECK-NEXT: .byte 0 @ 0x0437; CHECK-NEXT: .byte 2 @ 0x2438; CHECK-NEXT: .byte 4 @ 0x4439; CHECK-NEXT: .byte 6 @ 0x6440 <4 x i32> %cmp0, <4 x i32> %cmp1, ptr %cmp2_ptr) {441 %cmp2_load = load <4 x i8>, ptr %cmp2_ptr, align 4442 %cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1>443 %c0 = icmp ult <4 x i32> %cmp0, %cmp1444 %c = shufflevector <4 x i1> undef, <4 x i1> %c0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>445 %rv = select <8 x i1> %c, <8 x i8> %tr0, <8 x i8> %tr1446 ret <8 x i8> %rv447}448 449; We're using large data types here, and we have to fill with undef values until we450; get some vector size that we can represent.451define <10 x i8> @vuzp_wide_type(<10 x i8> %tr0, <10 x i8> %tr1,452; CHECK-LABEL: vuzp_wide_type:453; CHECK: @ %bb.0:454; CHECK-NEXT: .save {r4, lr}455; CHECK-NEXT: push {r4, lr}456; CHECK-NEXT: add r12, sp, #32457; CHECK-NEXT: add lr, sp, #48458; CHECK-NEXT: vld1.32 {d17[0]}, [r12:32]459; CHECK-NEXT: add r12, sp, #24460; CHECK-NEXT: vld1.32 {d16[0]}, [r12:32]461; CHECK-NEXT: add r12, sp, #56462; CHECK-NEXT: vld1.32 {d19[0]}, [r12:32]463; CHECK-NEXT: vld1.32 {d18[0]}, [lr:32]464; CHECK-NEXT: add lr, sp, #40465; CHECK-NEXT: vld1.32 {d20[0]}, [lr:32]466; CHECK-NEXT: ldr r12, [sp, #68]467; CHECK-NEXT: ldr r4, [r12]468; CHECK-NEXT: vmov.32 d23[0], r4469; CHECK-NEXT: add r4, sp, #64470; CHECK-NEXT: vld1.32 {d24[0]}, [r4:32]471; CHECK-NEXT: add r4, sp, #36472; CHECK-NEXT: vcgt.u32 q10, q12, q10473; CHECK-NEXT: vld1.32 {d17[1]}, [r4:32]474; CHECK-NEXT: add r4, sp, #28475; CHECK-NEXT: vld1.32 {d16[1]}, [r4:32]476; CHECK-NEXT: add r4, sp, #60477; CHECK-NEXT: vld1.32 {d19[1]}, [r4:32]478; CHECK-NEXT: add r4, sp, #52479; CHECK-NEXT: vld1.32 {d18[1]}, [r4:32]480; CHECK-NEXT: add r4, r12, #4481; CHECK-NEXT: vcgt.u32 q8, q9, q8482; CHECK-NEXT: vmovn.i32 d19, q10483; CHECK-NEXT: vmov.u8 lr, d23[3]484; CHECK-NEXT: vmovn.i32 d18, q8485; CHECK-NEXT: vmovn.i16 d22, q9486; CHECK-NEXT: vldr d18, .LCPI23_0487; CHECK-NEXT: vmov.8 d17[0], lr488; CHECK-NEXT: vtbl.8 d16, {d22, d23}, d18489; CHECK-NEXT: vmov d19, r2, r3490; CHECK-NEXT: vld1.8 {d17[1]}, [r4]491; CHECK-NEXT: add r4, sp, #8492; CHECK-NEXT: vmov d18, r0, r1493; CHECK-NEXT: vshl.i8 q8, q8, #7494; CHECK-NEXT: vld1.64 {d20, d21}, [r4]495; CHECK-NEXT: vshr.s8 q8, q8, #7496; CHECK-NEXT: vbsl q8, q9, q10497; CHECK-NEXT: vmov r0, r1, d16498; CHECK-NEXT: vmov r2, r3, d17499; CHECK-NEXT: pop {r4, lr}500; CHECK-NEXT: mov pc, lr501; CHECK-NEXT: .p2align 3502; CHECK-NEXT: @ %bb.1:503; CHECK-NEXT: .LCPI23_0:504; CHECK-NEXT: .byte 0 @ 0x0505; CHECK-NEXT: .byte 1 @ 0x1506; CHECK-NEXT: .byte 2 @ 0x2507; CHECK-NEXT: .byte 3 @ 0x3508; CHECK-NEXT: .byte 4 @ 0x4509; CHECK-NEXT: .byte 8 @ 0x8510; CHECK-NEXT: .byte 9 @ 0x9511; CHECK-NEXT: .byte 10 @ 0xa512 <5 x i32> %cmp0, <5 x i32> %cmp1, ptr %cmp2_ptr) {513 %cmp2_load = load <5 x i8>, ptr %cmp2_ptr, align 4514 %cmp2 = trunc <5 x i8> %cmp2_load to <5 x i1>515 %c0 = icmp ult <5 x i32> %cmp0, %cmp1516 %c = shufflevector <5 x i1> %c0, <5 x i1> %cmp2, <10 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>517 %rv = select <10 x i1> %c, <10 x i8> %tr0, <10 x i8> %tr1518 ret <10 x i8> %rv519}520 521%struct.uint8x8x2_t = type { [2 x <8 x i8>] }522define %struct.uint8x8x2_t @vuzp_extract_subvector(<16 x i8> %t) #0 {523; CHECK-LABEL: vuzp_extract_subvector:524; CHECK: @ %bb.0:525; CHECK-NEXT: vmov d16, r2, r3526; CHECK-NEXT: vmov d17, r0, r1527; CHECK-NEXT: vuzp.8 d17, d16528; CHECK-NEXT: vmov r0, r1, d17529; CHECK-NEXT: vmov r2, r3, d16530; CHECK-NEXT: mov pc, lr531 532 %vuzp.i = shufflevector <16 x i8> %t, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>533 %vuzp1.i = shufflevector <16 x i8> %t, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>534 %.fca.0.0.insert = insertvalue %struct.uint8x8x2_t undef, <8 x i8> %vuzp.i, 0, 0535 %.fca.0.1.insert = insertvalue %struct.uint8x8x2_t %.fca.0.0.insert, <8 x i8> %vuzp1.i, 0, 1536 ret %struct.uint8x8x2_t %.fca.0.1.insert537}538 539define void @test_15xi16(ptr %next.gep, ptr %next.gep13) {540; CHECK-LABEL: test_15xi16:541; CHECK: @ %bb.0:542; CHECK-NEXT: .save {r4, r5, r6, lr}543; CHECK-NEXT: push {r4, r5, r6, lr}544; CHECK-NEXT: add r2, r0, #2545; CHECK-NEXT: add r3, r0, #6546; CHECK-NEXT: vld1.16 {d20, d21}, [r2]!547; CHECK-NEXT: vld1.16 {d16}, [r2]!548; CHECK-NEXT: vmov.u16 r12, d16[0]549; CHECK-NEXT: ldr r2, [r2]550; CHECK-NEXT: vmov.u16 r4, d20[0]551; CHECK-NEXT: vld1.16 {d22, d23}, [r3]!552; CHECK-NEXT: vld1.16 {d24}, [r3]!553; CHECK-NEXT: vmov.u16 lr, d16[2]554; CHECK-NEXT: vmov.u16 r5, d22[0]555; CHECK-NEXT: vmov.u16 r6, d21[0]556; CHECK-NEXT: vmov.16 d17[0], r12557; CHECK-NEXT: vmov.16 d16[0], r4558; CHECK-NEXT: vmov.u16 r4, d24[0]559; CHECK-NEXT: vmov.u16 r12, d24[2]560; CHECK-NEXT: vmov.16 d17[1], lr561; CHECK-NEXT: vmov.16 d18[0], r5562; CHECK-NEXT: vmov.u16 r5, d20[2]563; CHECK-NEXT: vmov.u16 lr, d23[0]564; CHECK-NEXT: vmov.16 d19[0], r4565; CHECK-NEXT: vmov.u16 r4, d22[2]566; CHECK-NEXT: vmov.16 d16[1], r5567; CHECK-NEXT: vmov.u16 r5, d21[2]568; CHECK-NEXT: vmov.16 d17[2], r2569; CHECK-NEXT: ldr r2, [r3]570; CHECK-NEXT: vmov.16 d16[2], r6571; CHECK-NEXT: vmov.16 d18[1], r4572; CHECK-NEXT: vmov.u16 r4, d23[2]573; CHECK-NEXT: vmov.16 d19[1], r12574; CHECK-NEXT: vmov.16 d18[2], lr575; CHECK-NEXT: vmov.16 d19[2], r2576; CHECK-NEXT: add r2, r0, #30577; CHECK-NEXT: add r0, r0, #34578; CHECK-NEXT: vld1.16 {d17[3]}, [r2:16]579; CHECK-NEXT: vmov.16 d16[3], r5580; CHECK-NEXT: vmov.16 d18[3], r4581; CHECK-NEXT: vld1.16 {d19[3]}, [r0:16]582; CHECK-NEXT: vst1.16 {d16, d17}, [r1]!583; CHECK-NEXT: vst1.16 {d18, d19}, [r1]584; CHECK-NEXT: pop {r4, r5, r6, lr}585; CHECK-NEXT: mov pc, lr586 %a = getelementptr inbounds nuw i8, ptr %next.gep, i32 2587 %b = load <15 x i16>, ptr %a, align 2588 %c = getelementptr inbounds nuw i8, ptr %next.gep, i32 6589 %d = load <15 x i16>, ptr %c, align 2590 %interleaved.vec = shufflevector <15 x i16> %b, <15 x i16> %d, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29>591 store <16 x i16> %interleaved.vec, ptr %next.gep13, align 2592 ret void593}594