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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s3 4define <8 x i8> @vzipi8(ptr %A, ptr %B) nounwind {5; CHECK-LABEL: vzipi8:6; CHECK: @ %bb.0:7; CHECK-NEXT: vldr d16, [r1]8; CHECK-NEXT: vldr d17, [r0]9; CHECK-NEXT: vzip.8 d17, d1610; CHECK-NEXT: vadd.i8 d16, d17, d1611; CHECK-NEXT: vmov r0, r1, d1612; CHECK-NEXT: mov pc, lr13 %tmp1 = load <8 x i8>, ptr %A14 %tmp2 = load <8 x i8>, ptr %B15 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>16 %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>17 %tmp5 = add <8 x i8> %tmp3, %tmp418 ret <8 x i8> %tmp519}20 21define <16 x i8> @vzipi8_Qres(ptr %A, ptr %B) nounwind {22; CHECK-LABEL: vzipi8_Qres:23; CHECK: @ %bb.0:24; CHECK-NEXT: vldr d16, [r1]25; CHECK-NEXT: vldr d17, [r0]26; CHECK-NEXT: vzip.8 d17, d1627; CHECK-NEXT: vmov r0, r1, d1728; CHECK-NEXT: vmov r2, r3, d1629; CHECK-NEXT: mov pc, lr30 %tmp1 = load <8 x i8>, ptr %A31 %tmp2 = load <8 x i8>, ptr %B32 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>33 ret <16 x i8> %tmp334}35 36define <4 x i16> @vzipi16(ptr %A, ptr %B) nounwind {37; CHECK-LABEL: vzipi16:38; CHECK: @ %bb.0:39; CHECK-NEXT: vldr d16, [r1]40; CHECK-NEXT: vldr d17, [r0]41; CHECK-NEXT: vzip.16 d17, d1642; CHECK-NEXT: vadd.i16 d16, d17, d1643; CHECK-NEXT: vmov r0, r1, d1644; CHECK-NEXT: mov pc, lr45 %tmp1 = load <4 x i16>, ptr %A46 %tmp2 = load <4 x i16>, ptr %B47 %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>48 %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>49 %tmp5 = add <4 x i16> %tmp3, %tmp450 ret <4 x i16> %tmp551}52 53define <8 x i16> @vzipi16_Qres(ptr %A, ptr %B) nounwind {54; CHECK-LABEL: vzipi16_Qres:55; CHECK: @ %bb.0:56; CHECK-NEXT: vldr d16, [r1]57; CHECK-NEXT: vldr d17, [r0]58; CHECK-NEXT: vzip.16 d17, d1659; CHECK-NEXT: vmov r0, r1, d1760; CHECK-NEXT: vmov r2, r3, d1661; CHECK-NEXT: mov pc, lr62 %tmp1 = load <4 x i16>, ptr %A63 %tmp2 = load <4 x i16>, ptr %B64 %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>65 ret <8 x i16> %tmp366}67 68; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.69 70define <16 x i8> @vzipQi8(ptr %A, ptr %B) nounwind {71; CHECK-LABEL: vzipQi8:72; CHECK: @ %bb.0:73; CHECK-NEXT: vld1.64 {d16, d17}, [r1]74; CHECK-NEXT: vld1.64 {d18, d19}, [r0]75; CHECK-NEXT: vzip.8 q9, q876; CHECK-NEXT: vadd.i8 q8, q9, q877; CHECK-NEXT: vmov r0, r1, d1678; CHECK-NEXT: vmov r2, r3, d1779; CHECK-NEXT: mov pc, lr80 %tmp1 = load <16 x i8>, ptr %A81 %tmp2 = load <16 x i8>, ptr %B82 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>83 %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>84 %tmp5 = add <16 x i8> %tmp3, %tmp485 ret <16 x i8> %tmp586}87 88define <32 x i8> @vzipQi8_QQres(ptr %A, ptr %B) nounwind {89; CHECK-LABEL: vzipQi8_QQres:90; CHECK: @ %bb.0:91; CHECK-NEXT: vld1.64 {d16, d17}, [r2]92; CHECK-NEXT: vld1.64 {d18, d19}, [r1]93; CHECK-NEXT: vzip.8 q9, q894; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!95; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]96; CHECK-NEXT: mov pc, lr97 %tmp1 = load <16 x i8>, ptr %A98 %tmp2 = load <16 x i8>, ptr %B99 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>100 ret <32 x i8> %tmp3101}102 103define <8 x i16> @vzipQi16(ptr %A, ptr %B) nounwind {104; CHECK-LABEL: vzipQi16:105; CHECK: @ %bb.0:106; CHECK-NEXT: vld1.64 {d16, d17}, [r1]107; CHECK-NEXT: vld1.64 {d18, d19}, [r0]108; CHECK-NEXT: vzip.16 q9, q8109; CHECK-NEXT: vadd.i16 q8, q9, q8110; CHECK-NEXT: vmov r0, r1, d16111; CHECK-NEXT: vmov r2, r3, d17112; CHECK-NEXT: mov pc, lr113 %tmp1 = load <8 x i16>, ptr %A114 %tmp2 = load <8 x i16>, ptr %B115 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>116 %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>117 %tmp5 = add <8 x i16> %tmp3, %tmp4118 ret <8 x i16> %tmp5119}120 121define <16 x i16> @vzipQi16_QQres(ptr %A, ptr %B) nounwind {122; CHECK-LABEL: vzipQi16_QQres:123; CHECK: @ %bb.0:124; CHECK-NEXT: vld1.64 {d16, d17}, [r2]125; CHECK-NEXT: vld1.64 {d18, d19}, [r1]126; CHECK-NEXT: vzip.16 q9, q8127; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!128; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]129; CHECK-NEXT: mov pc, lr130 %tmp1 = load <8 x i16>, ptr %A131 %tmp2 = load <8 x i16>, ptr %B132 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>133 ret <16 x i16> %tmp3134}135 136define <4 x i32> @vzipQi32(ptr %A, ptr %B) nounwind {137; CHECK-LABEL: vzipQi32:138; CHECK: @ %bb.0:139; CHECK-NEXT: vld1.64 {d16, d17}, [r1]140; CHECK-NEXT: vld1.64 {d18, d19}, [r0]141; CHECK-NEXT: vzip.32 q9, q8142; CHECK-NEXT: vadd.i32 q8, q9, q8143; CHECK-NEXT: vmov r0, r1, d16144; CHECK-NEXT: vmov r2, r3, d17145; CHECK-NEXT: mov pc, lr146 %tmp1 = load <4 x i32>, ptr %A147 %tmp2 = load <4 x i32>, ptr %B148 %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>149 %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>150 %tmp5 = add <4 x i32> %tmp3, %tmp4151 ret <4 x i32> %tmp5152}153 154define <8 x i32> @vzipQi32_QQres(ptr %A, ptr %B) nounwind {155; CHECK-LABEL: vzipQi32_QQres:156; CHECK: @ %bb.0:157; CHECK-NEXT: vld1.64 {d16, d17}, [r2]158; CHECK-NEXT: vld1.64 {d18, d19}, [r1]159; CHECK-NEXT: vzip.32 q9, q8160; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!161; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]162; CHECK-NEXT: mov pc, lr163 %tmp1 = load <4 x i32>, ptr %A164 %tmp2 = load <4 x i32>, ptr %B165 %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>166 ret <8 x i32> %tmp3167}168 169define <4 x float> @vzipQf(ptr %A, ptr %B) nounwind {170; CHECK-LABEL: vzipQf:171; CHECK: @ %bb.0:172; CHECK-NEXT: vld1.64 {d16, d17}, [r1]173; CHECK-NEXT: vld1.64 {d18, d19}, [r0]174; CHECK-NEXT: vzip.32 q9, q8175; CHECK-NEXT: vadd.f32 q8, q9, q8176; CHECK-NEXT: vmov r0, r1, d16177; CHECK-NEXT: vmov r2, r3, d17178; CHECK-NEXT: mov pc, lr179 %tmp1 = load <4 x float>, ptr %A180 %tmp2 = load <4 x float>, ptr %B181 %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>182 %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>183 %tmp5 = fadd <4 x float> %tmp3, %tmp4184 ret <4 x float> %tmp5185}186 187define <8 x float> @vzipQf_QQres(ptr %A, ptr %B) nounwind {188; CHECK-LABEL: vzipQf_QQres:189; CHECK: @ %bb.0:190; CHECK-NEXT: vld1.64 {d16, d17}, [r2]191; CHECK-NEXT: vld1.64 {d18, d19}, [r1]192; CHECK-NEXT: vzip.32 q9, q8193; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!194; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]195; CHECK-NEXT: mov pc, lr196 %tmp1 = load <4 x float>, ptr %A197 %tmp2 = load <4 x float>, ptr %B198 %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>199 ret <8 x float> %tmp3200}201 202; Undef shuffle indices should not prevent matching to VZIP:203 204define <8 x i8> @vzipi8_undef(ptr %A, ptr %B) nounwind {205; CHECK-LABEL: vzipi8_undef:206; CHECK: @ %bb.0:207; CHECK-NEXT: vldr d16, [r1]208; CHECK-NEXT: vldr d17, [r0]209; CHECK-NEXT: vzip.8 d17, d16210; CHECK-NEXT: vadd.i8 d16, d17, d16211; CHECK-NEXT: vmov r0, r1, d16212; CHECK-NEXT: mov pc, lr213 %tmp1 = load <8 x i8>, ptr %A214 %tmp2 = load <8 x i8>, ptr %B215 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11>216 %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15>217 %tmp5 = add <8 x i8> %tmp3, %tmp4218 ret <8 x i8> %tmp5219}220 221define <16 x i8> @vzipi8_undef_Qres(ptr %A, ptr %B) nounwind {222; CHECK-LABEL: vzipi8_undef_Qres:223; CHECK: @ %bb.0:224; CHECK-NEXT: vldr d16, [r1]225; CHECK-NEXT: vldr d17, [r0]226; CHECK-NEXT: vzip.8 d17, d16227; CHECK-NEXT: vmov r0, r1, d17228; CHECK-NEXT: vmov r2, r3, d16229; CHECK-NEXT: mov pc, lr230 %tmp1 = load <8 x i8>, ptr %A231 %tmp2 = load <8 x i8>, ptr %B232 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15>233 ret <16 x i8> %tmp3234}235 236define <16 x i8> @vzipQi8_undef(ptr %A, ptr %B) nounwind {237; CHECK-LABEL: vzipQi8_undef:238; CHECK: @ %bb.0:239; CHECK-NEXT: vld1.64 {d16, d17}, [r1]240; CHECK-NEXT: vld1.64 {d18, d19}, [r0]241; CHECK-NEXT: vzip.8 q9, q8242; CHECK-NEXT: vadd.i8 q8, q9, q8243; CHECK-NEXT: vmov r0, r1, d16244; CHECK-NEXT: vmov r2, r3, d17245; CHECK-NEXT: mov pc, lr246 %tmp1 = load <16 x i8>, ptr %A247 %tmp2 = load <16 x i8>, ptr %B248 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>249 %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31>250 %tmp5 = add <16 x i8> %tmp3, %tmp4251 ret <16 x i8> %tmp5252}253 254define <32 x i8> @vzipQi8_undef_QQres(ptr %A, ptr %B) nounwind {255; CHECK-LABEL: vzipQi8_undef_QQres:256; CHECK: @ %bb.0:257; CHECK-NEXT: vld1.64 {d16, d17}, [r2]258; CHECK-NEXT: vld1.64 {d18, d19}, [r1]259; CHECK-NEXT: vzip.8 q9, q8260; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!261; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]262; CHECK-NEXT: mov pc, lr263 %tmp1 = load <16 x i8>, ptr %A264 %tmp2 = load <16 x i8>, ptr %B265 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31>266 ret <32 x i8> %tmp3267}268 269define <8 x i16> @vzip_lower_shufflemask_undef(ptr %A, ptr %B) {270; CHECK-LABEL: vzip_lower_shufflemask_undef:271; CHECK: @ %bb.0: @ %entry272; CHECK-NEXT: vldr d16, [r1]273; CHECK-NEXT: vldr d17, [r0]274; CHECK-NEXT: vzip.16 d17, d16275; CHECK-NEXT: vmov r0, r1, d16276; CHECK-NEXT: vmov r2, r3, d16277; CHECK-NEXT: mov pc, lr278entry:279 %tmp1 = load <4 x i16>, ptr %A280 %tmp2 = load <4 x i16>, ptr %B281 %0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 6, i32 3, i32 7>282 ret <8 x i16> %0283}284 285; NOTE: The mask here looks like something that could be done with a vzip,286; but which the current handling of two-result vzip can't do - thus ending up287; as a vtrn.288define <8 x i16> @vzip_lower_shufflemask_undef_rev(ptr %A, ptr %B) {289; CHECK-LABEL: vzip_lower_shufflemask_undef_rev:290; CHECK: @ %bb.0: @ %entry291; CHECK-NEXT: vldr d16, [r1]292; CHECK-NEXT: vldr d17, [r0]293; CHECK-NEXT: vtrn.16 d17, d16294; CHECK-NEXT: vmov r0, r1, d16295; CHECK-NEXT: vmov r2, r3, d17296; CHECK-NEXT: mov pc, lr297entry:298 %tmp1 = load <4 x i16>, ptr %A299 %tmp2 = load <4 x i16>, ptr %B300 %0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 4, i32 undef, i32 undef>301 ret <8 x i16> %0302}303 304define <4 x i32> @vzip_lower_shufflemask_zeroed(ptr %A) {305; CHECK-LABEL: vzip_lower_shufflemask_zeroed:306; CHECK: @ %bb.0: @ %entry307; CHECK-NEXT: vldr d16, [r0]308; CHECK-NEXT: vdup.32 q9, d16[0]309; CHECK-NEXT: vzip.32 q8, q9310; CHECK-NEXT: vmov r0, r1, d16311; CHECK-NEXT: vmov r2, r3, d17312; CHECK-NEXT: mov pc, lr313entry:314 %tmp1 = load <2 x i32>, ptr %A315 %0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp1, <4 x i32> <i32 0, i32 0, i32 1, i32 0>316 ret <4 x i32> %0317}318 319define <4 x i32> @vzip_lower_shufflemask_vuzp(ptr %A) {320; CHECK-LABEL: vzip_lower_shufflemask_vuzp:321; CHECK: @ %bb.0: @ %entry322; CHECK-NEXT: vldr d16, [r0]323; CHECK-NEXT: vdup.32 q9, d16[0]324; CHECK-NEXT: vzip.32 q8, q9325; CHECK-NEXT: vmov r0, r1, d16326; CHECK-NEXT: vmov r2, r3, d17327; CHECK-NEXT: mov pc, lr328entry:329 %tmp1 = load <2 x i32>, ptr %A330 %0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp1, <4 x i32> <i32 0, i32 2, i32 1, i32 0>331 ret <4 x i32> %0332}333 334define void @vzip_undef_rev_shufflemask_vtrn(ptr %A, ptr %B) {335; CHECK-LABEL: vzip_undef_rev_shufflemask_vtrn:336; CHECK: @ %bb.0: @ %entry337; CHECK-NEXT: vldr d16, [r0]338; CHECK-NEXT: vorr q9, q8, q8339; CHECK-NEXT: vzip.32 q8, q9340; CHECK-NEXT: vext.32 q8, q8, q8, #2341; CHECK-NEXT: vst1.64 {d16, d17}, [r1]342; CHECK-NEXT: mov pc, lr343entry:344 %tmp1 = load <2 x i32>, ptr %A345 %0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 0>346 store <4 x i32> %0, ptr %B347 ret void348}349 350define void @vzip_vext_factor(ptr %A, ptr %B) {351; CHECK-LABEL: vzip_vext_factor:352; CHECK: @ %bb.0: @ %entry353; CHECK-NEXT: vld1.64 {d16, d17}, [r0]354; CHECK-NEXT: vext.16 d18, d16, d17, #1355; CHECK-NEXT: vext.16 d16, d18, d17, #2356; CHECK-NEXT: vext.16 d16, d16, d16, #1357; CHECK-NEXT: vstr d16, [r1]358; CHECK-NEXT: mov pc, lr359entry:360 %tmp1 = load <8 x i16>, ptr %A361 %0 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 4, i32 5, i32 3>362 store <4 x i16> %0, ptr %B363 ret void364}365 366define <8 x i8> @vdup_zip(ptr nocapture readonly %x, ptr nocapture readonly %y) {367; CHECK-LABEL: vdup_zip:368; CHECK: @ %bb.0: @ %entry369; CHECK-NEXT: vld1.8 {d16[]}, [r1]370; CHECK-NEXT: vld1.8 {d17[]}, [r0]371; CHECK-NEXT: vzip.8 d17, d16372; CHECK-NEXT: vmov r0, r1, d17373; CHECK-NEXT: mov pc, lr374entry:375 %0 = load i8, ptr %x, align 1376 %1 = insertelement <8 x i8> undef, i8 %0, i32 0377 %lane = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 undef, i32 undef, i32 undef, i32 undef>378 %2 = load i8, ptr %y, align 1379 %3 = insertelement <8 x i8> undef, i8 %2, i32 0380 %lane3 = shufflevector <8 x i8> %3, <8 x i8> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 undef, i32 undef, i32 undef, i32 undef>381 %vzip.i = shufflevector <8 x i8> %lane, <8 x i8> %lane3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>382 ret <8 x i8> %vzip.i383}384 385define <16 x i16> @test_15xi16(ptr %next.gep, ptr %next.gep13) {386; CHECK-LABEL: test_15xi16:387; CHECK: @ %bb.0:388; CHECK-NEXT: add r1, r1, #2389; CHECK-NEXT: mov r2, #4390; CHECK-NEXT: vld1.16 {d16, d17}, [r1], r2391; CHECK-NEXT: vld1.16 {d18, d19}, [r1]392; CHECK-NEXT: vzip.16 q8, q9393; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]!394; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128]395; CHECK-NEXT: mov pc, lr396 %a = getelementptr inbounds nuw i8, ptr %next.gep, i32 2397 %b = load <15 x i16>, ptr %a, align 2398 %c = getelementptr inbounds nuw i8, ptr %next.gep, i32 6399 %d = load <15 x i16>, ptr %c, align 2400 %interleaved.vec = shufflevector <15 x i16> %b, <15 x i16> %d, <16 x i32> <i32 0, i32 15, i32 1, i32 16, i32 2, i32 17, i32 3, i32 18, i32 4, i32 19, i32 5, i32 20, i32 6, i32 21, i32 7, i32 22>401 ret <16 x i16> %interleaved.vec402}403