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1; RUN: llc -mtriple=armv8 -mcpu=cyclone < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOTSWIFT2; RUN: llc -mtriple=armv8 -mcpu=swift < %s | FileCheck %s3; RUN: llc -mtriple=armv8 -mcpu=cortex-a57 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOTSWIFT4 5declare arm_aapcs_vfpcc void @take_vec64(<2 x i32>)6 7define void @test_vec64() {8; CHECK-LABEL: test_vec64:9 10 call arm_aapcs_vfpcc void @take_vec64(<2 x i32> <i32 0, i32 0>)11 call arm_aapcs_vfpcc void @take_vec64(<2 x i32> <i32 0, i32 0>)12; CHECK-NOTSWIFT-NOT: vmov.f64 d0,13; CHECK: vmov.i32 d0, #014; CHECK: bl15; CHECK: vmov.i32 d0, #016; CHECK: bl17 18 ret void19}20 21declare arm_aapcs_vfpcc void @take_vec128(<8 x i16>)22 23define void @test_vec128() {24; CHECK-LABEL: test_vec128:25 26 call arm_aapcs_vfpcc void @take_vec128(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)27 call arm_aapcs_vfpcc void @take_vec128(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)28; CHECK-NOT: vmov.f64 [[ZEROREG:d[0-9]+]],29; CHECK: vmov.i32 q0, #030; CHECK: bl31; CHECK: vmov.i32 q0, #032; CHECK: bl33 34 ret void35}36 37declare void @take_i32(i32)38 39define void @test_i32() {40; CHECK-LABEL: test_i32:41 42 call arm_aapcs_vfpcc void @take_i32(i32 0)43 call arm_aapcs_vfpcc void @take_i32(i32 0)44; CHECK-NOTSWIFT-NOT: vmov.f64 [[ZEROREG:d[0-9]+]],45; CHECK: mov r0, #046; CHECK: bl47; CHECK: mov r0, #048; CHECK: bl49 50; It doesn't particularly matter what Swift does here, there isn't carefully51; crafted behaviour that we might break in Cyclone.52 53 ret void54}55